JPH04182986A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To decrease the electric power to be consumed at the time of initiation of bit lines and to prevent the increase of the potential of a grounding line by disconnecting one step of the bit lines which are not selected and in an inert state in the mid-way. CONSTITUTION:The semiconductor memory device which is disposed with 1st and 2nd signal lines along the rows and lines of memory cells, connects these lines to the respective memory cells, and assigns the rows and lines of the memory cells by the selection of these 1st and 2nd signal lines is provided with switch means 20 for disconnecting the circuits of the 1st signal lines in the mid-way of the 1st signal lines to disconnect a part or the whole of the non-selected 1st signal lines in the mid-way of the signal lines. The capacity of the bit lines connected to the non-selected memory cells is decreased in this case. The discharge electric power flowing from the bit lines to the non- selected memory cells is decreased and the electric power to be consumed at the time of the initialization of the bit lines is decreased. In addition, the temp. rise of the grounding line to which the respective memory cells are connected is suppressed and the malfunction of the memory cells is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a semiconductor memory device such as a RAM, and particularly to the structure of a signal line connected to a memory cell.

(b) Prior Art FIG. 5 is a circuit diagram schematically showing a static type RAM. In this figure, memory cells arranged in 4 rows and 4 columns are illustrated for the sake of simplification.

A plurality of memory cells (10) arranged in rows and columns are connected to word lines WL arranged in the row direction, and further connected to bit lines BL arranged in the column direction. The word line WL is
A decoder (1) consisting of a combination of logic gates (11)
2) and manually powered by this decoder (12).
It is specified alternatively according to bit address data Y1 and Y2. A predetermined potential is applied to a designated word line WL, and the memory cells (
10) are respectively connected to the bit line BL.

On the other hand, the bit line BL is connected to the data line DL via a MOS transistor (13) and to a power supply via a MOS transistor (14).
When the transistor (13) is turned on, the bit line BL is connected to the selective data line DL. A high power of a decoder (16) consisting of a combination of logic gates (15) is applied to the gate of the MOS transistor (13), and according to the 2-pin address data X1 and X2 input to the decoder (16). Alternatively, a MOS l-transistor (
13) is turned on. The data line DL is connected to the memory cell JL (
10) is connected to the sense amplifier that judges the data or the write driver that writes data to the memory cell (10), and when the MOS l-lasigister (13) is turned on and the bit line BL is connected to the data line DL. , a specific memory cell (10) is connected to a sense amplifier and a write driver.

The bit line BL is connected to the gate of the MOS transistor (17) connected between the MOS transistor (14) and the pair of bit lines 81 in order to initialize the focus line BL.
An inverted clock 7 of the clock φl that sets the active period of the clock φl;
1 is applied, the power supply potential is not applied to the pair of bit lines BL except during the active period of the bit line BL, and the bit line BL is initialized. Further, the logic gates (11>(15) of the decoders (12) and (16) are supplied with clocks φ2 and φ3 that set the period in which the word line WL and bit line BL are designated, and these clocks φ2 and φ3 The high voltage of each decoder (12016) is set to the word line WL within the period set by
and bit line BL.

FIG. 6 is a circuit diagram showing the configuration of each memory cell (10).

Each memory cell (10) has four MOS transistors (+>(2>(3) (4) and two resistors (5)).
(6), the drains and gates of MOS transistors (1) and (2) are connected to each other, and the drains are connected to the power supply through the respective resistors (5H6), and the sources are grounded to form a bistable type. A fritub flop is constructed. Furthermore, the drains of the MOS transistors (1) and (2) are connected to the bit line BL via the MOS transistors (3) and (4), and the gates of the MOS transistors (3) and (4) are connected to the word line WL. Ru.

Therefore, a specific memory cell (1
0) is specified, for example, that memory cell (10)
is connected to the sense amplifier via the bit line BL and data line DL, and the stored data is read out through the sense amplifier.

(c) Problems to be Solved by the Invention However, in the memory cell (10) as described above, the word line WL is selected and the MOS transistors (3) and (4) of the corresponding memory cell (10) are turned on, the bit line BL to MO
Since a discharge current flows to the ground side through the S) transistors (1) and (3) or the MOS transistor (2H4), the potential of the pinto wire B is pulled down to the ground potential.

Therefore, the power consumed when turning on the MOS transistors (14) and (17) to initialize the bit line BL increases, and the potential of the ground line rises due to the current flowing into the ground line, causing the memory cell (10) etc. may malfunction. The influence of such a discharge current flowing into the ground line increases as the number of rows and columns of memory cells (10) increases, and therefore becomes noticeable in a large-capacity memory device.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device that reduces power consumption, prevents potential rise in a ground line, and is suitable for increasing capacity.

(2) Means for Solving the Problems The present invention has been made to solve the above-mentioned problems, and is characterized in that a plurality of memory cells are arranged in columns and rows, and First and second signal lines are arranged along the columns and rows of memory cells and are connected to each memory cell, and selection of the first and second signal lines specifies the column and row of the memory cells. In the semiconductor memory device, a switch means for circuitly dividing the first signal line is provided in the middle of the first signal line, and a part or all of the unselected first signal line is disconnected. The problem lies in dividing the signal line in the middle.

(E) Effect According to the present invention, by dividing a part of the unselected bit line which is in an inactive state in the middle, the capacitance of the unselected bit line is reduced, and the capacitance of the unselected bit line is reduced. The inflowing discharge current decreases.

Therefore, the power consumed during bit line initialization can be reduced, and the potential of the ground line can be prevented from rising.

(f) Example An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of the semiconductor memory device of the present invention, and FIG. 2 is a timing diagram showing its operation.

A plurality of memory cells (10) are arranged in the row and column directions, and a word line WL and a bit line BL are arranged along each row and column.
are associated with each other. These word lines WL and bit lines BL are connected to corresponding memory cells (1o), respectively.
As in FIG. 5, it is alternatively designated by the outputs of the decoders (12) and (16).

An analog switch (2o) that divides the bit line BL into two is provided in the middle of the bit line BL, and this analog switch (20) is controlled to open and close based on address data x1 for selecting the bit line BL. This analog switch (20) is turned on when the bit line BL is selected to connect each memory cell (1o) to the data line DL, and is turned off when the bit line BL is not selected to separate the bit line BL. 0 For example, when there are 4 columns of memory cells (1o), the analog switch (20) is configured to operate in two pairs on the right side and two pairs on the left side in different systems, and the memory cells in the two columns on the right side (]0) is specified, the two pairs of analog switches (20) on the left side are turned off to separate the two pairs of bit lines BL on the left side, and when the two columns of memory cells (10) on the left side are specified, the two pairs of analog switches (20) on the right side are turned off. 20) is turned off, dividing the two pairs of bit lines BL on the right side. That is, each analog switch (2o) is given the output of a logic gate (21) that receives address data Xl, and the analog switch (20) is opened or closed according to the selection of the bit line BL.

In addition, a clock φ1 that sets the active period of the bit line BL is input to the logic game (21) that provides an output to the analog switch (2o), and when the bit line BL is initialized, each analog switch (2o) ) is configured to turn on. Therefore, when initializing the bit line BL,
Regardless of the address data X1, I2, the analog switch (20) is turned on and the power supply potential is supplied to the entire bit line BL.

As shown in FIG. 2, the clock φI that sets the active period of the bit line BL rises a while after the address ADR changes, and later, the clocks φ2 and φ3 sequentially rise. Therefore, when an address is specified and the bit line BL is activated, the output of the decoder (I2) is applied to the word line WL to specify the row of memory cells (lO), and then the output of the decoder (16) is applied to the word line WL. A column of memory cells (10) is designated by being applied to a MOS transistor (13) connected to the bit line BL. At this time, half of the bit line BL corresponding to the half column on the unspecified memory cell (10) side is separated because the analog switch (20) provided in the middle is turned off. memory cell (10) in the column specified by word line WL.
) will be separated from the Therefore, among the rows of memory cells (10) designated by the word line WL, the memory cells (10) that are not designated by the bit line BL are
Since half of the bit lines B are connected, the capacitance of the bit lines BL is substantially halved, and the discharge current flowing from the bit lines BL to the memory cells (10) is reduced.

By the way, when the bit line BL is divided by the analog switch (2o), the rise in potential on the data line DL side may be delayed during initial setting, but as shown in FIG.
By adding a precharge circuit to the bit line BL on the data line DL side of the analog switch (2o), the bit line B
It becomes possible to quickly complete the initial setting of L. That is, a MOS transistor (22) that applies a power supply potential to the data line DL side of the analog switch (2o) and a MOS transistor (23) that short-circuits the pair of bit lines BL are provided, and the gate of each MO3 transistor (22N23) is provided. By applying an inverted clock 7;I to the data line DL of the analog switch (20) during the initial setting period of the bit line BL.
The configuration is such that the power supply potential is also applied to the side bit line BL.

FIG. 4 is a circuit diagram showing another embodiment of the present invention. In this figure, a memory cell (1o), a decoder (12)
(16) and the analog switch (2o) itself
It is the same as the figure, and the same parts are denoted by the same reference numerals.

゛The analog switch (20) connects memory cells in even columns (
The bit line BL corresponding to the (10) column and the bit line BL corresponding to the odd column memory cell (10) column are configured to operate separately.
> is specified, the bit line BL to which the memory cell (10) in the odd column is connected is disconnected, and conversely, when the memory cell (10) in the odd column is specified, the memory cell (10) in the even column is connected. The bit line BL that is connected is divided.

According to such a configuration, the capacitance of the bit line BL connected to the memory cells (10) on both sides of the memory cell (10) specified by the address data is halved, so the bit line is transferred to the unselected memory cell (10). The discharge current flowing from line BL decreases. Generally, the ground line of each memory cell (10) is provided along the row of memory cells (10), so if the discharge current flowing into the memory cells (10) adjacent in the row direction is reduced, the potential of the ground line The effect of the increase is less likely to affect the selected memory cell (10).

Therefore, as shown in FIG. 1, bit line B1. The possibility of malfunctions occurring due to a rise in the potential of the ground line is lower than when dividing the line into left and right halves.

In this embodiment, the bit line BL is divided into two for memory cells (10) arranged in 4 rows and 4 columns. However, when the number of rows of memory cells (10) increases, the bit line BL B
It is also possible to divide L into four or eight parts, and the method of dividing the bit lines BL may be appropriately set according to the number of memory cells (]O).

(G) Effects of the Invention According to the present invention, since the capacitance of the bit line connected to the unselected memory cell can be reduced, the discharge current flowing from the bit line to the unselected memory cell can be reduced.
The power consumed when initializing the bit line can be reduced, and the rise in potential of the ground line to which each memory cell is connected is suppressed, thereby preventing memory cells from malfunctioning.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a timing diagram of the operation of Fig. 1, Fig. 3 is a circuit diagram when a precharge circuit is provided in the middle of the bit line, and Fig. 4 is a circuit diagram of an embodiment of the present invention. FIG. 5 is a circuit diagram of another embodiment of the present invention, FIG. 5 is a circuit diagram of a conventional semiconductor memory device, and FIG. 6 is a circuit diagram of a memory cell. (1) to (4)-MOS) transistor, (5) (6)
Resistance, (lO) Memory cell, (11) (+51
Logic gate, (12m6) Decoder, (13
) (14) (17) (22) (23) - MOS) transistor, (20) analog switch, <21)
logic gate.

Claims (2)

[Claims] (1) A plurality of memory cells are arranged in columns and rows, and first and second memory cells are arranged along the columns and rows of the memory cells.
In a semiconductor memory device in which signal lines are arranged and connected to each memory cell, and the column and row of the memory cell are specified by selection of the first and second signal lines, the first signal A semiconductor memory characterized in that a switch means for circuit-wise dividing the line is provided in the middle of the first signal line, and part or all of the unselected first signal line is divided in the middle of the signal line. Device. (2) The switch means provided on the first signal line,
2. The semiconductor memory device according to claim 1, wherein said first signal line is selectively opened and closed according to address information for selecting said first signal line.