JP2940175B2 - Decoder circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder circuit,
In particular, the present invention relates to a structure of a decoder circuit used for driving a word line of a dynamic random access memory (hereinafter referred to as DRAM).

[0002]

2. Description of the Related Art In order to achieve high integration of semiconductor memories, the dimensions of elements are being reduced further. At present, one-transistor one-capacitor type cells are mainly used for DRAM memory cells, and in order to reliably write a potential to the storage capacity of the memory cell, it is necessary to secure a sufficient write voltage. . For that purpose, the potential of a word line connected to a gate transistor constituting a memory cell must be driven sufficiently higher than a threshold voltage of the gate transistor. Therefore, a decoder circuit for selecting and driving an arbitrary word line has been devised.

A conventional decoder circuit can be roughly classified into a logic circuit that determines an input address signal and outputs a signal of a predetermined level when the address signal matches, and the conduction is controlled according to the output of the logic circuit. And a word line drive transistor. In the word line drive transistor, one of a source and a drain is connected to an input terminal of a clock signal for writing, the other is connected to a word line, and an output of the above-described logic circuit is applied to a gate.

Generally, an N-channel transistor has been used as the word line driving transistor. Therefore,
In order to drive a word line with a clock signal, a high-level voltage must be applied to the gate of a word line drive transistor to make the transistor conductive. For example, when the most common power supply voltage of 5 V is used, in order to write a 5 V potential to a memory cell, the word line must be set to about 7 V to compensate for a threshold voltage of a gate transistor of the memory cell. Therefore, the clock signal supplied to the word line is 7 V
In order to make the word line driving transistor connected to the word line conductive, a higher voltage of about 9 V, which is a higher voltage, is applied to the gate of the transistor by the bootstrap circuit.

However, under the current situation where the gate insulating film and the like of a transistor are thinned due to high integration and the withstand voltage of the element is decreasing, there is a problem that such high voltage causes deterioration of reliability. Was.

Therefore, in recent years, a P-channel transistor has been used as a word line driving transistor so that a word line can be set to a high voltage without applying a high voltage to a gate. That is, since the word line drive transistor is a P-channel transistor, a low level voltage is applied to its gate to make it conductive, and in the above example, the voltage applied to the gate of this transistor needs to be 5 V at the maximum. become.

[0007]

However, since a P-channel transistor is formed in an N-well provided in a P-type substrate, a PN junction is formed between the P-type substrate and the N-well. Therefore, the N-well must be at a high voltage when the transistor is conductive so that the PN junction does not become forward biased. Conventionally, a clock signal for writing is used as a voltage source for making the N-well a high voltage.

As described above, if this transistor is a P-channel transistor so that a high voltage is not applied to the gate of the word line driving transistor, a clock signal for writing can be generated not only by the word line driving transistor but also by the word line driving transistor. , N wells.

When an N-channel transistor is used as the word line driving transistor, the load capacitance of the clock signal for writing is mainly the capacitance of the source or drain diffusion layer of each transistor, but is not the P-channel transistor. When a transistor is used, an N-well diffusion layer capacitance is added in addition thereto, and the total load capacitance of a clock signal for writing is several times as large as that in a case where an N-channel is used.

It is difficult to drive such a large capacitive load at high speed. Therefore, there is a problem that the speed of the clock signal for writing decreases, and as a result, the rise of the word line level is delayed.

It is therefore an object of the present invention to provide a decoder circuit which can control the driving of a word line without using a high voltage signal and can drive the word line at high speed. It is in.

[0012]

According to the present invention, there is provided a decoder circuit comprising: a P-type region; an N-type well provided in the P-type region; and a level provided in the N-type well according to an address signal. between the source and drain to input a signal to the gate
A channel is provided between a word line and an input end of a signal for driving the word line, and a P-channel type word line driving transistor, and the N-type well is connected to a bias signal different from a signal for driving the word line. Means for biasing, wherein the bias signal has a higher voltage than a signal of a level corresponding to the address signal, and the transistor provided in the N-type well is provided with the P-channel type word line drive transistor. It is characterized by being limited.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.
First, the configuration and operation of the entire semiconductor memory device including the decoder circuit of the present invention will be described with reference to FIGS. Here, a 16 Mbit DRAM will be described as an example. This semiconductor memory device is formed on one P-type substrate, the memory cells are formed by N-channel MOS transistors, and the peripheral devices are formed by CMOS circuits. The memory cell 10 includes 16,777,216 cells divided into 2,048 rows and 8,096 columns, and each cell includes one N-channel MOS transistor and one capacitance element. The cell is configured,
It is formed of a so-called 1-transistor 1-capacitor type cell.

The X decoder 12 selects one of the 2048 word lines and the Y decoder selects one of the 8096 bit lines according to the address signal supplied from the address buffer 11, respectively. These address signals are transmitted from twelve address lines 16 to the address buffer 11.
Are supplied in a time-sharing manner.

When a row active RAS signal is input (see FIG. 2A), the clock generator 15
0 is supplied to the address buffer 11 (see FIG. 2B), and the row address is supplied from outside to the address buffer 11 (see FIG. 2C). The bias signal φ2 (FIG. 2 (d) or (e)) according to the present invention is supplied to the X decoder 12, and as described later, the N well in which the word line driving transistor forming the X decoder is formed has a high voltage. Be biased. A row address signal is applied from the address buffer 11 to the X decoder 12, and a signal φ1 for driving a word line is supplied from the clock generator 15 to the X decoder 12 (see FIG. 2 (f)), and is selected by the row address signal. The word line thus set attains a high level (see FIG. 2G). The sense amplifier 14 senses and amplifies the bit line to a high level or a low level according to the information of 0 or 1 stored in the memory cell connected to the selected word line (see FIG. 2 (h)).

Next, a row active CAS signal is input (see FIG. 2 (i)), the clock generator 15 supplies φc0 to the address buffer 11 (see FIG. 2 (j)), and the column address is changed to the Y decoder 13 (See FIG. 2 (k)). Next, a signal φc1 for driving a column select line for selecting a bit line is supplied from the clock generator to the Y decoder 13 (see FIG. 2 (l)), and the selected column select line goes high (FIG. 2). (M)).

By the above operation, one cell corresponding to the input address is connected to one bit line selected by the column select line.

Here, in the case of the read operation, the information of the selected cell corresponds to the high or low level state of the selected bit line, so that the level of this bit line is set to the I / O selector 17. , And output from the output buffer 18 to the output terminal Dout. On the other hand, if it is a write operation,
The data input from the input terminal Din is input to the input buffer 19.
Through the I / 0 selector 17, the level of the selected bit line is forced to the high level or the low level, and the data is written to the cell.

When the read or write operation is completed, R
The AS and CAS signals become high level, that is, non-active. Correspondingly, φ0, φ1, φ2 (in the case of FIG. 2 (e)), φC0, φC1 sequentially become low level, and one writing or The cycle of the read operation ends.

Among these operations, in particular, the write operation is performed when the data of the memory cell in which the low level has been stored is rewritten to the high level, or vice versa. In some cases, the opposite data must be written to the memory cell. In this case, the potential must be reliably written to the storage capacity of the memory cell. For this purpose, the potential of the word line connected to the gate transistor constituting the memory cell must be driven sufficiently higher than the threshold voltage of the gate transistor and at a high speed. Thus, the present invention has achieved this object by devising the configuration of the X decoder 12. This will be described with reference to FIGS.

FIG. 3 is a circuit diagram showing a configuration of the X decoder shown in FIG. The X decoder circuit determines a row address supplied from the address buffer 11 (FIG. 1), and outputs a low-level signal when the row address matches.
, Nn, and word line drive transistors Q0, Q1, Q2, Q3,..., Qn-1, Qn whose conduction is controlled in accordance with the output of the NAND circuit.

The word line driving transistors Q0 and Q
1, Q2, Q3,..., Qn-1, Qn, have their sources connected to the input terminal of the clock signal φ1 for driving the word lines, and have their drains connected to the word lines W0, W1, W2, W3,.
... Connected to Wn-1 and Wn, respectively, with NAN at the gate
It is a P-channel transistor to which outputs G0, G1, G2, G3... Gn-1, Gn of D circuits N0, N1, N2, N3. Since the word line drive transistor is a P-channel transistor, when this transistor is turned on and φ1 is applied to the word line, a low-level voltage (eg, 0 V) may be applied to the gate of the word line drive transistor. Become.
When not selected, a voltage (for example, 5 V) for turning off the word line drive transistor may be applied to the gate of the word line drive transistor. Therefore, even if the word line is set at a high potential (for example, 7 V) to ensure writing, it is not necessary to increase the gate voltage of this transistor (for example, 5 V), and the reliability of the transistor such as breakdown of the gate insulating film is reduced. Fear is reduced.

Φ1 is a clock signal for driving a word line and writing data to a memory cell.
Is supplied from the clock generator 15 (FIG. 1) after being supplied to the address buffer 11 (FIG. 2B).
(F)). This φ1 is for surely writing,
This is a high-potential (for example, 7 V) clock signal.

Since the semiconductor memory device including the decoder circuit is formed on a P-type substrate, an N-well must be provided in order to form a P-channel transistor, and a transistor must be formed therein. No.
In this embodiment, all the word line drive transistors Q0, Q1,... Are formed in one N well NW1.

As described above, when an N well is formed in a P substrate, a PN junction is formed between the P type substrate and the N well. Therefore, the N-well must be at a high voltage when the transistor is conducting so that the PN junction does not become forward biased.

Therefore, the inventor of the present invention does not use a clock signal φ1 for driving a word line as in the prior art as a means for biasing the N-well NW1 to a high voltage state, but uses another bias signal φ2 as an N. It was found to apply to the wells. With such a configuration, the load of φ1 is reduced because the clock signal φ1 for driving the word line is not used for biasing the N-well. Therefore, according to the present invention, word line driving can be performed at a higher speed than in the conventional case.

Referring to the plan view of FIG. 4 showing the pattern configuration of word line drive transistors Q0 to Q4 in the decoder circuit shown in FIG. 3, and FIGS. 5A and 5B which are sectional views thereof. An example of a wiring pattern of the bias signal φ2 will be described. The same components as those in FIG. 3 are denoted by the same reference numerals. An N well NW1 is provided on a P-type substrate 51,
Word line drive transistors Q0,
Q1... Are provided.

(Not shown) Word line drive transistors Q0, Q1 receiving signals from NAND circuits N0, N1.
Are formed of a polycrystalline silicon film, and are arranged on the N well NW1 with a gate oxide film 53 interposed therebetween. A clock signal φ1 for driving a word line and performing writing or the like on a memory cell extends in a word line direction from a wiring Lφ1 running in a direction perpendicular to the word line direction, and one clock signal φ1 for two word line driving transistors. SL0, SL made of an aluminum layer which are wired one by one
1 are supplied. The wirings SL0, SL1,... Become the source electrodes of the gate line driving transistors Q0, Q1,.
Therefore, two gate line driving transistors (for example, Q
(0, Q1). The source electrodes SL0, SL1,...
1, P-type diffusion regions s0, s1,.
And a plurality of contact holes.

On the other hand, the gate line driving transistors Q0 and Q
.. Are provided for each transistor. Therefore, the drain electrodes DL0, DL1,.
Is arranged. Similarly, the drain electrodes DL0, DL1,... Are also connected to the P-type diffusion regions d0, d1,. Further, the drain electrodes DL0, D
Are connected to word lines W0, W1,... Made of a lower polycrystalline silicon layer by contact holes C0, C1,.

The signal .phi.2 for biasing the N-well NW1 extends in the word line direction from a wiring L.phi.2 running over the word lines W0, W1,... In a direction perpendicular to the word line direction, and includes two word line driving transistors. Wirings BL0 and BL1 made of an aluminum layer, one for each wiring
... Are connected to the N ⁺ -type diffusion regions N0, N1... In the N well NW1 by a plurality of contact holes, respectively, and bias the N well NW1 to a high voltage.

Referring to FIGS. 5A and 5B, an element formation region is defined by a field oxide film 51 in an N well NW1 provided on a P-type substrate 51. By diffusing P-type or N-type impurities into these element formation regions, P-type diffusion regions s0 serving as a common source of word line driving transistors Q0 and Q1, and P-type diffusion regions d0 and d1 serving as drains thereof, respectively. And N-type diffusion regions N0 and N1
Are formed. Word line drive transistors Q0, Q
One gate electrode G0, G1 is arranged on N well NW1 via a gate oxide film 53. Clock signal φ1
Is connected to a P-type diffusion region s0 via a contact hole.
In addition, DL0 and DL1 made of an aluminum layer connected to the word lines W0 and W1 are connected to P-type diffusion regions d0 and d1 via contact holes. Further, BL0 and BL1 made of an aluminum layer to which a bias signal signal φ2 for biasing the N well NW1 is supplied are connected to the N-type diffusion layers N0 and N1 through contact holes.
Thereby, N well NW1 is biased to a high voltage.

FIG. 4 shows an example of a wiring pattern for supplying a bias signal φ2 for biasing the N well NW1.
Various wiring patterns are possible by changing the method of contact with the well and the like. Another wiring pattern example will be described with reference to FIGS. Note that the pattern of the word line driving transistor is the same as that of FIG.

The example of the pattern shown in FIG.
2 are connected to N ⁺ -type diffusion regions necessary for biasing N wells, specifically, aluminum wirings BL10 to which a bias signal φ2 is supplied by contact holes.
The N ⁺ type diffusion regions N10 are arranged at the source / drain regions d0, s of the word line driving transistors Q0, Q1,.
It is characterized in that it is not parallel to 0, d1, s1,. In the example of FIG. 4, the N ⁺ type diffusion region N
Are formed in the formation region of the word line drive transistor, the area of the entire formation region increases accordingly. In this example, however, the N ⁺ type diffusion region N1
Regions 0... Do not affect the entire area of the word line drive transistor formation region, and thus have the effect of reducing the area accordingly.

Next, FIG. 7 shows an example of a pattern in a case where a so-called multilayer wiring technique using two layers of aluminum wiring or aluminum wiring and silicide wiring is used. In this example, a wiring Lφ1 to which a clock signal φ1 for driving a word line and writing data into a memory cell or the like is supplied is arranged on a word line driving transistor formation region by a multilayer wiring technique. For example, when the aluminum wiring is a two-layer wiring, if the wiring Lφ1 is the second aluminum wiring of the upper layer wiring, the wiring pattern shown in the figure can be obtained. In this case, the bias signal φ2 can be directly connected from Lφ2 made of the first aluminum wiring to the N-type diffusion layer N21 via the contact hole to bias the N-type well to a high voltage.

The drain electrodes DL0, DL1,...
Is formed of a silicide wiring instead of an aluminum wiring, the wiring Lφ1 can be arranged on the word line drive transistor region by a single layer of aluminum wiring without forming a two-layer aluminum wiring.

Further, as an example of a pattern using a multilayer wiring technique, a wiring Lφ2 to which a bias signal φ2 is supplied is shown in FIG.
The wiring pattern similar to Lφ1 shown in FIG.
φ2 can be a wiring made of silicide.

Next, a circuit for generating a signal φ2 for biasing the N well to a high voltage will be described. This signal φ2 is generated from the clock generator 15, as shown in FIG. Since the clock generator 15 is a circuit for generating a plurality of clock signals (φ0, φ1, φ2, φC0, φC1, etc.), it is composed of a plurality of clock generation circuits. One of the plurality of clock generation circuits has φ
There are also two generator circuits.

Since the purpose of φ2 is to bias the N-well for forming the word line driving transistor to a high voltage, it may be a DC signal that always supplies a high voltage. FIG. 8 shows an example of a high voltage generating circuit for generating such a DC signal. In this circuit, an N-type transistor T0 having a drain and a gate connected to a power supply terminal (for example, 5 V) and a source connected to a node A, a gate and a drain connected to the node A, and a source connected to the φ2 output terminal N-channel transistor T1 and oscillator 4
And one end is connected to the output end of the oscillator 4 and the other end is connected to the node A.
Is a so-called charge pump circuit composed of a capacitor C1 connected to the capacitor C1. With this circuit, for example, if the power supply voltage is 5V, a high voltage signal φ2 of about 7V is always applied to the N well. Φ2 in this case is shown in FIG.
This corresponds to that shown in FIG. Note that this charge pump circuit is an example, and the object of the present invention can be achieved by any high voltage generation circuit that supplies a DC voltage higher than the power supply voltage.

Although the φ2 generation circuit shown in FIG. 8 always generates a high-voltage DC signal, it is necessary to bias the N-well to a high voltage in order to reduce power consumption. A signal having only a high voltage, that is, a clock signal as shown in FIG.
In this case, since φ2 is a signal for preventing the clock signal φ1 for driving the word line and performing writing or the like to the memory cell from being involved in biasing the N-well to a high voltage, φ1 is at a high level. Before it becomes high, the N-well must be biased to a high voltage.

FIG. 9 shows an example of a high voltage clock generating circuit for generating such a clock signal φ2. This circuit supplies a signal which becomes high level earlier than φ1 to one end of the capacitor C2, for example, supplies φ0 to charge the capacitor C2, and drives B at the other end by a signal delayed by φ0 by the delay circuit 3. It has become. FIG. 10 shows a rising state of φ2. As shown in FIG. 10, when the signal delayed by the delay circuit 3 is applied to B, the charging voltage of the capacitor C2 increases, and the voltage higher than the power supply voltage (for example, 7V) becomes φ2
Supplied as With such a configuration, the N well can be biased to a high voltage before φ1 becomes a high level. The signal for making φ2 is φ
It should be made based on the signal that goes to high level earlier than 1.
It need not be φ0. Since the purpose of φ2 is to bias the N well to a high voltage, it is not necessary to control the rising timing strictly as in φ1. Therefore, the rise timing has a degree of freedom, and the present invention also has an advantage that the circuit design is easy. Further, the circuit configuration of the high-voltage clock generation circuit is an example, and the object of the present invention is achieved by a circuit that generates a high-voltage clock signal that rises faster than φ1.

As described above, according to the present embodiment,
By supplying a bias signal φ2 different from the clock signal φ1 for writing to the N well in which the word line driving transistor is formed, the word driving transistor is supplied to the P-channel without fear of gate insulating film destruction due to application of a high voltage. Since the transistor can be a type transistor, and the clock signal φ1 for writing does not have an extra capacitive load, the word line can be driven at high speed.

In the embodiment described above, the semiconductor memory device is provided on the P-type substrate and one N well is formed thereon. However, the present invention is limited to one N well. However, the same effect can be obtained even when divided into a plurality of wells by supplying a bias signal to each well. Further, the present invention is not limited to the example provided on the P-type substrate. For example, a P-well is provided on an N-type substrate and a semiconductor memory device is formed in the P-well.
Further, a so-called double well in which an N well is provided in the P well may be provided, and a word line drive transistor may be formed therein. In this case, the P well corresponds to the P-type region according to the present invention.

The present invention is not limited to a decoder circuit for a DRAM, but may be, for example, an SRAM (static RA).
M), PROM (programmable read)
only memory), EPROM (erasab)
le PROM), EEPROM (electrica)
For example, the present invention is also applicable to an all-easy programmable PROM.

[0044]

As described above, the decoder circuit of the present invention supplies word bias to the N-well where the word line driving transistor is formed by supplying a bias signal different from a clock signal for writing. The transistor can be a P-channel transistor without the risk of gate insulating film destruction due to the application of a high voltage, and the word line can be driven at high speed because no extra capacitive load is applied to the clock signal for writing. It became possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device including a decoder circuit of the present invention.

FIG. 2 is a timing chart for explaining an operation of the semiconductor memory device shown in FIG. 1;

FIG. 3 is a circuit diagram illustrating an example of a decoder circuit of the present invention.

FIG. 4 is a plan view showing a part of a wiring pattern of the decoder circuit shown in FIG. 3;

5 is a sectional view taken along line XX and a line YY of FIG. 4;

FIG. 6 is a plan view showing another wiring pattern of a part of the decoder circuit shown in FIG. 3;

FIG. 7 is a plan view showing still another wiring pattern of a part of the decoder circuit shown in FIG. 3;

FIG. 8 is a circuit diagram showing an example of a high voltage bias circuit.

FIG. 9 is a circuit diagram showing another example of the high voltage bias circuit.

FIG. 10 is an operation waveform diagram of the circuit shown in FIG. 9;

[Explanation of symbols]

 Reference Signs List 10 memory cell 11 address buffer 12 X-decoder 13 Y-decoder 14 sense amplifier 15 clock generator 17 I / O

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/8242 G11C 17/00 304B

Claims (17)

(57) [Claims] 1. A P-type region and the P-type and N-type well which is provided in the region, the N-type provided within the well and enter the level of the signal corresponding to the address signal to the gate source and drain
A channel between the gates is provided between a word line and an input end of a signal for driving the word line, and a P-channel type word line driving transistor is provided. The N-type well is different from a signal for driving the word line. Means for biasing with a bias signal, wherein the bias signal has a higher voltage than a signal of a level corresponding to the address signal, and the transistor provided in the N-type well comprises a P-channel type word line. A decoder circuit which is limited to a driving transistor. 2. The decoder circuit according to claim 1, wherein a signal inputted to the gate of said word line driving transistor is generated by a logic circuit which receives an address signal and outputs a voltage of a level corresponding to the address signal. 3. The decoder circuit according to claim 1, wherein the same number of the word line drive transistors as the word lines are provided in the N-type well. 4. The decoder circuit according to claim 1, wherein said bias signal is a DC signal. 5. The decoder circuit according to claim 1, wherein said bias signal generating circuit is a high voltage generating circuit using a charge pump. 6. A P-type region, an N-type well provided in the P-type region, and a signal provided at a level corresponding to an address signal provided in the N-type well to a gate, and a source and a drain are provided.
A channel between the gates is provided between a word line and an input end of a signal for driving the word line, and a P-channel type word line driving transistor is provided. The N-type well is different from a signal for driving the word line. Means for biasing with a bias signal, wherein the transistor provided in the N-type well is limited to the P-channel type word line drive transistor, and the bias signal is less than the signal for driving the word line. A decoder circuit, which is also a clock signal which has a high voltage before. 7. A circuit for generating a high voltage signal based on an internal clock signal having a high voltage before a signal for driving the word line as the circuit for generating the bias signal. 7. The decoder circuit according to 6. 8. An N-type diffusion region having an impurity concentration higher than that of the N-type well for biasing the bias signal in the N-type well, and the N-type diffusion region and a wiring to which the bias signal is supplied. 2. The decoder circuit according to claim 1, wherein the first and second terminals are connected by a contact hole. 9. The decoder circuit according to claim 8, wherein said N-type diffusion region is provided in said word line drive transistor formation region. 10. The N-type diffusion region has a source and a drain of a different one of the word line driving transistors in the N-well.
9. The decoder circuit according to claim 8, wherein the decoder circuit is provided in a region that is not sandwiched between the diffusion regions that constitute the channels between them. 11. The decoder circuit according to claim 8, wherein the wiring to which the bias signal is supplied is in the same layer as the wiring to which the signal for driving the word line is supplied. 12. The wiring according to claim 8, wherein the wiring to which the bias signal is supplied is an aluminum wiring.
2. The decoder circuit according to 1. 13. The decoder circuit according to claim 8, wherein the wiring to which the bias signal is supplied is a different wiring layer from the wiring to which the signal for driving the word line is supplied. 14. The decoder circuit according to claim 1, wherein said word line is of a DRAM. 15. The decoder circuit according to claim 1, wherein said word line is of an SRAM. 16. The decoder circuit according to claim 1, wherein said word line is of an EPROM. 17. The decoder circuit according to claim 1, wherein said word line is of an EEPROM.