KR0151060B1 - Semiconductor memory device and tis manufacturing process - Google Patents

Abstract

Disclosed are an SRAM cell and a method of manufacturing the same. Increasing the density of SRAM cells and accompanying cell size decreases the capacitance of cell storage nodes. As a result, reliability problems are caused by an increase in the soft error rate (SER). Thus, the present invention discloses a method that can increase storage node capacitance, which is essential for highly integrated products. First, by forming a TFT in a storage node region of an SRAM cell adopting a bottom gate TFT, forming a film quality (SiN) having a high dielectric constant to be used as an insulating film of a capacitor, and forming a conductive layer applied with a voltage thereon. The storage node capacitance can be increased by completing a capacitor including an electrode formed of a gate conductive layer and a TFT channel offset and an electrode formed of a conductive layer to which a voltage is applied.

Therefore, the present invention can solve the node capacitance reduction problem that occurs with the reduction of the cell size in the highly integrated SRAM and contribute to the SER improvement.

Description

Semiconductor memory device and manufacturing method thereof

1 is a general circuit diagram of an SRAM cell, and shows an equivalent circuit diagram of a CMOS SRAM using a resistive element P-channel thin film transistor.

2A to 2B are equivalent circuit diagrams of an SRAM cell having increased capacitance of a node when fabricating an SRAM cell according to the present invention.

3A to 3G are layout views showing step by step manufacturing methods of an SRAM cell according to an embodiment of the present invention.

4 is a vertical sectional view of an SRAM cell fabricated by the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to a TFT SRAM (SRAM) device and a manufacturing method thereof.

In general, SRAM as a semiconductor memory device is widely used in the medium and small-capacity memory field because it is lower in memory capacity but faster and easier to use than DRAM (Dynamic Random Access Memory).

The memory cell of the SRAM consists of a structure in which two inverter transistors consisting of two transfer transistors, two drive transistors, and two load elements are coupled (see FIG. 1). It is preserved as the voltage difference between the input and output terminals, that is, the charge accumulated in the floating capacitance in the node. This charge is always supplemented from a constant power supply (Vcc) through a load MOS transistor or a load resistor, which is a load element, so that a refresh function is unnecessary as in DRAM.

On the other hand, the SRAM memory cell is a load element constituting the cell, and although deflation type NMOS transistors are used, they are rarely used today because of their large power consumption. Instead, they have low power consumption and are easy to manufacture. The use of polycrystalline silicon has been mainstream. However, as the memory capacity increases further and the required resistance increases, the difference between the load current supplied from the load cell in the memory cell and the leakage current at the node of the cell decreases. It is a factor that lowers the manufacturing yield of the memory device, and to solve this problem is a CMOS type SRAM using a PMOS TFT as a load element.

FIG. 1 is a general circuit diagram of a conventional SRAM cell, showing a CMOS SRAM using a P-channel thin film transistor (TFT) as a resistor.

An NMOS first transfer transistor (T1) formed at the left side of the cell, the gate of which is connected to a word line, and the drain thereof to a first bit line; An NMOS second transfer transistor (T2) formed at the right side of the cell, the gate of which is connected to the word line, and the drain of which is connected to a second bit line; An NMOS first driving transistor (T3) connected to a source of the first transfer transistor and a drain thereof, the source of which is grounded (Vss), and a gate of the first transfer transistor connected to a source of the second transfer transistor (T2); An NMOS second driving transistor T4 connected to a source of the second transfer transistor T2 and a drain thereof, a source thereof connected to a ground V _ss , and a gate thereof connected to a source of the first transfer transistor T1. ); The drain thereof is connected to the drain of the first driving transistor T3, the source thereof is connected to the constant power line Vcc, and the gate thereof is connected to the gate of the first driving transistor and the source of the second transfer transistor. A P-channel first thin film transistor T5; The drain thereof is connected to the drain of the second driving transistor T4, the source thereof is connected to a constant power line Vcc, and the gate thereof is the gate of the second driving transistor T4 and the first transfer transistor (T4). And a P-channel second thin film transistor T6 connected to the source of T1).

Meanwhile, a method of forming the thin film transistor includes a top gate type in which the gate of the thin film transistor is positioned above the channel and the source / drain, and the gate of the thin film transistor is positioned below the channel and the source / drain. There is a bottom gate type to be formed so as to, and a double gate type to be located above and below.

However, if the thin film transistor is simply configured as a cell according to a conventional manufacturing method, the integration of SRAM (Static Access Memory) is increased, which causes a serious soft error problem during high speed operation. As the size of the SRAM cell decreases, the capacitance of the cell node also decreases, so that the storage node voltage tends to drop as the operation speed increases. This drop causes the surrounding alpha particles to easily cause soft errors.

In other words, this reduction in capacitance results in a reduction in the resistance component to the soft error rate (SER), which greatly affects the reliability of the SRAM.

Accordingly, an object of the present invention is to provide a bottom gate TFT SRAM cell having improved reliability by solving the above problems.

Another object of the present invention is to provide a manufacturing method suitable for manufacturing the bottom gate TFT SRAM cell.

In order to achieve the above object, the present invention has proposed a method for improving SER by increasing the capacitance of a cell node under a bottom gate TFT structure.

Accordingly, in the present invention, in the case of an SRAM cell employing a bottom gate, a method of increasing a node capacitance by forming a conductive layer on a cell storage node is provided.

Specifically, a thin insulating layer, for example, 60 nm silicon nitride (SiN) is laminated on a region composed of a TFT gate and a TFT channel offset of a cell node, and an amorphous silicon or polysilicon conductive layer is formed thereon. By forming a voltage, the node capacitance is increased. When implemented as described above, the equivalent circuit of the cell has an arrangement in which a capacitor is added to the storage node of the cell as shown in FIGS. 2A to 2B. Accordingly, an aspect of the present invention is to provide an SRAM capable of contributing to SER improvement and solving the node capacitance reduction problem that occurs with the reduction of the cell size in a highly integrated SRAM.

According to another aspect of the present invention, there is provided a method including: defining an active region and an inactive region on a semiconductor substrate; Forming a pull down transistor and a pass transistor of an SRAM cell as a first conductive layer in the active region; Forming a second conductive layer constituting a ground line (Vss line) and a word line of the SRAM cell; Forming a third conductive layer constituting a gate of the TFT in the bottom gate TFT; Forming a fourth conductive layer forming a channel of the TFT and a Vcc power line on the gate of the TFT; Depositing an insulating film having a high dielectric constant such as silicon nitride (SiN) to a predetermined thickness as an interlayer insulating film of a capacitor through an oxidation process on the TFT channel; And forming a fifth conductive layer overlapping the node portion of the cell (including the TFT offset region) to increase the storage node capacitance of the SRAM cell thus formed. That is, a TFT SRAM manufacturing method comprising the step of depositing a pattern of the fifth conductive layer to be used as the other electrode of the capacitor with polysilicon or amorphous silicon to a thickness of 1000 Å and then patterning.

In this way, the SRAM cell storage node is formed by forming an insulating film having a high dielectric constant between the electrode formed by the gate conductive layer and the TFT channel offset of the TFT and the electrode formed by the conductive layer formed thereon through the completed SRAM cell structure. Capacitors can be built in to increase the storage node capacitance.

At this time, the voltage applied to the fifth conductive layer used as the electrode of the capacitor is because the conductive layer is not in physical contact with the unit cell of the lower structure, according to the structure of the present invention, if necessary from the ground (Vss) potential You can select up to the power supply (Vcc) potential.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

In the present invention, a method of improving SER by increasing capacitance under a bottom gate TFT structure is proposed.

3a to 3g are layouts showing the step-by-step method of manufacturing an SRAM cell according to an embodiment of the present invention, and FIG. 4 is a view of the SRAM cell fabricated by the steps of FIGS. 3a to 3g. Each vertical cross section is shown.

Specifically, FIG. 3A illustrates a mask layout defining an active area of an SRAM cell. Reference numeral 1 is a semiconductor substrate, and reference numeral 3 is a mask pattern defining an active region.

3B illustrates a layout in which a pull down transistor and a pass transistor of an SRAM cell are formed as a first conductive layer. Specifically, the first contact mask pattern defining the gate mask pattern 5 on the active region mask pattern defined in FIG. 3a to form the driving and transmission pins and to connect the ground line Vss and the word line. Define up to (7).

FIG. 3C shows a layout for forming a second conductive layer constituting a ground line (Vss line) and a word line of a SRAM cell. Specifically, the wiring mask pattern 9 including the contact mask pattern 7 formed in FIG. 3B and forming a second conductive layer serving as a ground line and a word line is defined. In addition, the second contact mask pattern 11 for connecting the cell node and the TFT gate is also defined. Although not shown in the drawing, the bit lines of the transfer transistors are also connected at this stage.

FIG. 3D shows the layout of the third conductive layer constituting the bottom gate of the TFT. Specifically, the gate mask pattern 13 for forming the third conductive layer of the TFT is defined.

3E shows the layout of the fourth conductive layer constituting the channel of the TFT and the Vcc power line. Specifically, the third contact mask pattern 15 for connecting the TFT channel and the cell node is formed on the cell node to electrically connect the TFT channel and the cell node, and then to form the channel layer of the TFT and the Vcc power line. The mask pattern 17 is defined.

3f shows the layout of only the TFTs of the SRAM cells excluding the lower structure, in order to know the shape of the TFT more accurately. Specifically, it is a layout showing only the bottom gate mask pattern 13 of the TFT and the channel and Vcc power line mask pattern 17 of the TFT defined in FIGS. 3D and 3E. After forming the channel of the TFT, an insulating film such as silicon nitride (SiN) having a high dielectric constant is deposited as an interlayer insulating film of a capacitor through an oxidation process on an upper portion of the TFT channel.

FIG. 3G illustrates the layout of the fifth conductive layer overlapping the node region (including the TFT offset region) of the cell on the layout of FIG. 3f in order to increase the storage node capacitance in the SRAM cell thus formed. Specifically, a mask pattern 19 for forming a fifth conductive layer serving as one terminal of the capacitor is defined. The conductive layer to be used as the other electrode of the capacitor is deposited with amorphous silicon or polysilicon at a thickness of 1000 Å and then patterned.

The SRAM cell structure thus completed is formed in the SRAM cell storage node by forming an insulating film having a high dielectric constant between the electrode formed by the gate conductive layer and the TFT channel offset of the TFT and the electrode formed by the conductive layer formed thereon. Capacitors can be formed to increase the storage node capacitance.

4 shows a vertical cross-sectional view of the SRAM formed according to the above steps. Second conductive layer 109 constituting a first conductive layer 150 forming a gate of a pull down transistor and a pass transistor of an SRAM cell, a ground line Vss line, and a word line. ), The third conductive layer 113 constituting the bottom gate of the TFT, the fourth conductive layer 117 constituting the channel of the TFT and the Vcc power line, and the node of the cell on the TFT channel to increase the storage node capacitance. A vertical cross-sectional view of the fifth conductive layer 119 overlapping the region (including the TFT offset region) may be viewed.

In this case, the voltage applied to the fifth conductive layer 119 used as the electrode of the capacitor is grounded as necessary because the conductive layer is not in physical contact with the lower unit cell. You can select from potential to Vcc potential.

Therefore, a silicon nitride film to be used as an insulating film of a capacitor after forming a TFT in a storage node region of an SRAM memory cell employing a bottom gate TFT as a method for increasing storage node capacitance, which is essential for high-integration products of 4M or higher, can be used. By forming a film having a high dielectric constant such as (SiN) and forming a conductive layer applied with a voltage thereon, an electrode composed of a gate conductive layer and a TFT channel offset of a TFT and a conductive layer applied with a voltage are formed. Capacitors consisting of electrodes can be completed to increase the storage node capacitance.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea to which the present invention pertains.

Claims (11)

In a TFT SRAM device forming a CMOS using a PMOS TFT as a load element, an offset of a TFT gate conductive layer 113 and a TFT channel conductive layer 117 in a storage node region of a TFT SRAM cell. The region constitutes one electrode of the capacitor, and the interlayer insulating film 118 is stacked on the upper portion thereof, and the conductive layer 119 constituting the other electrode of the capacitor is stacked on the upper portion thereof without contact with the underlying conductive layer. TFT SRAM device characterized in that it comprises. The TFT SRAM device according to claim 1, wherein a voltage capable of applying a voltage from a ground potential to a Vcc potential is applied to the conductive layer (119). The TFT SRAM device according to claim 1, wherein the conductive layer (119) is located above the TFT gate conductive layer or the TFT channel and the Vcc power line. The TFT SRAM device according to claim 1, wherein the TFT is a bottom gate transistor. The TFT SRAM device according to claim 1, wherein the interlayer insulating film (118) is a material having a high dielectric constant. The TFT SRAM device according to claim 5, wherein the material having high dielectric constant is any one of an oxide and a silicon nitride film (SiN). A TFT SRAM device according to claim 1, wherein the thickness of said interlayer insulating film (118) is less than 200 GPa. The TFT SRAM device according to claim 1, wherein the conductive layer (119) is formed of any one of polysilicon and amorphous polysilicon. 2. The gate and TFT channel offset regions of the TFTs and the P + of the cell storage node of claim 1, except that the portions of the conductive layers 119 forming the capacitors overlap with the TFTs. A TFT SRAM device comprising all of the contact sites where a / N + diode is formed. The TFT SRAM device according to claim 1, wherein the conductive layer (119) runs in the same direction without overlapping with the Vcc power line. Defining an active region and an inactive region on the semiconductor substrate; Forming a pull down transistor and a pass transistor of an SRAM cell as a first conductive layer in the active region; Forming a second conductive layer constituting a ground line (Vss line) and a word line of the SRAM cell; Forming a third conductive layer constituting a gate of the TFT in the bottom gate TFT; Forming a fourth conductive layer forming a channel of the TFT and a Vcc power line on the gate of the TFT; Depositing an insulating film having a high dielectric constant, such as silicon nitride (SiN), to a thickness of 60 占 to an interlayer insulating film of a capacitor through an oxidation process after forming the TFT channel; And forming a fifth conductive layer overlapping the node portion of the cell (including the TFT offset region) to increase the storage node capacitance of the SRAM cell thus formed. That is, a TFT SRAM manufacturing method comprising the step of depositing a pattern of the fifth conductive layer to be used as the other electrode of the capacitor with one of polysilicon and amorphous silicon to a thickness of 1000 Å and then patterning.