JPH0382074A - Semiconductor device - Google Patents

Abstract

PURPOSE:To rapidly switch a PNPN element from ON to OFF by applying a low forward voltage between an anode and a cathode, applying a potential having a reversed phase and a forward voltage or less to intermediate P-type and N-type layers, cutting OFF a current flowing to a P-type gate, and removing storage charge of an N-type gate. CONSTITUTION:In a semiconductor device having PNPN four layers in such a manner that the P-type layer of one end is used as an anode, an N-type layer of the other end is used as a cathode, and the intermediate P-type or N-type layer is used as a gate, a low forward voltage is applied between the anode and the cathode, a potential having a forward voltage or less and a reversed phase is applied to the P-type layer to become an intermediate P-type gate and the N-type layer to become an N-type gate, a current flowing to the P-type gate is cut OFF, and storage charge of the N-type gate can be removed. The anode and the cathode are connected to the high potential side Vcc and low potential side Vcc-Vf of a power source, the N-type gate and the P-type gate are respectively connected to first and second bit lines B1, B2 through first and second transfer gates Q1, Q2, and first and second transfer gates Q3, Q5 are opened and closed by first and second word lines W1, W2.

Description

[Detailed Description of the Invention] [Summary of the Invention] To quickly switch a PNPN element from on to off in a silice type semiconductor device having a PNPN junction, particularly a semiconductor memory device using the same. It has four layers of PNPN, and one end of P
In a semiconductor device in which one layer is an anode, the other end of the N layer is a cathode, and the middle P layer or N layer is a gate, a low forward voltage is applied between the anode and the cathode, and the P layer becomes the middle P gate. The configuration is such that the N layer serving as the N gate is given a potential equal to or less than the line forward voltage and having an opposite phase, thereby blocking the current flowing through the P gate and making it possible to remove the accumulated charge in the N gate.

[Industrial application field]

The present invention relates to a thyristor type semiconductor device having a PNPN junction, and particularly to a semiconductor memory device using the same.

2. Description of the Related Art As the amount of information processing increases in recent years, semiconductor memory devices that are integrated on a larger scale are required.

Semiconductor storage devices include SRAM, DRAM, etc.
Although SRAM operates more stably than OR71M, it uses a larger number of elements, which is an obstacle to higher integration.

An SRAM can be configured by using a PNPN element in a memory cell, and this memory cell has a small number of elements.The present invention relates to an SRAM using a PNPN element.

[Conventional technology]

The present inventor has previously proposed an SRAM using a PNPN element (Japanese Patent Application No. 1-136502), in which the current-voltage characteristic of the gate region exhibits a negative resistance characteristic within the range of the potential difference between the anode and the cathode. SRA takes advantage of the fact that a thyristor can have a stable binary potential state when it is on or off.
This constitutes the M cell. This memory cell consists of one PNPN element and an M for a transfer gate that switches the potential.
O3) One bit is composed of two elements (one transistor), so it is a static RAM with a much higher degree of integration than the conventional one.
can be provided. This will be explained with reference to FIGS. 5 and 6.

FIG. 5(a) shows the configuration of this PNPN element, and (c)
shows this more specifically at the edge P of the PNPNd layer structure.
.

The 0 equivalent circuit in which the N layer becomes the anode A1 and the cathode C and the intermediate P layer or NJi becomes the gate G is as shown in (C), which is the same as Cyrisk. However, the usage is different. In other words, a forward voltage is applied between the anode and cathode, but this voltage is extremely low, about the forward voltage Vt of a PN junction diode, and breakover leading to snapback, which is typical of thyristors, does not occur. , the characteristics are as shown in FIG. 5(d).

That is, the collector voltage V is 0, the anode voltage vA is, for example, 0.6■, and the gate voltage is 0. When is set to 0, a current flows in the V a - V * direction in FIG. 5(C), and if the arrow direction is the positive direction of the gate current I@, a negative gate current flows. Since this current is also the base current of transistor Q, Q is turned on, and the collector current is the transistor Q! base, flows through the emitter.

However, since V is O, there is no collector current of Q2.
This state is the 0th order gate voltage V@ at the 31st point in (d)
When Q begins to increase in the positive direction, the current in the VA-vG direction becomes small and the collector current of transistor Q begins to flow. This is the current in the Vs-(h direction, VA-V,
The direction of current is opposite. Eventually, the gate current I6 becomes 0 at a certain value vl of vr.

This is 32 points of 0).

When the gate voltage -Vf further increases, the collector current of the transistor Q2 increases accordingly, and the gate current 1. increases. However ■. An increase in Qs causes a decrease in the base current of Ql, and a decrease in the collector current of Ql and thus in the base current of Q8. Therefore, the increase in the collector current and hence the gate current of Qs is limited at this point, and eventually reaches a maximum value. This is point S5 in (d). When the gate voltage V@ further increases, the gate current starts to decrease and becomes 0 at a certain gate voltage v3. This is the 34 points in (a).

In this way, this PNPN element has a gate current of 0.
There are two states, point 53 and point S1. In the former, transistors Q and Q are on and their own collector current becomes the base current of the other, and in the latter, transistors Q, , and Q are both off. be. This Q,,Q.

The on/off status is data 1. This PNPN element can be used as an SRAM memory cell.

Figure 6 shows an SR using this PNPN element as a memory cell.
In this figure showing the main parts of AM, WL is a word line, BL is a bit line, Q3 is a transfer gate, and Q4 is a write gate.

Writing is performed as follows: set the word line WL to the selection level, turn on the transfer gate hQs,
Also, the write enable line WE is set to the write mode level, the write gate Q4 is turned on, and the write data 1,
0, the level of the bit line BL is set to H or L. At H, transistor Q1 of memory cell MC. Qg is both off,
Both are on at L. The H and L levels are the voltage V, and the voltage V
,,V.

Therefore, the gate current 1s (current of Qs) is 0 in both cases. Writing is also an inversion of the cell storage state, so when the cell is on, set V,=V to turn the cell off, and when the cell is off, set V,=V to turn the cell on. This vl and ■8 are vcc v in this example
, and VCC. After writing, the word line WL is set to a non-select level and the transfer gate Q is turned off.

Reading is performed as follows. That is, word 1%WL
Transfer gate Q by setting it to the selection level.

1) Turn on and create paths for Vcc, R, Qz, and VG.

If the memory cell MC is on (Q, , Q, are on), a current flows through this path, and if MC is off, the current does not flow. Therefore, the voltage of the resistor R changes according to the stored data, and this is applied to the data output line. Take it out from ut.

[Problem to be solved by the invention]

In this SRAM, when the memory cell is on, the collector-base junction of the PNP transistor Q is deeply forward biased and a large amount of charge is accumulated, so the switching from on to off is performed by the N gate (see Figure 5). This cannot be done quickly by simply increasing the potential of the N layer (which becomes the gate G in a)
(It takes a long time, such as 00μs).

It is an object of the present invention to improve this point and to quickly switch the PNPN element from on to off.

[Means to solve the problem]

As shown in FIG. 1, in the present invention, the P gate, ie, the base of transistor Q2 and the transistor Q.

A transfer gate Q is also provided at the gate indicated by the dotted line in FIG. 5(a), which becomes the collector of PJi, and is connected to the second bit line B through the gate.

Transfer gate Q is turned on and off by second word line W2. Others are the same as in FIG. 6, Wl is the first word line, B is the first bit line, and these are Wl in FIG.
Corresponds to L and BL. Transfer gate Q connects the N gate of memory cell MC to the bit line via write gate Q4 and to resistor R and data output *D, . . . but these are omitted in FIG.

The transfer gates Q, , Qs are N in FIG. 1(a).
An N-channel MO3) transistor is used for the gate, and a P-channel MO3) transistor is used for the P gate.
As shown in Fig. 1(b), both of these are N-channel M
It may be an O3I-transistor, or it may be a P-channel MO3) transistor (not shown).

[Effect]

In this memory cell, writing and reading can be performed as described above, and turning the memory cell from on to off (assuming on is 0 and off is 1, l write) is performed as follows.

That is, word lines Wl, W! Set the selection level to Transfer Gate Q! , Q, are turned on, and the potential vG of the N gate of the bit line B1 is set to the above V! Then, the level of the bit line Bz is lowered to draw out the charge accumulated in the P gate. This makes it possible to change the memory cell MC from on to off at high speed, and the write pulse width can be significantly shortened.

〔Example〕

FIG. 2 shows an embodiment of the memory cell of FIG. 1(a).

When a P layer and Nli separated by trench isolation 130 are formed on a semiconductor substrate, and an N layer and a P layer are sequentially formed on the P layer, PNPN elements Q, , Q are formed together with the N'' layer of the substrate.
I can do t. When PZN source/drain layers are formed on the N layer and PN on both sides, and gate electrodes W1 and W2 are formed, transfer gates QS and Q are formed.

The power supply VCC line is contacted to the P'' layer of the PNPN element, the N layer is connected by the N'' area polycrystalline silicon layer (conductor layer) 1+ of Q, and the P layer is connected to Q.

is connected to the P”SI region of Q by a polycrystalline silicon layer Lt.
The remaining N"f+1 area of 3 is moved to metal JIBl and Q.

The remaining P''?il region is connected to the metal layer B2. Fig. 2(a) is a cross-sectional view, and Fig. 2(b) is a plan view.The memory cell and the transfer gate are separated by isolation. This is to prevent the generation of parasitic thyristors.

FIG. 3 shows another embodiment of the invention. In this example, a wide isolation region is provided, a silicon layer is grown on this region, and transfer gates Q, , Q are formed.

A source/drain region, etc., are formed in the silicon layer.

In other words, the transfer gate is either 301 (a silicon single crystal layer is formed on an insulator and an FET is made from this) or TPT (a silicon polycrystalline layer or a silicon amorphous layer is formed on an insulator and an FET is made from this). thing)
Formed by Such a configuration can also prevent the generation of parasitic thyristors. Also, transfer game) Q, Qs
may be a so-called SIMOX type Sol element in which a buried oxide film layer is selectively formed directly under the channel.

Figure 4 shows transfer gate Q=, N channel M in Qs.
O3) An example using a transistor is shown. Furthermore, the surfaces of the polycrystalline silicon layers V cc , L + , and L z are made of silicide. That is, the conductive layer L1 may be made of polycrystalline silicon doped with N-type impurities, but the conductive layer L! The part that contacts the N″ region is doped with N-type impurities, and the part that contacts the P9 region is polycrystalline silicon doped with P-type impurities, creating a PN junction between them. A silicide layer, which is a compound of a high-melting point metal and silicon, short-circuits this.Also, since silicide has low resistance, it is also useful for lowering the resistance of the polycrystalline silicon layer.

As transfer gates Q,,Q,, MOS FIS
JFI instead of TO! A unipolar element such as T may also be used.

If reading is performed in the same manner as in FIG. 6, only one of the bit lines will be used and the other will be idle, but it is also possible to use both and drive the differential amplifier with them.

〔Effect of the invention〕

As described above, according to the present invention, writing to an SRAM using a PNPN element can be performed at high speed, and a large-capacity and high-speed 5RIV can be realized.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention. Fig. 2 (a) and (b) are a sectional view and a plan view showing Embodiment 1 of the invention. Fig. 3 is a sectional view showing Embodiment 2 of the invention. , Figure 4(a)
and (b) are a cross-sectional view and a plan view showing Embodiment 3 of the present invention, FIGS. 5(a) to (d) are explanatory diagrams of a PNPN element, and FIG. 6 is a main circuit of an SRAM using a PNPN element. It is a diagram. In FIG. 1, Q, , Q are PNPN elements, Q, , Q are transfer gates, W+, W* are word lines, and B+, Bx are bit lines.

Claims (1)

[Claims] 1. Has 4 PNPN layers, with the P layer at one end serving as an anode;
In a semiconductor device in which the N layer at the other end is the cathode and the middle P layer or N layer is the gate, a low forward voltage is applied between the anode and the cathode, and the P layer becomes the middle P gate and the N gate. A semiconductor device characterized in that a potential having a phase opposite to that of the forward voltage is applied to the N layer to block a current flowing through the P gate, thereby making it possible to remove accumulated charges in the N gate. 2. Connect the anode and cathode to the high potential side of the power supply (V_c_c
and the low potential side (V_c_c-V_f), and connect the N gate and P gate to the first and second transfer gates (Q
_3, Q_5) through the first and second bit lines (B_1
, B_2), and the first and second transfer gates are opened and closed by the first and second word lines.