JP2003068982A - Static random access memory with non-volatile data holding function and its operating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a static random access memory with a non-volatile data holding function and its operating method, where a static random access memory is made to have the non-volatile data holding function so as to be further reduced in power consumption and manufacturing cost. SOLUTION: A one conductivity-type drain region 4, a reverse conductivity- type channel region 2, and a reverse conductivity-type source region 3 are provided on a one conductivity-type semiconductor board 1, a floating gate 6 and a gate electrode 8 are provided so as to cover a pn junction composed of the one conductivity-type drain region and the reverse conductivity-type, and a load resistor 9 is provided so as to be electrically connected to the one end of the one conductivity-type drain region 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static random access memory (S
RAM), and in particular, a static random memory with a non-volatile data retention function, which is characterized by an element structure and an operating method for operating a high-speed, large-scale integration, and low-cost memory element to be non-volatile. -It relates to the access memory.

[0002]

2. Description of the Related Art With the spread of high-speed data communication in recent years,
Electronic devices and systems for performing data communication at high speed and low power consumption are required to have lower cost, higher speed, and lower power consumption.

An SRAM (Static Random Access Memory) is one of the electronic devices used for such data communication, but the conventional SRAM device is a high speed device with a power supply voltage applied as a single device. It has a feature that it can operate with low power consumption.

Particularly, among them, one transistor is SR
A pn-junction 1-transistor SRAM that can form an AM and can reduce the chip area has been proposed as a low-cost and highly-integratable SRAM. Here, a conventional pn-junction 1-transistor SRAM will be described with reference to FIG. .

See FIG. 7A. FIG. 7A shows a conventional pn junction single transistor SRAM.
3 is a schematic cross-sectional view of one memory cell of FIG. 1, in which an n ⁺ type channel region 43 and an n ⁺ type source region 44 are formed in an element formation region surrounded by an element isolation oxide film 42 provided on a p type silicon substrate 41.
And a p ⁺ -type drain region 47 is provided so as to be in contact with the n ⁺ -type channel region 43, and a pn formed by the n ⁺ -type channel region 43 and the p ⁺ -type drain region 47 is provided.
A gate electrode 46 is provided so as to cover the junction 48 with a gate oxide film 45 interposed.

Further, after the W load resistance layer 50 is provided via the first interlayer insulating film 49, the second interlayer insulating film 51 is provided, and W is provided via the contact hole provided in the second interlayer insulating film 51. A power supply electrode 52 connected to one end of the load resistance layer 50, a drain electrode 53 connected to the other end of the W load resistance layer 50 and in contact with the p ⁺ -type drain region 47, and a source electrode 54 in contact with the n ⁺ -type source region 44. Is provided.

FIG. 7B is an equivalent circuit of one memory cell of the conventional pn junction one transistor SRAM shown in FIG. 7A.
A power supply potential V _dd is applied to the power supply electrode 52, and
A source potential V _s (ground potential in the figure) is applied to the source electrode, and the drain potential V _d output to the drain electrode 53 is controlled by the gate potential V _g applied to the gate electrode 46.

See FIG. 7C. FIG. 7C shows the I _{d of the} pn junction 1-transistor SRAM.
FIG. 7 is a −V _d characteristic diagram, in which the thickness of the depletion layer of the pn junction 48 is controlled by applying a gate potential V _g , and thereby an N-type negative differential resistance characteristic is obtained.

In this case, the intersection of the pn junction 48 negative differential resistance shown by the solid line and the load resistance of the W load resistance layer 50 shown by the broken line gives two stable states, and the gate potential V _g causes the negative differential resistance current to flow. It is possible to control the voltage in two states, that is, the high state H (V _H ) and the low state L (V _L ) by controlling the voltage.

By holding one of these two stable voltage states unless a signal is input,
The SRAM (Static Random Access Memory) characteristics can be obtained by only one pn junction with a gate electrode.

[0011]

[Problems to be Solved by the Invention] However, such a pn
Since the junction 1-transistor SRAM does not have a function of holding data in a non-volatile manner, for example, in a system such as a personal computer, it must coexist with a non-volatile memory to read data from or store data in the non-volatile memory. There is.

Therefore, when viewed as a system as a whole, there is a problem that power consumption due to wiring between memories and loss in the manufacturing process are large, and it is difficult to reduce power consumption and cost.

Therefore, the present invention further reduces the power consumption by providing a nonvolatile data holding function,
The purpose is to achieve low prices.

[0014]

FIG. 1 is an explanatory view of the principle configuration of the present invention, and means for solving the problems in the present invention will be described with reference to FIG. Note that FIG.
FIG. 1A is a conceptual configuration diagram of one memory cell.
(B) is an I _d -V _d characteristic diagram, and the reference numeral 7,
Reference numerals 10 are a second gate insulating film and an element isolation insulating film, respectively. 1A and 1B, in order to achieve the above-mentioned object, the present invention is a static random access memory with a non-volatile data retention function. The reverse conductivity type channel region 2 and the reverse conductivity type source region 3 are provided, and the floating and gate electrodes 8 are formed so as to cover the pn junction formed by the one conductivity type drain region 4 and the reverse conductivity type channel region 2. Provided and
A load resistor 9 is provided so as to be in electrical contact with the one conductivity type drain region 4 at one end. The one-conductivity-type semiconductor substrate in the present invention includes not only one-conductivity-type semiconductor substrate but also one-conductivity-type well regions provided in the opposite-conductivity-type semiconductor substrate.

That is, according to the present invention, by adding the floating gate 6 to the pn junction 1-transistor SRAM,
It is intended to increase the functionality of the element by adding a function of retaining information to the SRAM without increasing the area of the element, thereby reducing the number of elements as a whole system for storing data, and Reduced power consumption due to wiring between cells and loss of manufacturing process, low power consumption,
The price can be reduced.

In this case, the power source voltage V is applied to the other end of the load resistor 9.
_{When dd} is applied to the floating gate 6, the drain electrode potential V _d takes two states of a high state H and a low state L due to the negative differential resistance in the state where there is no carrier of the opposite conductivity type, and the drain electrode potential V _d is opposite to the floating gate 6. The film thickness of the floating gate 6 is such that the pn junction does not exhibit negative differential resistance in the presence of the conductivity type carrier and the drain electrode potential V _d takes a stable high state H ′ different from the high state H. ,
Also, it is necessary to adjust the film thickness of the first gate insulating film 5 interposed between the floating gate 6 and the one conductivity type semiconductor substrate 1.

When such a pn junction transistor SRAM is operated, the intersection of the negative differential resistance and the load resistance 9 corresponds to two stable operating points in the state where the floating gate 6 has no carriers of the opposite conductivity type. Then, the high state H therein is moved to the stable operating point H ′ in the state where the floating gate 6 has the opposite conductivity type carrier after the power is turned off, and the low state L is reversely conducted to the floating gate 6 after the power is turned off. Move to a stable operating point without mold carrier.

When the information is held in a non-volatile state, before the power supply voltage V _dd is cut off, the external sense amplifier circuit senses whether it is in the high state H or the low state L, and the low state is detected. In L, the power is turned off as it is, and in the high state H, a bias having a polarity for injecting carriers of the opposite conductivity type into the floating gate 6 is applied between the gate electrode 8 and the source region 3 of the opposite conductivity type to reverse the floating gate 6. After injecting the conductive type carrier and moving it to the stable operating point H ′, the power source may be turned off.

To restore the information from the non-volatile state, the power supply voltage V _dd is applied, the drain voltage V _d is once set to 0 V by an external circuit, and then the stable voltage is moved to the stable point. Latch the drain voltage V _d ,
When a bias having a polarity that discharges carriers of the opposite conductivity type is applied between the gate electrode 8 and the source region 3 of the opposite conductivity type, and when the carriers of the opposite conductivity type are accumulated in the floating gate 6, the carriers of the opposite conductivity type are After discharging, the latched drain voltage V _d may be applied and moved to a stable point.

In this case, when the latched drain voltage V _d is in the low state L, that is, when the floating gate 6 has no carriers of the opposite conductivity type before the application of the power source voltage, the drain voltage V _d is in the low state L and the power source voltage is low. Before the application, if there are carriers of the opposite conductivity type in the floating gate 6, the drain voltage V _d becomes the high state H, and the power supply voltage is once turned off between the high state H and the low state L of the SRAM. When re-applied, it can return to each state, and SRAM
A function capable of holding information in a nonvolatile manner in the chip can be added.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION An SRAM with a nonvolatile data holding function according to a first embodiment of the present invention will now be described with reference to FIGS. 2 to 5. First, refer to FIGS. The manufacturing process will be described. See FIG. 2A. First, for example, after selectively forming an element isolation oxide film 12 on a p-type silicon substrate 11 doped with 1 × 10 ¹⁶ cm ^{−3 of} B (boron), a resist pattern 13 is provided, Using the resist pattern 13 as a mask, the concentration of As ions 14 in the activation region surrounded by the element isolation oxide film 12 excluding the drain region is, for example, 1 × 10 ¹⁹ cm ^−3.
So that the n ⁺ -type channel region 16 and the n ⁺ -type channel region 16
An n ⁺ type region 15 to be the type source region 17 is formed.

Next, after removing the resist pattern 13, the exposed surface is dry-oxidized on the exposed surface to a thickness of, for example, 4 nm.
A gate oxide film 18 is formed, and then a non-doped polycrystalline silicon layer 19 having a thickness of, for example, 10 nm to be a floating gate is deposited.

Then, again by dry oxidation, the thickness of the non-doped polycrystalline silicon layer 19 is reduced to, for example,
After forming the second gate oxide film 20 having a thickness of 4 nm, a non-doped polycrystalline silicon layer 21 having a thickness of, for example, 300 nm is deposited.

Next, as shown in FIG. 3C, a resist pattern 22 having a width of, for example, 300 nm is provided, and etching is performed using this resist pattern 22 as a mask to form the gate electrode 24 / second electrode.
A gate structure composed of gate oxide film 20 / floating 23 / first gate oxide film 18 is formed.

Next, as shown in FIG. 3D, after removing the resist pattern 22, a new resist pattern 25 covering the n ⁺ type source region 17 is formed. Using this resist pattern 25 as a mask, the concentration of B ions 26 is reduced. For example, the p ⁺ -type drain region 27 is formed by implanting so as to have a ^{dose of} 1 × 10 ¹⁹ cm ⁻³ , the pn junction 28 is formed between the n ⁺ -type channel region and the gate electrode 24, and Convert to type. The floating gate 23 remains undoped.

Next, as shown in FIG. 4E, after removing the resist pattern 25, thermal CV is performed.
A first interlayer insulating film 29 made of a SiO ₂ film is formed by using the D method, and then a W film is deposited on the entire surface and then patterned so as to obtain a predetermined resistance value. To form.

Next, referring to FIG. 4F, a second interlayer insulating film 31 made of a BPSG film is formed on the entire surface.
After forming the contact hole, a contact hole is formed at a predetermined position, and then, an A film having a thickness of, for example, 300 nm
By depositing an I film, a power supply electrode 32 connected to one end of the W load resistance layer 30, a drain electrode 33 connected to the other end of the W load resistance layer 30 and the p ⁺ -type drain region 27,
And the source electrode 34 connected to the n ⁺ type source region 17
By forming the S,
The basic structure of the RAM is completed.

The SR with the non-volatile data holding function
The thicknesses of the first gate oxide film 18 and the floating gate 23 in AM are such that the pn junction 28 does not exhibit negative differential resistance when electrons are present in the floating gate 23.
It is necessary to adjust the drain potential V _d so that it takes a stable point H ′ state shown in FIG.

Next, with reference to FIG. 5, the operation of the SRAM with a non-volatile data holding function will be described. Refer to FIG. 5A. FIG. 5A is an equivalent circuit diagram of the SRAM with the non-volatile data holding function according to the first embodiment of the present invention. In a normal operation state, no electrons are stored in the floating gate 23. Not injected, the source electrode 34 is set to the ground potential V _s , the power supply voltage V _dd is applied to the power supply electrode 32, and the pn junction 28 is depleted by the positive gate potential V _g applied to the gate electrode 24. The layer thickness is controlled so that an N-shaped negative differential resistance appears. When the gate potential V _g is 0 or negative, the N-type negative differential resistance does not appear at the pn junction 28, and the diode characteristic becomes blunt.

In this case, the negative differential resistance due to the pn junction 28 shown by the solid line and the load resistance due to the W load resistance layer 30 shown by the broken line are shown, just like the conventional pn junction 1-transistor SRAM. The two intersections of two correspond to two stable operating points L and H, and the SRAM operation becomes possible by making these operating points L and H correspond to "0" and "1", respectively.

Next, a method of holding information in a nonvolatile manner will be described. First, before the power supply voltage V _dd is cut off, the drain potential V _d of each memory cell is set to H level by the external sense amplifier circuit.
It senses whether the memory cell is in the high (H) or low (L) state, and the memory cell in the low state is powered off as it is.

5B and 5C, on the other hand, in the memory cell in which the drain potential V _d is High, a positive bias is applied between the gate electrode 24 and the source electrode 34 to make the floating gate 23 After injecting electrons into the semiconductor device and moving it to a stable point H ′ which is an intersection of the dull diode characteristic shown by the thin solid line in FIG. 5C and the load resistance by the W load resistance layer 30 shown by the broken line, the power is turned off. .

Next, a method for restoring the held data when the power is turned off and then turned on again will be described. First,
When the power supply voltage V _dd is applied again, the drain potential V _d is once set to 0 V by an external circuit, then moved to a stable point, and the potential V _d (L or H ′) is latched, and the gate electrode 2
A negative bias is applied between 4 and the source electrode 34.

At the time of turning off the power supply, the drain potential V _d
Floating gate 2 in a memory cell of L
Since no electrons have been injected into 3, the differential negative resistance appears and the drain potential V _d returns to L again.

On the other hand, when the power is turned off, in the memory cell having the drain potential V _d of H, since electrons are accumulated in the floating gate 23, the electrons are emitted due to the applied negative bias, and the electrons are emitted. Then, the latched potential H'is applied to move to the stable point H caused by the negative differential resistance.

As described above, in the first embodiment of the present invention, the two states of SRAM, High and Low, are simply turned off by providing the floating gate, and when the power supply voltage is once turned off and then applied again, the respective states are turned on. It is possible to add the function of holding information in a nonvolatile manner in the SRAM chip.

Therefore, the memory cell area is pn
SR because it is exactly the same as junction 1-transistor SRAM
Since the degree of integration of the AM itself does not decrease and it is not necessary to use a non-volatile memory in addition to the SRAM in the entire system such as a personal computer, power consumption due to wiring between the memories and loss of a manufacturing process are reduced. Therefore, low power consumption and low price can be achieved.

It takes about 10 ⁻⁶ seconds to inject or extract electrons from the floating gate 23 when the power supply is off and on, but the SRAM operation can be performed at the same high speed as other SRAMs.

Next, with reference to FIG. 6, a manufacturing process of the SRAM with a nonvolatile data holding function of the second embodiment of the present invention will be described. First, the gate structure and the drain are formed after the gate structure is formed by the steps of FIGS. 2A to 3C exactly as in the first embodiment of the present invention. A new resist pattern 35 is provided so as to cover the formation region, and then,
As ions 3 using this resist pattern 35 as a mask
6 is relatively high energy, for example, 1 × 10 ¹⁹ cm
^By implanting so as to have a concentration of ^−3, an n ⁺ type source region 37 deeper than the n ⁺ type channel region 16 is formed.

After that, again, FIGS. 3D to 4F are performed.
Through the steps of, the basic structure of the SRAM with a non-volatile data holding function, which has almost the same configuration as the first embodiment except the shape of the n ⁺ type source region 37, is completed.

In the second embodiment, since the n ⁺ type source region 37 is deeply formed, the source electrode 3
When forming No. 4, a short circuit or the like due to Al penetration does not occur. In this case, the drain region does not need to be deeply formed because it has the same conductivity type as the p-type silicon substrate.

Although the respective embodiments of the present invention have been described above, the present invention is not limited to the numerical values, conditions, etc. described in the respective embodiments, and various modifications can be made. For example, in each of the above-described embodiments, the floating gate is provided to hold the information when the power is turned off in a non-volatile manner.
A SiN film is used instead of the doped polycrystalline silicon layer, and S
Electrons may be trapped by utilizing the interface state at the interface of iO ₂ / SiN.

Further, in each of the above embodiments, the W load resistance layer is used as the load resistance, but it may be a load resistance using other metal or polycrystalline silicon, and further, the surface of the semiconductor substrate. It is also possible to use the diffusion resistance formed in the above as the load resistance.

Further, in each of the above-mentioned embodiments, the carrier traveling in the channel region is an electron, but it is not limited to an electron and may be a hole. In that case, each region may be a hole. It is sufficient to invert all the conductivity types and the polarity of the applied bias.

[0045]

According to the present invention, since the pn junction single transistor SRAM is provided with the floating gate,
A nonvolatile data holding function can be added without increasing the area, which greatly contributes to simplification of the entire system such as a personal computer, low power consumption, and low cost.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a principle configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process up to the middle of the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a manufacturing process up to the middle of FIG. 2 and subsequent steps of the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of the manufacturing process after FIG. 3 of the first embodiment of the present invention.

FIG. 5 is an explanatory diagram of an operation of the SRAM according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram of a manufacturing process according to the second embodiment of the present invention.

FIG. 7 is an explanatory diagram of a conventional pn junction single transistor SRAM.

[Explanation of symbols]

1 1-conductivity type semiconductor substrate 2 reverse-conductivity type channel region 3 reverse-conductivity type source region 4 1-conductivity type drain region 5 first gate insulating film 6 floating gate 7 second gate insulating film 8 gate electrode 9 load resistor 10 element isolation insulating film 11 p-type silicon substrate 12 element isolation oxide film 13 resist pattern 14 As ions 15 n ⁺ type region 16 n ⁺ type channel region 17 n ⁺ type source region 18 first gate oxide film 19 non-doped polycrystalline silicon layer 20 second Gate oxide film 21 Non-doped polycrystalline silicon layer 22 Resist pattern 23 Floating gate 24 Gate electrode 25 Resist pattern 26 B ion 27 p ⁺ type drain region 28 pn junction 29 First interlayer insulating film 30 W load resistance layer 31 Second interlayer Insulating film 32 Power electrode 33 Drain electrode 34 Source electrode 35 Resist pattern Turn 36 As ion 37 n ⁺ type source region 41 p type silicon substrate 42 element isolation oxide film 43 n ⁺ type channel region 44 n ⁺ type source region 45 gate oxide film 46 gate electrode 47 p ⁺ type drain region 48 pn junction 49 1 interlayer insulating film 50 W load resistance layer 51 second interlayer insulating film 52 power electrode 53 drain electrode 54 source electrode

Claims (5)

[Claims] 1. A one-conductivity type drain region, a reverse-conductivity type channel region, and a reverse-conductivity type source region are provided on a one-conductivity type semiconductor substrate, and the one-conductivity type drain region and the reverse-conductivity type channel region are formed. A static random random circuit with a non-volatile data retention function, characterized in that a floating gate and a gate electrode are provided so as to cover the pn junction, and a load resistor is provided so as to be in electrical contact with one conductivity type drain region at one end. Access memory. 2. A power supply voltage is applied to the other end of the load resistor, and the drain electrode potential is in a high state H and a low state L due to a negative differential resistance in a state where carriers of opposite conductivity type do not exist in the floating gate. The pn junction does not exhibit a negative differential resistance in a state where carriers of opposite conductivity type are present in the floating gate, and the drain electrode potential takes a stable high state H ′ different from the high state H. 2. The nonvolatile data according to claim 1, wherein the film thickness of the floating gate and the film thickness of the first gate insulating film interposed between the floating gate and the one conductivity type semiconductor substrate are adjusted. Static random access memory with retention function. 3. The method of operating a static random access memory with a non-volatile data holding function according to claim 1, wherein the negative differential resistance and the negative differential resistance are set in a state where the floating gate has no carriers of opposite conductivity type. The intersection with the load resistance corresponds to two stable operating points, and the high state H therein is moved to the stable operating point H ′ in the state where the floating gate has carriers of the opposite conductivity type after the power is turned off. A method of operating a static random access memory with a non-volatile data retention function, which comprises moving the low state L to a stable operating point in the state where there is no carrier of opposite conductivity type in the floating gate after the power is turned off. 4. Before cutting off the power supply voltage, an external sense amplifier circuit senses whether it is in a high state H or a low state L. In the low state L, the power is turned off as it is, and in the high state H. A bias having a polarity for injecting carriers of the opposite conductivity type into the floating gate is applied between the gate electrode and the source region of the opposite conductivity type to inject the carriers of the opposite conductivity type into the floating gate, and the carrier moves to the stable operating point H ′. 4. The method of operating a static random access memory with a non-volatile data holding function according to claim 3, wherein the power is turned off and the information is held non-volatile after the operation. 5. A power supply voltage is applied to a static random access memory with a non-volatile data holding function in a state where information is held, the drain voltage V _d is once set to 0 V by an external circuit, and then moved to a stable point, In the case where the drain voltage V _d at the stable point is latched, a bias having a polarity that discharges the opposite conductivity type carriers is applied between the gate electrode and the opposite conductivity type source region, and the opposite conductivity type carriers are accumulated in the floating gate. 4. The static data with a non-volatile data retention function according to claim 3, wherein after the reverse conductivity type carrier is released, the latched drain voltage _Vd is applied to move to a stable point to restore the memory information. -How to operate the random access memory.