JP2738604B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-density, large-capacity semiconductor memory device having a MOS (metal-oxide-semiconductor structure) transistor.

[0002]

2. Description of the Related Art FIG. 12 shows a memory cell portion of a conventional semiconductor memory device having a MOS transistor. In this semiconductor memory device, L
The rectangular active region 72 is formed by the OCOS isolation method (selective oxidation method) or the trench isolation method. Gate electrodes 73 and 74 are made of polysilicon and have an active region.
Crosses 72. Portions of the active region 72 covered by the gate electrodes 73 and 74 function as channel regions 82 and 81, respectively. Active region 72 sandwiched between gate electrodes 73 and 74
A drain region 76 is formed in the portion. Source regions 75 and 77 are formed in other portions of active region 72, and are arranged adjacent to gate electrodes 73 and 74, respectively.

A MOS transistor is constituted by a gate electrode 73, a channel region 82, a source region 75, and a drain region 76, and includes a gate electrode 74, a channel region 81, a source region 77, and a drain region 76. Another MOS transistor is configured. These two MOS transistors have a drain region
Share 76.

[0004] The drain region 76 is connected to a bit line (not shown) via a bit contact 79. Source regions 75 and 77 are connected to one electrode of a charge storage capacitor (not shown) via storage contacts 78 and 80, respectively.

The above two MOS transistors, bit contact 79, and storage contacts 78 and 80
And a capacitor for charge storage constitute one memory cell of the semiconductor memory device. The gate electrodes 73 and 74 function as word lines, and an address signal is supplied to the memory cells through the word lines.

A memory cell as described above is, for example, an n-type M
When an OS transistor is provided, when a high potential bias is applied to the gate electrode 73 or 74, one of the two MOS transistors is turned on. At this time, if the memory cell is in the read state, the signal charge stored in the capacitor is stored in the storage contact 78 or 80.
Then, the signal is transferred to the drain region 76 via the source region 75 or 77 and the channel region 82 or 81 of the MOS transistor in the ON state. This signal charge is then sent to a sense amplifier (not shown) via a bit contact 79 and a bit line. Conversely, if the memory cell is in a write state, signal charges are transferred from the drain region 76 to the capacitor in a direction opposite to that in the above-described read state. The transferred signal charges are stored in the capacitor.

When a MOS transistor of a memory cell as described above is formed, a source region and a drain region are formed by implanting impurity ions into an active region in order to obtain ohmic contact with an electrode material. .
The impurity ions are usually implanted into, for example, a region (impurity implantation region 71 shown in FIG. 12) covering the entire surface of the MOS transistor. Since the gate electrodes 73 and 74 function as a mask when implanting impurity ions, the source and drain regions can be formed in a self-aligned manner by implanting impurity ions. In this case, part of the drain side active region becomes the drain region 76, and part of the source side active region becomes the source regions 75 and 77.

A conventional DRA known as a semiconductor memory device
Most of M (Dynamic Random Access Memory) adopts a folded bit line system in consideration of noise resistance. Therefore, when the active region is rectangular as shown in FIG. 12, each memory cell is arranged as shown in FIG. As shown in this figure, the active regions adjacent to the active region 91 are the active regions 89, 90, 92, and 93. The active region is arranged so as to form a row parallel to the gate electrode 96 functioning as a word line. The active regions in one column are offset from the active regions in adjacent columns by half the pitch of the active regions in each column. For example, as shown in FIG.
And 91 are respectively 1/2 pitch from active regions 89 and 92 and active regions 90 and 93, that is, active region 8
It is offset by half the distance between 8 and 91.

[0009]

By the way, the element isolation region for electrically insulating between the active regions has a capacity of 4 megabits (4 megabits).
M) In the case of manufacturing a DRAM or a semiconductor memory device having a relatively low degree of integration, it is formed by selectively oxidizing a silicon substrate using a LOCOS isolation method. On the other hand, a highly integrated 16M DR with a fine structure
When manufacturing an AM or 64M DRAM, it is necessary to form fine element isolation regions having widths of 0.6 to 0.7 μm and 0.4 to 0.5 μm, respectively. However, a fine element isolation region having a width of 0.4 to 0.7 μm cannot be formed by using the LOCOS isolation method. Therefore, when manufacturing a highly integrated semiconductor memory device requiring a fine element isolation region, the element isolation region must be formed by using a trench isolation method. In the trench isolation method, for example, an element isolation region is formed by forming a groove in a silicon substrate and filling the groove with an insulating material.

However, the above-mentioned conventional semiconductor memory device has the following problems.

1) As shown in FIG. 12, since the region 71 into which impurity ions are implanted covers the entire surface of the MOS transistor, the impurity ions implanted into the impurity implantation region 71 reduce the fine structure of the memory cell. During the heat treatment step for forming, from the source regions 77 and 75 and the drain region 76, from all the boundaries between the channel region 81 and the source region 77 and the drain region 76, and from the channel region
Heat is diffused from all boundaries between the source region 75 and the drain region 76 to the channel regions 81 and 82. Therefore, in particular, in a MOS transistor, which is the smallest transistor used in a memory cell of a DRAM, the influence of the short channel effect such as a decrease in threshold voltage and a decrease in punch-through breakdown voltage cannot be ignored, and a leak current increases. As a result, it becomes difficult to hold the signal charge of the capacitor required for the storage operation of the memory cell, and the memory cell does not operate normally.

2) As shown in FIG. 12, since the impurity ion implanted region 71 covers the entire surface of the MOS transistor, the total area of the source regions 75 and 77 and the drain region 76 is relatively large. For this reason, the junction capacitance generated between the silicon substrate 70 and the source regions 77 and 75 and the drain region 76 increases, and in particular, the parasitic capacitance of the bit line increases, causing an increase in current consumption and a decrease in operation speed.

3) As shown in FIG. 13, in a folded bit line type semiconductor memory device, an active region 91, an active region 89,
The distance between 90, 92 and 93 is the active area 91 and the active area
It is less than 1/2 of the distance to 88. Therefore, the width of the element isolation region to be formed between the active regions becomes non-uniform.
However, it is extremely difficult to form an element isolation region having a non-uniform width using the trench isolation method. Therefore, highly integrated 16M DRAM and 64M DRAM
When manufacturing a semiconductor device, there are two isolation methods, namely, a LOCOS isolation method that can form an element isolation region having an uneven width, and a trench isolation method that can form a fine element isolation region having a width of 0.4 to 0.7 μm. Therefore, the process for forming the element isolation region becomes complicated.

The present invention solves the above-mentioned conventional problems, and aims at reducing the short channel effect and reducing the junction capacitance between the semiconductor substrate and the source and drain regions. , The malfunction of the memory cell is reduced, the reliability of the storage operation is improved, and the MOS
An object of the present invention is to provide a semiconductor memory device capable of preventing an increase in current consumption and a decrease in driving capability of a type transistor. Another object of the present invention is to provide a semiconductor memory device having a structure in which an active region can be easily separated by a single element isolation technique.

[0015]

A semiconductor memory device according to the present invention includes a plurality of memory cells, each of which has an active region having a MOS transistor formed in a surface region of a semiconductor substrate, possess the gate electrode of the type transistor, and a first impurity implantation region and a second impurity doped region defining a source region and a drain region of the MOS transistor, the area of each impurity-implanted region
Are the source-side active region and the drain-side active region, respectively.
By making it smaller , the above-mentioned object is achieved.

In the semiconductor memory device according to the present invention, the gate electrode is formed on the semiconductor substrate so as to divide the active region into a source-side active region having a storage contact and a drain-side active region having a bit contact. Have been. The portion of the active region located below the gate electrode functions as a channel region of the MOS transistor. The first impurity-implanted region is formed in a part of the source-side active region so as to overlap at least a part of the storage contact and the gate electrode. The portion of the source-side active region overlapping with the first impurity-implanted region functions as the source region of the MOS transistor. Further, the second impurity-implanted region is formed in a part of the drain-side active region so as to overlap at least a part of the bit contact and the gate electrode. The portion of the drain-side active region overlapping with the second impurity-implanted region functions as a drain region of the MOS transistor.

The active region of each memory cell is preferably arranged in a row parallel to the gate electrode. In this case, the active areas of two adjacent columns are arranged such that all distances between adjacent active areas are substantially equal.
Examples of the planar shape of the active region include a T shape, a Y shape, a V shape, and an oblique shape.

[0018]

The semiconductor memory device of the present invention includes a plurality of T-shaped or Y-shaped active regions having MOS transistors formed in the surface region of the semiconductor substrate.
The T-shaped or Y-shaped active regions are arranged in a plurality of rows that are alternately shifted in phase so that the intervals between the active regions are substantially equal. Therefore, in this case, it is not necessary to use the LOCOS isolation method capable of forming an element isolation region having an uneven width when forming the element isolation region, but only the trench isolation method capable of forming a fine element isolation region. May be used. Therefore, when manufacturing the semiconductor memory device of the present invention, the element isolation region that electrically insulates each active region can be easily formed by a simple process.

Further, in the semiconductor memory device of the present invention, the impurity-implanted region for forming the source region is formed so as to overlap with the source-side active region and a part of the contact region provided therein. Similarly, an impurity-implanted region for forming a drain region is formed so as to overlap a drain-side active region and a part of a contact region provided therein. By implanting impurity ions into these impurity-implanted regions, the overlapping portion between the source-side active region and the impurity-implanted region becomes a source region, and the overlapping portion between the drain-side active region and the impurity-implanted region becomes a drain region. Therefore, in the heat treatment performed after the impurity ion implantation, the impurity ions are transferred from the source region and the drain region to the channel region only through part of the boundary between the channel region and the source-side active region and the drain-side active region. Will spread. For this reason, the effective channel length of the channel region is not significantly shortened, and the short channel effect can be significantly reduced.

As described above, in the semiconductor memory device of the present invention, since the impurity-implanted region overlaps only a part of the source-side active region and the drain-side active region, the area of the obtained source region and drain region is obtained. Is smaller than that of a conventional semiconductor memory device in which an impurity implantation region overlaps the entire memory cell. Therefore, the junction capacitance between the semiconductor substrate and the source region and the drain region can be reduced, so that the parasitic capacitance of the semiconductor memory device can be reduced, so that the driving capability of the MOS transistor is not impaired. Can be.

According to the present invention, the active region may have another shape such as a V-shape or an oblique shape. Even in such a case, the impurity-implanted region may include at least one of the source-side active region and a part of the contact region provided therein, and the drain-side active region and the contact region provided therein. It is arranged so as to overlap only the part. For this reason, the above effects such as a reduction in the short channel effect and a reduction in the junction capacitance can be obtained.

[0022]

Embodiments of the present invention will be described below.

(Embodiment 1) FIG. 1 is a partial plan view of an embodiment of a semiconductor memory device according to the present invention. In the semiconductor memory device of the present embodiment, a plurality of T-shaped active regions 2, 3, 4, 5, 6, 7, and 8 are formed in the surface region of the semiconductor substrate 1, and on the semiconductor substrate 1, A plurality of gate electrodes 9, 9,... Are formed. Active areas 2, 3, 4, 5,
The arrangement of 6, 7 and 8 is based on a folded bit line scheme. The portions of the T-shaped active regions 2, 3, 4, 5, 6, 7, and 8 that protrude downward in the drawing are sandwiched between the two gate electrodes 9, 9.

Active regions 2, 3, 4, 5, 6, 7 and 8
Are arranged in rows parallel to the gate electrodes 9, 9,.... The row composed of the active regions 2, 5 and 8 and the row composed of the active regions 3 and 6 and the column composed of the active regions 4 and 7 are arranged so as to be alternately out of phase. It is made uniform. Therefore, even when the semiconductor memory device is highly integrated and the interval between each active region is narrowed, a complicated process of using both the LOCOS isolation method, the trench and the isolation method is unnecessary for forming the element isolation region. Therefore, the active regions can be easily isolated by using only the trench isolation method which is particularly effective when the interval between the active regions is small.

FIG. 2 shows the active region 2 of the semiconductor memory device of FIG.
FIG. The active region 2 and two gate electrodes 9 and 9 intersecting the active region 2 form two MOSs.
Type transistor. The portion of the active region 2 covered with the gate electrodes 9 and 9 is a channel region. Reference numerals 14 and 16 indicate a source side active region, and 15 indicates a drain side active region. The storage contacts 17 and 19, which are contact regions, are provided on the source-side active regions 14 and 16, respectively. Similarly, the bit contact 18, which is a contact region, is provided on the drain-side active region 15.

The impurity-implanted regions 20 and 22 for the source-side active regions 14 and 16 are
And a part of the storage contact 17
And covers part of 19. The impurity implantation region 11 for the drain side active region 15 covers a part of the drain side active region 15 and a part of the bit contact 18. By implanting impurity ions into these impurity implanted regions 20, 22, and 11, a source region and a drain region are formed. In that case, the source side active area
The overlapping portions of 14 and 16 and the impurity-implanted regions 20 and 22 each become a source region, and the overlapping portion of the drain-side active region 15 and the impurity-implanted region 11 becomes a drain region.

FIG. 3 is a sectional view of the semiconductor memory device taken along the line AA 'in FIG. FIG. 3 also shows the other two gate electrodes 9 and 9 respectively adjacent to the two gate electrodes 9 and 9 shown in FIG. A gate insulating film 36 is formed between the two gate electrodes 9 and 9 shown in FIG. The two gate electrodes 9 and 9 newly shown in FIG.
It is formed directly on 29. The interlayer insulating film 37 is formed so as to cover other parts of the substrate 1 and all the gate electrodes 9 except for a part of the active region 2.

The semiconductor memory device further includes a capacitor 38. Each capacitor 38 includes a common upper plate electrode 24, lower plate electrode 26, and a capacitor dielectric film 25 formed therebetween. The lower plate electrode 26 is formed on the interlayer insulating film 37 and the portion of the active region 22 not covered by the interlayer insulating film 37. The portion of the active region 2 that contacts the lower plate electrode 26 is the storage contact
17 and 19. The impurity implantation regions 20 and 22 for forming the source region are formed in the surface region of the semiconductor substrate 1. Storage contacts as shown
17 and 19 are arranged so as to overlap a part of the impurity implantation regions 20 and 22, respectively.

N-type diffusion regions 28 are formed in impurity implantation regions 20 and 22 by impurity diffusion from storage contacts 17 and 19, respectively. N-type diffusion region
28 may be separated from the separation region 29 as in the region 28 on the left side in the figure. In contrast, storage contacts 17
Is larger than the width of the gate electrode.
The mold diffusion region 28 reaches the isolation region 29.

FIGS. 4, 5, and 6 are cross-sectional views of the semiconductor memory device taken along lines BB ', CC', and DD 'in FIG. 2, respectively. In FIG. 4, the impurity implanted regions 20, 22, and 11 are not seen, but in FIGS. 5 and 6, the impurity implanted region 11 for forming the drain region appears. The impurity implantation region 11 is provided in a surface region of the semiconductor substrate 1.

In FIG. 6, all the gate electrodes 9, 9... Are located on the element isolation region 29. A portion of the active region 2 that is not covered with the interlayer insulating film 37 is in contact with the bit line 27 and functions as a bit contact 18. In the impurity implantation region 11, an N-type diffusion region 28 is provided.
Is formed by impurity diffusion from the substrate.

In the semiconductor memory device configured as described above, since the impurity-implanted regions 20 and 22 overlap only a part of the source-side active regions 14 and 16, the source region is the same as that of the source-side active regions 14 and 16. It is formed only in part.
Further, only a part of the boundary between the source-side active regions 14 and 16 and the channel region adjacent thereto becomes the boundary between the corresponding source region and channel region.
Similarly, the drain region is formed only in a part of the drain-side active region 15, and only a part of the boundary between the drain-side active region 15 and the channel region adjacent thereto is formed at the boundary between the drain region and the channel region. Become.

In the semiconductor memory device of this embodiment, each MOS
The impurity implantation region 20 or 22 of the
Although formed for the source side active region 14 or 16 of the S-type transistor itself, the configuration of the present invention is not limited to this. Two adjacent source-side active regions in different MOS transistors may share one impurity-implanted region. Further, the two active regions on the source side and the active region on the drain side located therebetween may share one impurity implantation region.

(Embodiment 2) FIG. 7 is a partial plan view of another embodiment of the semiconductor memory device of the present invention. The semiconductor memory device of the present embodiment differs from the semiconductor memory device of the first embodiment only in that a Y-shaped active region is provided instead of the T-shaped active region. Therefore, the same components as those of the semiconductor memory device according to the first embodiment are denoted by the same reference numerals as those shown in FIGS.

In the semiconductor memory device of the present embodiment, a plurality of Y-shaped active regions 32,
33, 34, and 35 are formed, and a plurality of gate electrodes 9, 9,... Are formed on the semiconductor substrate 1. Active area 3
The arrangement of 2, 33, 34 and 35 is based on a folded bit line scheme. The portions of each of the Y-shaped active regions 32, 33, 34, and 35 extending downward in the drawing are sandwiched between two gate electrodes 9, 9.

As in the first embodiment, the active regions 32, 33, 34 and 35 are arranged in rows parallel to the gate electrodes 9, 9,. The row of active areas 32 and 35 and the row with active area 33 and the row with active area 34 are arranged so as to be alternately out of phase so that the spacing between each active area is substantially uniform. ing. Therefore, even when the semiconductor memory device is highly integrated and the interval between the active regions is narrowed, the active regions can be easily separated by using only the trench isolation method.

In the semiconductor memory device of this embodiment, as shown in FIG. 2, each MOS transistor has an independent impurity implantation region, but the present invention is not limited to this. As shown in FIG. 10 described later, a plurality of adjacent MOS transistors may share one injection region.

(Embodiment 3) FIG. 8 is an enlarged plan view of an active region in still another embodiment of the semiconductor memory device of the present invention. In the semiconductor memory device of the present embodiment, the semiconductor substrate
An active region 51 is formed in a surface region of the semiconductor device 50, and a gate electrode 52 is formed on the semiconductor substrate 50. The active region 51 has a source-side active region 53 and a drain-side active region 54. The contact region is located above the drain-side active region 54 in the drawing.
57 are provided, and a contact region 56 is provided below the source-side active region 53 in the figure. Gate electrode of active region 51
The portion covered by 52 functions as a channel region 55. A MOS transistor is constituted by the gate electrode 52 and the active region 51.

The impurity implanted region 58 for forming the source region covers a part of the source side active region 53 and a part of the contact region 56, and the impurity implanted region 59 for forming the drain region is formed on the drain side. Part of the active region 54 and part of the contact region 57 are covered. Therefore, the source region is formed only in a part of the source-side active region 53, and only a part of the boundary between the source-side active region 53 and the adjacent channel region 55 is formed at the boundary between the source region and the channel region 55. Becomes Similarly, the drain region is formed only in a part of the drain-side active region 54, and only a part of the boundary between the drain-side active region 54 and the adjacent channel region 55 is formed at the boundary between the drain region and the channel region 55. Part.

In the semiconductor memory device of this embodiment shown in FIG. 8, a part of the impurity implanted regions 58 and 59 extends to the element isolation region, but the present invention is not limited to this. As shown in the modification shown in FIG. 9, the entire impurity implantation regions 68 and 69 may be arranged inside the active region 61. Except for the difference in the position of the impurity implanted region,
The modification of FIG. 9 has the same structure as the embodiment shown in FIG.

(Embodiment 4) FIG. 10 is a partial plan view of still another embodiment of the semiconductor memory device of the present invention. In the semiconductor memory device of this embodiment, a plurality of V-shaped active regions 41 are formed in the surface region of the semiconductor substrate 40,
A plurality of gate electrodes 42 are formed thereon. Each active region 41 has two source-side active regions 43 and one drain-side active region 44. Source side active area 43
The drain-side active region 44 has contact regions 46 and 47, respectively. Gate electrode 42 of active region 41
The portion covered with the functions as a channel region. The active region 41 and the gate electrode 42 crossing the active region 41 constitute a MOS transistor.

The impurity implanted region 49 is formed in each source side active region.
43, a part of each drain-side active region 44, and a part of each of the contact regions 46 and 47. Therefore, the source region is formed only in a part of the source side active region 43,
Only a part of the boundary between the source-side active region 43 and the channel region adjacent thereto becomes the boundary between the source region and the channel region. Similarly, the drain region is formed only in a part of the drain-side active region 44, and only a part of the boundary between the drain-side active region 44 and the channel region adjacent thereto is formed at the boundary between the drain region and the channel region. Become.

(Embodiment 5) FIG. 11 is a partial plan view of still another embodiment of the semiconductor memory device of the present invention. In the semiconductor memory device of this embodiment, a plurality of oblique active regions 101 are formed in the surface region of the semiconductor substrate 100, and a plurality of gate electrodes 102 are formed on the semiconductor substrate 100. Each oblique-type active region 101 obliquely crosses the gate electrode 102 and has two source-side active regions 103 and one drain-side active region 104. The source side active region 103 and the drain side active region 104 have contact regions 106 and 107, respectively. The portion of the active region 101 covered with the gate electrode 102 functions as a channel region. The active region 101 and the gate electrode 102 crossing the active region 101 form a MOS transistor. BL indicates a region where a bit line is wired.

The impurity implanted region 109 covers a part of each source side active region 103, a part of each drain side active region 104, a part of each contact region 106, and the entire surface of each contact region 107. Therefore, the source region is formed only in a part of the source-side active region 103 and the source-side active region 103 is formed.
Only a part of the boundary between the source region and the channel region becomes the boundary between the source region and the channel region. Similarly, the drain region is formed only in a part of the drain-side active region 104, and only a part of the boundary between the drain-side active region 104 and the channel region adjacent thereto is formed at the boundary between the drain region and the channel region. Become.

As is clear from the above description, in the semiconductor memory devices in all the above-mentioned embodiments, only a part of the boundary between the source side active region and the channel region adjacent thereto is formed between the source region and the channel region. And only a part of the boundary between the drain-side active region and the channel region adjacent to the drain-side active region is the boundary between the drain region and the channel region. Therefore, in a heat treatment step performed after impurity ion implantation, impurity ions are transferred from the source region and the drain region to the channel region through only a part of the boundary between the source-side active region and the drain-side active region and the channel region. Due to thermal diffusion, the effective channel length of the channel region is not significantly reduced, and is not easily affected by the short channel effect even in fine design rules. Therefore, malfunction of the semiconductor memory device can be reduced.

Further, in the semiconductor memory device of the present invention, the impurity-implanted region for forming the source region overlaps only a part of the source-side active region, and the impurity-implanted region for forming the drain region is formed as the drain-side active region. , And the resulting area of the source region and the drain region is smaller than that in the case where the impurity-implanted region covers the entire active region. Therefore, the junction capacitance generated between the semiconductor substrate and the source region and the drain region is reduced, whereby the parasitic capacitance of the semiconductor memory device can be reduced.

Therefore, according to the present invention, by limiting the impurity-implanted region as described above, two effects, that is, a short channel effect and a junction capacitance are reduced. These two effects, the LDD (Raitoryi-doped drain) Step N ^- performs only (low concentration) ion implantation, in case of no N ⁺ (high-concentration) ion implantation, becomes more pronounced.

[0048]

According to the present invention, a semiconductor memory device in which the short channel effect is reduced and the junction capacitance between the semiconductor substrate and the source and drain regions is reduced.
In such a semiconductor memory device, the malfunction of the memory cell is reduced, the reliability of the memory operation is improved, and an increase in current consumption and a decrease in driving capability of the MOS transistor are prevented. Further, by employing an arrangement in which the distances between the active regions are substantially equal, the active regions can be easily separated by a single element isolation technique.

[Brief description of the drawings]

FIG. 1 is a partial plan view of a semiconductor memory device of the present invention.

FIG. 2 is an enlarged plan view showing an active region of the semiconductor memory device of FIG.

FIG. 3 is a sectional view of the semiconductor memory device taken along line AA ′ of FIG. 2;

FIG. 4 is a cross-sectional view of the semiconductor memory device taken along line BB ′ of FIG. 2;

FIG. 5 is a cross-sectional view of the semiconductor memory device along the line CC ′ in FIG. 2;

FIG. 6 is a sectional view of the semiconductor memory device taken along line DD ′ of FIG. 2;

FIG. 7 is a partial plan view of another semiconductor memory device of the present invention.

FIG. 8 is an enlarged plan view showing an active region of still another semiconductor memory device of the present invention.

9 is an enlarged plan view showing an active region of a modification of the semiconductor memory device of FIG. 8;

FIG. 10 is a partial plan view of still another semiconductor memory device of the present invention.

FIG. 11 is a partial plan view of still another semiconductor memory device of the present invention.

FIG. 12 is an enlarged plan view showing a memory cell portion of a conventional semiconductor memory device.

FIG. 13 is a partial plan view of the conventional semiconductor memory device shown in FIG.

[Explanation of symbols]

1,40,50,60,70,100 Semiconductor substrate 2,3,4,5,6,7,8,32,33,34,35,41,5
1, 61, 72, 88, 89, 90, 91, 92, 93, 94, 95, 101 Active regions 9, 42, 52, 62, 73, 74, 96, 102 Gate electrodes 11, 20, 22, 49, 58, 59, 68, 69, 71, 109 Impurity implanted regions 14, 16, 43, 53, 63, 75, 77, 103 Source-side active regions 15, 44, 54, 64, 76, 104 Drain-side active regions 17, 19, 78, 80, 106 Storage contact 18, 79, 107 Bit contact 46, 47, 56, 57, 66, 67 Contact area 55, 65, 81, 82 Channel area

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tsukasa Doi 22-22 Nagaikecho, Abeno-ku, Osaka-shi Inside Sharpe Co., Ltd. (56) References JP-A-1-123463 (JP, A) JP-A-2-81474 (JP, A)

Claims (1)

(57) [Claims] 1. A semiconductor memory device having a plurality of memory cells, wherein each of the memory cells includes an active region having a MOS transistor formed in a surface region of a semiconductor substrate; The MO formed on the substrate is divided into a source side active region having a storage contact and a drain side active region having a bit contact.
A gate electrode of the S-type transistor , at least one of the storage contact and the gate electrode;
Formed on a part of the source side active area so as to overlap with a part
The first impurity implanted region, and at least a part of the bit contact and the gate electrode
Formed in a part of the drain side active region so as to overlap with
And a portion of the active region located below the gate electrode.
A source region overlapping with the first impurity implantation region.
The source side region is used as the source region, and the second impurity
Drain the portion of the drain side active region that overlaps the implantation region.
A semiconductor memory device in which the MOS type transistor serving as a transistor region is formed .