JP5452911B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a capacitor.

  As a kind of nonvolatile memory, there is known an FeRAM (Ferroelectric Random Access Memory) that retains data by using a hysteresis (history phenomenon) of a ferroelectric substance.

  There are two types of FeRAM, which are roughly classified according to the difference in cell structure. One has a 1T1C type cell structure including a field effect transistor for selecting a memory cell and a ferroelectric capacitor, and the other has a field effect transistor whose gate insulating film is made of a ferroelectric. It has a 1T type cell structure.

  FIG. 4 is a schematic plan view of a FeRAM having a conventional 1T1C type cell structure.

  The FeRAM includes a P-type silicon substrate (not shown). An element isolation portion (for example, a LOCOS oxide film) is selectively formed on the surface of the silicon substrate, and a plurality of rectangular active regions 101 in plan view are exposed from the element isolation portion. The active regions 101 are arranged in a matrix that is aligned in the longitudinal direction and in a direction orthogonal to the longitudinal direction.

  In the active region 101, two memory cells are formed. Each memory cell has a 1T1C type cell structure.

  N-type impurity regions are formed at both ends and a central portion of the active region 101 in the longitudinal direction in the surface layer portion of the silicon substrate at intervals. The impurity region at one end of the active region 101 forms a drain region of a field effect transistor provided in one memory cell. The impurity region at the other end of the active region 101 forms a drain region of a field effect transistor provided in the other memory cell. The impurity region at the center of the active region 101 forms a source region common to the field effect transistors included in the two memory cells.

  On the silicon substrate, a gate electrode 102 is provided at a position facing each channel region between the source region and each drain region. The gate electrodes 102 of the field effect transistors arranged in a direction orthogonal to the longitudinal direction of the active region 101 are integrated to form one word line WL.

  An interlayer insulating film is stacked on the silicon substrate. On the interlayer insulating film, a ferroelectric capacitor 103 is provided at a position facing the drain region of each memory cell (above one end and the other end in the longitudinal direction of the active region 101). The ferroelectric capacitor 103 has a laminated structure in which a ferroelectric film is interposed between the lower electrode 104 and the upper electrode 105.

  The lower electrode 104 has a substantially square shape in plan view. A first contact plug 106 is provided through the interlayer insulating film between the center portion of the lower electrode 104 and the drain region. The lower electrode 104 is electrically connected to the drain region via the first contact plug 106.

  The upper electrode 105 has a substantially square shape in plan view smaller than the lower electrode 104. Above the central portion of the upper electrode 105, the plate line PL extends in a direction orthogonal to the longitudinal direction of the active region 101. The plate line PL is electrically connected to the upper electrode 105.

  In addition, the bit line BL extends in the longitudinal direction of the active region 101 above the active region 101. The bit line BL is electrically connected to the source region at the center of the active region 101 via the second contact plug 107.

When a voltage is applied between the plate line PL and the bit line BL in a state where the field effect transistor is turned on by applying a voltage to the word line WL, spontaneous polarization is applied to the ferroelectric film of the ferroelectric capacitor 103. Occurs. As a result, data writing is achieved and the polarization state is maintained, so that the data is retained. At the time of reading data, a pulse voltage is applied between the plate line PL and the bit line BL while the field effect transistor is turned on by applying a voltage to the word line WL. When the polarization direction of the ferroelectric film changes due to the application of the pulse voltage, a current flows between the plate line PL and the bit line BL, so that a logic signal “1” or “0” is obtained depending on the presence or absence of the current. be able to.
JP 2004-95915 A

  FeRAM has design rules. In this design rule, the minimum distance between the gate electrode 102 and the first contact plug 106, the minimum distance between the peripheral edge of the lower electrode 104 and the first contact plug 106, the first contact plug 106 and the second contact. A minimum distance from the plug 107 is determined. In order to increase the ratio of the area of the ferroelectric capacitor (capacitor area) to the area of the memory cell (cell area) while complying with the design rule, it is necessary to devise the layout of each part of the FeRAM. As the ratio of the capacitor area to the cell area is larger, the operation margin (operation stability) of the FeRAM is improved.

  Accordingly, an object of the present invention is to provide a semiconductor device capable of increasing the ratio of the capacitor area to the cell area while following the design rule.

In order to achieve the above object, the invention according to claim 1 is a semiconductor layer of a first conductivity type, an element isolation portion that is selectively formed on the surface of the semiconductor layer and separates a plurality of active regions from each other; In each active region, a first impurity region of a second conductivity type formed in the surface layer portion of the semiconductor layer, and in each active region, formed in the surface layer portion of the semiconductor layer with a space from the first impurity region. A second impurity region of a second conductivity type, a gate electrode formed on the semiconductor layer and facing a region between the first impurity region and the second impurity region, and above the first impurity region. A lower electrode formed on the upper electrode; an upper electrode formed on the lower electrode; a ferroelectric film interposed between the lower electrode and the upper electrode; and a plate formed above the upper electrode. Line and bottom A plate via connected to the upper electrode and having an upper end connected to the plate line; and a position overlapping the plate via in plan view; an upper end connected to the lower electrode; and a lower end connected to the first impurity region A capacitor contact plug connected to the second impurity region, a bit line formed above the second impurity region, and a bit contact plug having a lower end connected to the second impurity region and electrically connected to the bit line. The active region includes a straight region extending in a predetermined direction and a T-shape in a plan view having an orthogonal region orthogonal to the linear region in the center of the predetermined direction of the linear region, and the adjacent active regions are Orthogonal to the predetermined direction so that they do not deviate from each other in either the predetermined direction or the direction orthogonal to the predetermined direction Are formed side by side in the direction, and a recess is formed on the side of the active region opposite to the side where the orthogonal region is formed, and the first impurity region is formed in each active region. The second impurity region is formed at each end of the orthogonal region of each active region, and the bit contact plug is adjacent to a direction perpendicular to the predetermined direction. Arranged at the center of a quadrangle having the capacitor contact plugs connected to the four first impurity regions formed in the active region as apexes, and comprising the lower electrode, the upper electrode, and the ferroelectric film The semiconductor device includes a ferroelectric capacitor, and the ferroelectric capacitor has a pentagonal shape in plan view .

  In this semiconductor device, an element isolation portion for isolating a plurality of active regions from each other is selectively formed on the surface of the first conductivity type semiconductor layer. Each active region has a T-shape in plan view having a linear region extending in a predetermined direction and an orthogonal region orthogonal to the linear region at the center of the linear region in the predetermined direction. A plurality of active areas are formed side by side in a direction orthogonal to the predetermined direction. At both ends of the straight line region, a first impurity region of the second conductivity type is formed in the surface layer portion of the semiconductor layer. A second impurity region of the second conductivity type is formed in the surface layer portion of the semiconductor layer at the end of the orthogonal region. A gate electrode is provided on the semiconductor layer. The gate electrode is opposed to a region between the first impurity region and the second impurity region. A capacitor including a lower electrode and an upper electrode is formed above the first impurity region. The first impurity region and the lower electrode are electrically connected via a capacitive contact plug. A bit line is formed above the second impurity region. The second impurity region and the bit line are electrically connected via a bit contact plug.

The bit contact plug is arranged at the center of a quadrangle with the capacitor contact plugs connected to the four first impurity regions formed in the two active regions adjacent to each other in the direction orthogonal to the predetermined direction. . As a result, the distance between the two capacitor contact plugs arranged in the predetermined direction can be reduced while ensuring the minimum distance defined by the design rule between the capacitor contact plug and the bit contact plug. As a result, the cell area can be reduced. In addition, the area of the capacitor can be expanded in a predetermined direction while ensuring the minimum distance determined by the design rule between the bit contact plug and the lower electrode in plan view. As a result, the capacitor area can be increased. Therefore, it is possible to increase the ratio of the capacitor area to the cell area while following the design rule.
In addition, a recess is formed on the side opposite to the side where the orthogonal region is formed in the straight region of the active region. When a plurality of active regions are formed side by side in a direction orthogonal to the predetermined direction, the adjacent active regions are arranged such that the concave portion formed in the linear region and the orthogonal region face each other. In this way, when the concave portion is formed in the active region, the adjacent active regions can be formed closer to each other as compared with the case of the active region in which the concave portion is not formed. Thereby, the integration degree of the semiconductor device can be further improved.

The semiconductor device includes a plate line formed above the upper electrode, the lower end is connected to the upper electrode, and further a plate via which the upper end is connected to the plate line.

Capacity contact plug and plate vias are overlap in plan view. With this layout, the same photomask (reticle) can be used for the photolithography process when forming the capacitor contact plug and the photolithography process when forming the plate via.

The semiconductor device further includes a ferroelectric film interposed between the lower electrode and the upper electrode. That is, the semiconductor device includes a ferroelectric capacitor including a lower electrode, an upper electrode, and a ferroelectric film interposed therebetween . Before SL ferroelectric capacitor is formed in a plan view pentagonal shape.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic plan view of an FeRAM according to the first embodiment of the present invention. FIG. 2 is a circuit diagram of the FeRAM shown in FIG. 3 is a schematic cross-sectional view taken along section line III-III of FeRAM shown in FIG.

  The FeRAM 1 includes a plurality of memory cells. Each memory cell has a 1T1C type cell structure. 1 and 2 show a part of the FeRAM 1. In FIG. 2, one memory cell is surrounded by a broken line.

  The FeRAM 1 includes a P-type semiconductor layer 2 as shown in FIG. The semiconductor layer 2 may be a semiconductor substrate such as a Si (silicon) substrate or a SiC (silicon carbide) substrate, or may be a Si layer or a SiC layer formed by epitaxial growth or a CVD method.

  An element isolation portion 4 is selectively formed on the surface of the semiconductor layer 2 while avoiding a plurality of active regions 3. The element isolation portion 4 may have, for example, an STI (Shallow Trench Isolation) structure in which an insulator is embedded in a groove dug relatively shallow from the surface of the semiconductor layer 2 or a LOCOS (Local Oxidation of). A silicon oxide film selectively formed on the surface of the semiconductor layer 2 by the silicon method may be used.

In FIG. 1, the outline of the active region 3 is indicated by a bold line. The active regions 3 are arranged in a matrix that is aligned in the row direction and the column direction at regular intervals in the row direction and the column direction. More specifically, each active region 3 is formed such that adjacent active regions 3 do not deviate from each other in either the row direction or the column direction. Each active region 3 has a T-shape in plan view having a linear region 3A extending in the column direction and an orthogonal region 3B orthogonal to the linear region 3A at the center of the linear region 3A in the column direction. The linear area 3A of each active area 3 is arranged on one side in the row direction with respect to the orthogonal area 3B. A concave portion is formed on the side opposite to the side where the orthogonal region 3B is formed in the linear region 3A of each active region 3, and the adjacent active regions 3 are formed in the linear region 3A. The recess and the orthogonal region 3B are arranged so as to face each other.

  In each active region 3, as shown in FIG. 3, impurities for two N-channel MOSFETs (hereinafter referred to as “NMOS”) 5 are formed in the surface layer portion of the semiconductor layer 2. Regions 6 and 7 are formed. The impurity regions 6 are formed at both ends of the linear region 3 </ b> A and form the drain regions of the two NMOSs 5. The impurity region 7 is formed at the end of the orthogonal region 3B of the active region 3 and forms a common source region for the two NMOSs 5.

On the semiconductor layer 2, a gate insulating film 8 is formed at a position facing the region between the drain region 6 and the source region 7 (the channel region of the NMOS 5). The gate insulating film 8 is made of, for example, SiO ₂ (silicon oxide). A gate electrode 9 is formed on the gate insulating film 8. The gate electrode 9 is made of, for example, doped polysilicon (for example, polysilicon doped with an N-type impurity at a high concentration). A sidewall 10 is formed around the gate electrode 9. The sidewall 10 covers the entire circumference of the side surfaces of the gate insulating film 8 and the gate electrode 9. The sidewall 10 is made of, for example, SiN (silicon nitride) or SiO ₂ .

  As shown in FIGS. 1 and 2, the gate electrodes 9 of the NMOSs 5 arranged in the row direction are integrated to form word lines WL1, WL2,. The word lines WL1, WL2,... Are formed in a straight line extending in the row direction perpendicular to the regions other than the drain region 6 in the linear region 3A in plan view on both sides in the column direction of the active region 3 with respect to the orthogonal region 3B. Has been.

As shown in FIG. 3, a first interlayer insulating film 11 is stacked on the semiconductor layer 2. The first interlayer insulating film 11 is made of, for example, SiO ₂ .

A ferroelectric capacitor 12 is disposed on the first interlayer insulating film 11 at a position facing each drain region 6. The ferroelectric capacitor 12 has a structure in which a lower electrode 13, a ferroelectric film 14 and an upper electrode 15 are laminated on the first interlayer insulating film 11 in this order. In other words, the ferroelectric capacitor 12 has a structure in which the ferroelectric film 14 is interposed between the lower electrode 13 and the upper electrode 15. The ferroelectric capacitor 12 has a pentagonal shape (home base shape) in which a rectangular portion and a substantially isosceles triangular portion are coupled in plan view. In addition, the ferroelectric capacitor 12 has a trapezoidal cross section with the upper portion narrowed due to difficulty in etching at the time of formation.

  The lower electrode 13 has a pentagonal shape (home base shape) in which a rectangular portion and a substantially isosceles triangular portion are coupled in plan view. The lower electrode 13 is made of a conductive material containing a noble metal such as Ir.

The ferroelectric film 14 has a pentagonal shape in plan view that is similar to the lower electrode 13 and smaller than the lower electrode 13 and larger than the upper electrode 15. The ferroelectric film 14 is made of, for example, PZT (Pb (Zr, Ti) O ₃ : lead zirconate titanate).

The upper electrode 15 has a pentagonal shape in plan view that is similar to the lower electrode 13 and smaller than the lower electrode 13. The upper electrode 15 has a structure in which, for example, an IrO ₂ (iridium oxide) film, an Ir (iridium) film, and an IrTa (iridium tantalum) alloy film are laminated on the ferroelectric film 14 in this order. The IrTa alloy film has a hydrogen barrier property.

Each surface of the first interlayer insulating film 11 and the ferroelectric capacitor 12 is covered with a hydrogen barrier film 16 for preventing characteristic deterioration due to hydrogen reduction of the ferroelectric film 14. The hydrogen barrier film 16 is made of, for example, Al ₂ O ₃ (alumina).

A second interlayer insulating film 17 is laminated on the hydrogen barrier film 16. The second interlayer insulating film 17 is made of, for example, SiO ₂ .

  As shown in FIGS. 1 and 2, the FeRAM 1 further includes plate lines PL1, PL2,... And bit lines BL1, BL2,. The plate lines PL1, PL2,... And the bit lines BL1, BL2,... Are separated from each other by an interlayer insulating film (not shown) above the second interlayer insulating film 17, for example. Formed in layers.

  The plate lines PL1, PL2,... Extend substantially linearly via the center of the upper electrode 15 of each ferroelectric capacitor 12 aligned in the row direction. The plate lines PL1, PL2,... Are made of, for example, Al (aluminum).

  The bit lines BL1, BL2,... Extend in a straight line passing over the source region 7 formed in each active region 3 arranged in the column direction. The bit lines BL1, BL2,... Are made of Al, for example.

  As shown in FIG. 3, in the first interlayer insulating film 11, a capacitor contact plug 18 is buried between each drain region 6 and the lower electrode 13 of the ferroelectric capacitor 12 facing the drain region 6. As shown in FIG. 1, the capacitor contact plugs 18 on the two drain regions 6 of each active region 3 are arranged at positions symmetrical with respect to the center in the column direction of the linear region 3 </ b> A of the active region 3.

  As shown in FIG. 3, each capacitor contact plug 18 is buried in a capacitor contact hole 19 penetrating the first interlayer insulating film 11 via a barrier metal 20. The barrier metal 20 covers the side surface of the capacitor contact hole 19 and the portion of the drain region 6 that faces the capacitor contact hole 19. As a result, the lower end of the capacitor contact plug 18 is connected to the drain region 6 through the barrier metal 20, and the upper end thereof is opposite to the word lines WL1, WL2,... It is connected to a position shifted to the outside of the opposite direction of both ends of the linear region 3A. The capacitor contact plug 18 is made of, for example, W (tungsten). The barrier metal 20 is made of, for example, TiN (titanium nitride).

  In the second interlayer insulating film 17, a plate via 21 is embedded between the upper electrode 15 of each ferroelectric capacitor 12 and the plate lines PL1, PL2,. Specifically, a plate via hole 22 is formed in the second interlayer insulating film 17 at a position overlapping the capacitor contact hole 19 in plan view. The plate via hole 22 penetrates the second interlayer insulating film 17, further penetrates the hydrogen barrier film 16, and its lower end reaches the upper electrode 15. A barrier metal 23 is formed on the side surface of the plate via hole 22 and on the portion of the upper electrode 15 and the hydrogen barrier film 16 that faces the plate via hole 22. The barrier metal 23 is made of TiN, for example. The plate via 21 is embedded in the plate via hole 22 via the barrier metal 23. As a result, the lower end of the plate via 21 is connected via the barrier metal 23 to a position shifted from the center of the upper electrode 15 to the side opposite to the word lines WL1, WL2,. It is connected to lines PL1, PL2,.

  In addition, above each source region 7, a bit contact hole 24 that penetrates the first interlayer insulating film 11 and a bit via hole 25 that continuously penetrates the hydrogen barrier film 16 and the second interlayer insulating film 17 communicate with each other. Is formed. A barrier metal 26 made of the same material as the barrier metal 20 is formed on the side surface of the bit contact hole 24 and on the portion of the source region 7 facing the bit contact hole 24. A bit contact plug 27 made of the same material as that of the capacitor contact plug 18 is embedded inside the barrier metal 26. Thus, the lower end of the bit contact plug 27 is connected to the source region 7 via the barrier metal 26. On the other hand, a barrier metal 28 made of the same material as the barrier metal 23 is formed on the side surface of the bit via hole 25 and on the portion of the hydrogen barrier film 16 and the bit contact plug 27 that faces the bit via hole 25. A bit via 29 made of the same material as that of the plate via 21 is embedded inside the barrier metal 28. The bit contact plug 27 is electrically connected to the bit lines BL1, BL2,... Via the barrier metal 28 and the bit via 29.

  The position of the active region 3 in the row direction is a bit centered on a square centered at the capacitor contact plug 18 connected to the four drain regions 6 formed in the two active regions 3 adjacent in the row direction. The contact plug 27 is set to be disposed.

  When the NMOS 5 is turned on by applying a voltage to the word lines WL1, WL2,..., A voltage is applied between the plate lines PL1, PL2,. Then, spontaneous polarization occurs in the ferroelectric film 14 of the ferroelectric capacitor 12. As a result, data writing is achieved and the polarization state is maintained, so that the data is retained. When reading data, the NMOS 5 is turned on by applying a voltage to the word lines WL1, WL2,..., And between the plate lines PL1, PL2,. A pulse voltage is applied to. When the polarization direction of the ferroelectric film 14 is changed by application of the pulse voltage, current flows between the plate lines PL1, PL2,... And the bit lines BL1, BL2,. Thus, the logic signal “1” or “0” can be obtained.

  As described above, in FeRAM 1, a plurality of active regions 3 are formed side by side in the row direction. Each active region 3 has a T-shape in plan view having a linear region 3A extending in the column direction and an orthogonal region 3B orthogonal to the linear region 3A at the center of the linear region 3A in the column direction. N-type drain regions 6 are formed in the surface layer portion of the P-type semiconductor layer 2 at both ends of the linear region 3A. An N-type source region 7 is formed in the surface layer portion of the semiconductor layer 2 at the end of the orthogonal region 3B. A gate electrode 9 is provided on the semiconductor layer 2. The gate electrode 9 is opposed to a region between the drain region 6 and the source region 7. A ferroelectric capacitor 12 including a lower electrode 13, a ferroelectric film 14 and an upper electrode 15 is formed above the drain region 6. The drain region 6 and the lower electrode 13 are electrically connected via a capacitor contact plug 18. In addition, bit lines BL1, BL2,... Are formed above the source region 7. The source region 7 and the bit lines BL1, BL2,... Are electrically connected via a bit contact plug 27.

  The bit contact plug 27 is arranged at the center of a quadrangle with the capacitor contact plugs 18 connected to the four drain regions 6 formed in the two active regions 3 adjacent in the row direction as apexes. As a result, the distance between the two capacitor contact plugs 18 arranged in the column direction can be reduced while ensuring the minimum distance determined by the design rule between the capacitor contact plug 18 and the bit contact plug 27. As a result, the cell area can be reduced. Further, the area of the ferroelectric capacitor 12 can be expanded in the column direction while ensuring the minimum distance defined by the design rule between the bit contact plug 27 and the lower electrode in plan view. As a result, the capacitor area can be increased. Therefore, it is possible to increase the ratio of the capacitor area to the cell area while following the design rule.

Further, since the capacitor contact plug 18 and the plate via 21 are formed at positions overlapping in plan view, the same photomask is used for the photolithography process when the capacitor contact plug 18 is formed and the photolithography process when the plate via 21 is formed. (Reticle) can be used.
Further, a concave portion is formed on the side opposite to the side where the orthogonal region 3B is formed in the linear region 3A of the active region 3. When a plurality of active regions 3 are formed side by side in the row direction, the adjacent active regions 3 are arranged such that the concave portions formed in the linear region 3A and the orthogonal region 3B face each other. Thus, when the recessed part is formed in the active area | region 3, compared with the case of the active area | region where the recessed part is not formed, the adjacent active region 3 can be formed still closer. Thereby, the integration degree of the semiconductor device 1 can be further improved.

  Although one embodiment of the present invention has been described above, various design changes can be made to the embodiment within the scope of the matters described in the claims.

  For example, the present invention can be applied not only to FeRAM but also to a DRAM (Dynamic Random Access Memory) including a paraelectric capacitor.

FIG. 1 is a schematic plan view of an FeRAM according to the first embodiment of the present invention. FIG. 2 is a circuit diagram of the FeRAM shown in FIG. 3 is a schematic cross-sectional view taken along section line III-III of FeRAM shown in FIG. FIG. 4 is a schematic plan view of a conventional FeRAM.

Explanation of symbols

1 FeRAM
2 Semiconductor layer 3 Active region 3A Linear region 3B Orthogonal region 4 Element isolation part 6 Drain region 7 Source region 9 Gate electrode 12 Ferroelectric capacitor 13 Lower electrode 14 Ferroelectric film 15 Upper electrode 18 Capacitor contact plug 21 Plate via 27 bit Contact plug BL1, BL2 Bit line PL1, PL2 Plate line WL1, WL2 Word line

Claims (1)

A first conductivity type semiconductor layer;
An element isolation portion that is selectively formed on the surface of the semiconductor layer and isolates a plurality of active regions from each other;
In each active region, a first impurity region of a second conductivity type formed in a surface layer portion of the semiconductor layer;
In each active region, a second impurity region of a second conductivity type formed in the surface layer portion of the semiconductor layer and spaced from the first impurity region;
A gate electrode formed on the semiconductor layer and facing a region between the first impurity region and the second impurity region;
A lower electrode formed above the first impurity region;
An upper electrode formed on the lower electrode;
A ferroelectric film interposed between the lower electrode and the upper electrode;
A plate line formed above the upper electrode;
A plate via having a lower end connected to the upper electrode and an upper end connected to the plate line;
A capacitor contact plug formed at a position overlapping the plate via in plan view, and having an upper end connected to the lower electrode and a lower end connected to the first impurity region;
A bit line formed above the second impurity region;
A bit contact plug having a lower end connected to the second impurity region and electrically connected to the bit line;
The active region has a T-shape in plan view having a linear region extending in a predetermined direction and an orthogonal region orthogonal to the linear region in the center of the linear region in the predetermined direction, and the adjacent active regions are in the predetermined direction And a plurality of them arranged in a direction orthogonal to the predetermined direction so as not to be shifted from each other in any of the directions orthogonal to the predetermined direction,
A concave portion is formed on the side opposite to the side on which the orthogonal region is formed in the linear region of the active region,
The first impurity regions are respectively formed at both ends of the linear region of each active region,
The second impurity region is formed at an end of the orthogonal region of each active region,
The bit contact plug is disposed at the center of a quadrangle having apexes of the capacitor contact plugs connected to the four first impurity regions formed in two active regions adjacent to each other in a direction orthogonal to the predetermined direction. and,
A ferroelectric capacitor comprising the lower electrode, the upper electrode and the ferroelectric film;
The ferroelectric capacitor is a semiconductor device having a pentagonal shape in plan view .

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