JP7272098B2 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

Ferroelectric memory, which stores logic according to the residual polarization value of a ferroelectric capacitor, is used in various devices as a non-volatile memory that combines the advantages of DRAM (Dynamic Random Access Memory) and flash memory. there is A ferroelectric capacitor is formed by sandwiching a ferroelectric film between electrodes. For example, there has been proposed a technique of forming a ferroelectric film of a ferroelectric capacitor so as to cover the entire memory cell region, thereby suppressing leakage generated between the upper electrode and the lower electrode (for example, See Patent Document 1).

JP-A-11-3977

A MIM (Metal-Insulator-Metal) capacitor in which an insulating film is sandwiched between metal films is known as a capacitor built into a semiconductor device. For example, an MIM capacitor is formed by laminating an insulating film and an electrode on a wiring formed in a wiring layer and connecting the electrode to the wiring of the upper wiring layer. However, when forming an MIM capacitor using a wiring layer, an empty area of a predetermined size is required in the wiring area. If it is difficult to form an MIM capacitor with a desired capacitance value between a pair of wiring layers, another wiring layer is also used to form the MIM capacitor. As the number of wiring layers forming the MIM capacitor increases, the number of manufacturing steps increases and the manufacturing cost rises. In addition, as the number of manufacturing processes increases, the yield, which is the percentage of non-defective products of semiconductor devices, decreases.

In one aspect, an object of the present invention is to form a capacitor of a desired size in a semiconductor device while suppressing an increase in the number of manufacturing steps.

According to one aspect, a semiconductor device includes a first electrode provided above a semiconductor substrate, a lower electrode provided above the semiconductor substrate, an insulating film, and an upper electrode stacked in order from the semiconductor substrate side. an electrically insulating protective film provided to cover the first element, the first electrode, and the first element to protect the first element; and a second electrode provided on the opposite side of the electrode, wherein the first electrode comprises a first conductive film, a first insulating film, and a second electrode, which are formed in order from the semiconductor substrate side. By patterning the conductive film, it is formed simultaneously with the lower electrode, the insulating film and the upper electrode, and has the same lamination structure as the first element.

According to one aspect of the present invention, a capacitor of a desired size can be formed in a semiconductor device while suppressing an increase in the number of manufacturing steps.

1 is a partial cross-sectional view showing an example of a semiconductor device according to one embodiment; FIG. 1 is a circuit diagram showing an example of a memory cell of a ferroelectric memory; FIG. It is a partial cross-sectional view showing an example of a semiconductor device in another embodiment. 4 is a partial cross-sectional view showing an example of a method of manufacturing the semiconductor device shown in FIG. 3; FIG. 5 is a partial cross-sectional view showing a continuation of the manufacturing method of FIG. 4; FIG. 6 is a partial cross-sectional view showing a continuation of the manufacturing method of FIG. 5; FIG. It is a partial sectional view showing an example of a manufacturing method of a semiconductor device in another embodiment. 8 is a partial cross-sectional view showing a continuation of the manufacturing method of FIG. 7; FIG. FIG. 9 is a partial cross-sectional view showing a continuation of the manufacturing method of FIG. 8; FIG. 10 is a partial cross-sectional view showing a continuation of the manufacturing method of FIG. 9; It is a partial sectional view showing an example of a manufacturing method of a semiconductor device in another embodiment. FIG. 12 is a partial cross-sectional view showing a continuation of the manufacturing method of FIG. 11; 13 is a partial cross-sectional view showing a continuation of the manufacturing method of FIG. 12; FIG. FIG. 14 is a partial cross-sectional view showing a continuation of the manufacturing method of FIG. 13; 15 is a partial cross-sectional view showing a continuation of the manufacturing method of FIG. 14; FIG. It is a partial cross-sectional view showing an example of a semiconductor device in another embodiment. 17 is a partial cross-sectional view showing an example of a method of manufacturing the semiconductor device shown in FIG. 16; FIG. FIG. 18 is a partial cross-sectional view showing a continuation of the manufacturing method of FIG. 17; FIG. 19 is a partial cross-sectional view showing a continuation of the manufacturing method of FIG. 18; FIG. 20 is a partial cross-sectional view showing a continuation of the manufacturing method of FIG. 19; It is a partial cross-sectional view showing an example of a semiconductor device in another embodiment. It is a partial cross-sectional view showing an example of a semiconductor device in another embodiment. FIG. 23 is an explanatory diagram showing the shape of the plug and wiring of FIG. 22 viewed from above the semiconductor device; 23 is a partial cross-sectional view showing an example of a method of manufacturing the semiconductor device shown in FIG. 22; FIG. FIG. 25 is a partial cross-sectional view showing a continuation of the manufacturing method of FIG. 24; 26 is a partial cross-sectional view showing a continuation of the manufacturing method of FIG. 25; FIG. It is a partial sectional view showing an example of a manufacturing method of a semiconductor device in another embodiment. FIG. 28 is a partial cross-sectional view showing a continuation of the manufacturing method of FIG. 27;

Embodiments will be described below with reference to the drawings. Note that in each cross-sectional view, the thickness and aspect ratio of wiring and films may be exaggerated for clarity of explanation, and may differ from the cross-sectional shape of the actual device.

FIG. 1 shows an example of a semiconductor device according to one embodiment. A semiconductor device 100 shown in FIG. 1 has an element such as a ferroelectric capacitor 10, for example. Semiconductor device 100 may be a ferroelectric memory having memory cells including ferroelectric capacitors 10 . Ferroelectric capacitor 10 is an example of a first element. For example, the ferroelectric capacitor 10 is formed by laminating a lower electrode 11, a ferroelectric film 12, and an upper electrode 13 in order on an interlayer insulating film 104 provided on a semiconductor substrate 101 such as silicon, and selectively separating the laminated three layers. are formed by collectively patterning. That is, the ferroelectric capacitor 10 is provided above the semiconductor substrate 101 . A dielectric film or an insulating film may be formed instead of the ferroelectric film 12 .

In the following description, the semiconductor device 100 is assumed to be a ferroelectric memory. Although elements such as transistors are formed on the semiconductor substrate 101, they are omitted from the drawing. The lower electrode 11 is connected to, for example, a transfer transistor provided on the semiconductor substrate 101 via a plug (through electrode) or the like formed in the interlayer insulating film 104 in a cross section different from the cross section shown in FIG. The upper electrode 13 is connected to, for example, a plate line through a plug formed in an interlayer insulating film 106 provided on an interlayer insulating film 104 in a cross section different from that shown in FIG.

The semiconductor device 100 has an electrode 21 on the interlayer insulating film 104 at a position separated from the ferroelectric capacitor 10 . That is, the electrode 21 is provided above the semiconductor substrate 101 . The semiconductor device 100 also has an electrically insulating protective film 30 provided on the interlayer insulating film 104 to cover the ferroelectric capacitor 10 and the electrode 21 . For example, the protective film 30 is provided along the top and side surfaces of the ferroelectric capacitor 10 and has the function of protecting the ferroelectric capacitor 10 . For example, the protective film 30 is a dielectric film.

For example, the protective film 30 is formed over the entire chip of the semiconductor device 100 covering not only the ferroelectric capacitor 10 but also the electrodes 21 . By covering the side surfaces of the ferroelectric capacitor 10 with the protective film 30, it is possible to prevent hydrogen, moisture, etc. from entering the ferroelectric capacitor 10. FIG. As a result, reduction of the ferroelectric film 12 by hydrogen can be suppressed, and deterioration of the characteristics of the ferroelectric capacitor 10 can be suppressed. In addition, the protective film 30 prevents hydrogen and moisture from passing between the lower portion and the upper portion of the protective film 30 .

The semiconductor device 100 has an electrode 22 provided on the opposite side of the electrode 21 with the protective film 30 interposed therebetween. For example, the electrode 21 is connected to a ground line or the like via a plug or the like formed in the interlayer insulating film 104 in a cross section different from that shown in FIG. The electrode 22 is connected to a power line or the like via a plug or the like formed in the interlayer insulating film 106 in a cross section different from that shown in FIG. A capacitor 20 (MIM capacitor) is formed by the electrodes 21 and 22 and the protective film 30 . The electrode 21 is an example of a first electrode, and the electrode 22 is an example of a second electrode.

In FIG. 1, the capacitor 20 can be formed by using the protective film 30 of the ferroelectric capacitor 10 as an insulating film. That is, by using the process of forming the protective film 30 of the ferroelectric capacitor 10, the insulating film of the capacitor 20 can be built into the layer forming the ferroelectric capacitor 10. FIG. Therefore, in addition to the step of forming the protective film 30, adding the step of forming the insulating film of the capacitor 20 can be omitted. In addition, after the protective film 30 is formed on the semiconductor substrate 101, patterning for forming the shape of the protective film 30 is not required. The process can be simplified. As a result, the number of manufacturing steps of the semiconductor device 100 can be reduced compared to the case where the insulating film for the capacitor 20 is formed separately from the protective film 30 and the protective film 30 is patterned.

For example, by connecting the electrodes 21 and 22 of the capacitor 20 to a power supply line and a ground line, respectively, the capacitor 20 can function as a smoothing capacitance element, and the power supply voltage can be stabilized. Also, the capacitor 20 can be used as a circuit element such as a capacitive element of a CR time constant circuit.

The ferroelectric capacitors 10 used as storage elements of memory cells are arranged at a high density in the area where the memory cell array is formed, but are not formed around the memory cell array. For this reason, for example, the capacitor 20 can be built in the formation region of decoders, drivers, sense amplifiers, write amplifiers, etc. formed around the memory cell array to control the operation of the memory cells. Therefore, the capacitor 20 having a large area can be formed in an arbitrary shape, and the capacitor 20 having a desired capacitance value can be formed in a single layer as compared with the case where the capacitor is formed in the empty area of the wiring in the wiring layer. be able to.

Since the capacitor 20 can be formed in the layer in which the ferroelectric capacitor 10 is formed, the number of manufacturing steps for forming the capacitor 20 can be reduced compared to the case of forming the capacitor using a plurality of wiring layers. , an increase in manufacturing cost of the semiconductor device 100 can be suppressed. Moreover, it is possible to suppress a decrease in yield due to an increase in the number of manufacturing processes. Therefore, the capacitor 20 having a desired size can be formed in the semiconductor device 100 while suppressing an increase in the number of manufacturing steps.

The semiconductor device 100 shown in FIG. 1 is manufactured as follows. The manufacturing method after the step of forming the interlayer insulating film 104 will be described below. First, a metal film for forming the electrode 21 is formed on the interlayer insulating film 104, and the metal film is selectively etched using a resist pattern as a mask to form the electrode 21. Next, as shown in FIG. Next, after the films of the lower electrode 11, the ferroelectric film 12 and the upper electrode 13 are sequentially formed on the insulating film 104, the resist pattern is used as a mask to collectively etch the portion where the ferroelectric capacitor 10 is not formed. and the ferroelectric capacitor 10 is formed. Plugs (not shown) connected to the electrode 21 and the lower electrode 11 are formed in the interlayer insulating film 104 in advance.

Next, protective film 30 is formed on interlayer insulating film 104 to cover ferroelectric capacitor 10 and electrode 21 . Next, a metal film for forming the electrodes 22 is formed on the protective film 30, and the metal film is selectively etched using the resist pattern as a mask to form the electrodes 22. Next, as shown in FIG. Thereafter, an interlayer insulating film 106 is formed, and through holes (not shown) penetrating through the interlayer insulating film 106 to the upper electrode 13 and the electrode 22 are formed. A plug is formed by filling the through-hole with a conductive material.

FIG. 2 shows an example of a memory cell MC of a ferroelectric memory. For example, memory cells MC of ferroelectric memories are roughly classified into 2T2C type and 1T1C type. A 2T2C type memory cell MC has a pair of transfer transistors T1 and T2 and a pair of ferroelectric capacitors C1 and C2. A 1T1C type memory cell MC has one transfer transistor T and one ferroelectric capacitor C. As shown in FIG. Ferroelectric capacitors C, C1, and C2 correspond to ferroelectric capacitor 10 shown in FIG. 1 and described later.

In the 2T2C type memory cell MC, gates of a pair of transfer transistors T1 and T2 are connected to a common word line WL. One of the source and drain of the transfer transistor T1 is connected to the bit line BL, and the other of the source and drain of the transfer transistor T1 is connected to one end of the ferroelectric capacitor C1. The other end of ferroelectric capacitor C1 is connected to plate line PL. One of the source and drain of the transfer transistor T2 is connected to the bit line /BL, and the other of the source and drain of the transfer transistor T2 is connected to one end of the ferroelectric capacitor C2. The other end of ferroelectric capacitor C2 is connected to plate line PL.

Sense amplifier SA is connected to bit line pair BL, /BL. The ferroelectric capacitors C1 and C2 are set to different polarization states in the write operation. For example, in a logic 1 write operation, ferroelectric capacitor C1 is set to a strongly polarized state and ferroelectric capacitor C2 is set to a weakly polarized state. In a logic 0 write operation, ferroelectric capacitor C1 is set to a weakly polarized state and ferroelectric capacitor C2 is set to a strongly polarized state.

In the read operation, after the bit lines BL and /BL are reset to low level, the plate line PL is driven to high level, and the floating bit lines BL and /BL are brought into the polarization state of the ferroelectric capacitors C1 and C2. The voltage is set accordingly. The sense amplifier SA differentially amplifies the voltage difference between the bit lines BL and /BL to read the logic held by the memory cell MC.

In the 1T1C type memory cell MC, the gate of the transfer transistor T is connected to the word line WL. One of the source and drain of the transfer transistor T is connected to one of the bit lines BL and /BL, and the other of the source and drain of the transfer transistor T is connected to one end of the ferroelectric capacitor C. FIG. The other end of ferroelectric capacitor C is connected to plate line PL.

The sense amplifier SA is connected to one of the bit line pair BL, /BL during a read operation. The ferroelectric capacitor C is set to one of two polarization states corresponding to logic ("1" or "0") of write data in a write operation. In the read operation, the read bit line (BL or /BL) connected to the ferroelectric capacitor C for reading data is set to a low level floating state, for example, and then the plate line PL is driven to a high level. The read bit line is set to a voltage corresponding to the polarization state of the ferroelectric capacitor C according to the driving of the plate line PL. The sense amplifier SA reads the logic held by the memory cell MC by differentially amplifying the voltage of the read bit line and the reference voltage VREF. For example, the reference voltage VREF is set to an intermediate voltage between two voltages of the read bit line which are respectively set according to the ferroelectric capacitors C in two polarization states.

As described above, in this embodiment, the capacitor 20 having a desired size can be formed in the semiconductor device 100 while suppressing an increase in the number of manufacturing processes. Moreover, since the capacitor 20 can be formed using the protective film 30 covering the side surface of the ferroelectric capacitor 10, the capacitor 20 of a desired size can be formed while protecting the ferroelectric film 12 from contamination.

FIG. 3 shows an example of a semiconductor device according to another embodiment. Elements similar to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. A semiconductor device 100A shown in FIG. 3 is, for example, a ferroelectric memory having memory cells each including a ferroelectric capacitor 10 . FIG. 3 shows memory cells MC (FIG. 2) including ferroelectric capacitors 10 and formation regions of capacitors 20. FIG. For example, a memory cell MC of a ferroelectric memory is of 1T1C type.

The semiconductor device 100A has an element isolation region STI (Shallow Trench Isolation) formed on the surface of a semiconductor substrate 101 such as silicon, and a well region WELL formed using the element isolation region STI as a mask. Note that the element isolation region is not limited to STI, and may be LOCOS (LOCal Oxidation of Silicon).

The semiconductor device 100A has a source region S and a drain region D formed on the surface of the semiconductor substrate 101 using the element isolation region STI and the gate electrode G as a mask. As shown in FIG. 3, for example, an LDD (Lightly Doped Drain) structure may be formed using the gate electrode G and the oxide film OX on the side walls of the gate electrode G as masks.

In FIG. 3, the illustration of the gate insulating film provided under the gate electrode G is omitted. For example, well region WELL is a p-type semiconductor, and source region S and drain region D are n-type semiconductors. The gate electrode G, source region S, and drain region D function as an n-channel MOS (Metal Oxide Semiconductor) transistor Tr (transfer transistor (one of T1, T2, and T shown in FIG. 2)). Note that the gate electrode G is part of the word line WL shown in FIG.

The semiconductor device 100A has an isolation region STI and an insulating film 201 covering the transistor. For example, the insulating film 201 is a silicon oxynitride (P--SiON) film. The semiconductor device 100A also has an interlayer insulating film 102, an insulating film 202, an interlayer insulating film 103, an insulating film 203, and interlayer insulating films 104 and 106 which are sequentially laminated on the insulating film 201. FIG. The interlayer insulating films 102, 103, 104, etc. may be simply referred to as insulating films 102, 103, 104 below. The insulating films 202 and 103 are used as wiring layers for forming wiring such as bit lines BL.

For example, the interlayer insulating film 102 is a P (Plasma)-TEOS (Tetraethoxysilane)-NSG (Non-doped Silicate Glass) film, and the interlayer insulating films 103 and 104 are P-TEOS films. For example, the insulating films 202 and 203 are silicon nitride (SiN) films. Note that the insulating films 202 and 203 may be silicon oxynitride. Insulating film 202 is provided to prevent oxidation of plugs 41 and 42 exposed from interlayer insulating film 102 . The insulating film 203 is provided to prevent the wirings 51 , 52 and 53 exposed from the interlayer insulating film 103 from being oxidized.

One of the source region S and the drain region D of the transistor Tr is connected to the wiring 51 for the bit line BL through the plug 41 in the insulating film 102 . The other of the source region S and the drain region D of the transistor Tr is strongly connected through the plug 42 in the insulating film 102, the wiring 52 provided in the insulating films 202 and 103, and the plug 62 provided in the insulating films 203 and 104. It is connected to the lower electrode 11 of the dielectric capacitor 10 .

A ferroelectric capacitor 10 has a lower electrode 11, a ferroelectric film 12 and an upper electrode 13 laminated on an interlayer insulating film 104, as in FIG. The ferroelectric film 12 is an example of an electrical insulator film. For example, the lower electrode 11 is a platinum (Pt) film, the ferroelectric film 12 is a lead titanium zirconate (PZT) film, and the upper electrode 13 is an iridium oxide (IrOx) film. Note that the lower electrode 11 may be an iridium (Ir) film. Also, the lower electrode 11, the ferroelectric film 12 and the upper electrode 13 may be made of materials other than those described above. Ferroelectric capacitor 10 may include films other than lower electrode 11 , ferroelectric film 12 and upper electrode 13 .

Capacitor 20 has electrode 21 provided on interlayer insulating film 104, as in FIG. The electrode 21 is connected to the wiring 53 provided on the insulating films 202 and 103 through plugs 63 provided on the insulating films 203 and 104 . The semiconductor device 100A also has an electrically insulating protective film 30 that covers the ferroelectric capacitor 10 and the electrodes 21 of the capacitor 20, as in FIG. The protective film 30 is formed over the entire chip of the semiconductor device 100A and provided along the top surface and side surfaces of the ferroelectric capacitor 10 . An electrode 22 is provided at a position facing the electrode 21 with the protective film 30 interposed therebetween. As a result, the protective film 30 sandwiched between the electrodes 21 and 22 functions as the capacitor 20 .

The semiconductor device 100</b>A has an interlayer insulating film 106 provided on the protective film 30 and the electrodes 22 . Upper electrode 13 of ferroelectric capacitor 10 is connected to plate line PL (FIG. 2) through plug 72 formed in interlayer insulating film 106 . For example, the plugs 41, 42, 62, 63, 72 and the wirings 51, 52, 53 are formed using tungsten (W).

4 to 6 show an example of a method of manufacturing the semiconductor device 100A shown in FIG. FIGS. 4 to 6 show manufacturing steps after the insulating film 203 and the interlayer insulating film 104 of FIG. 3 are formed. That is, in FIGS. 4 to 6, the transistor Tr, wiring 51 (bit line BL), 52 and 53 in FIG. 3 have already been formed. Numerical values such as film thickness shown in the following manufacturing method are examples, and other values may be used.

First, in FIG. 4A, a resist pattern (not shown) is formed on the interlayer insulating film 104 in regions other than regions where the plugs 62 and 63 are formed. Then, the insulating films 104 and 203 are selectively etched using the resist pattern as a mask to form through holes for the plugs 62 and 63 . After that, a titanium film (Ti; 10 nm) and a titanium nitride film (TiN: 20 nm) are sequentially formed on the interlayer insulating film 104 and inside the through-holes using a PVD (Physical Vapor Deposition) method. be. In the figure, description of the titanium film and the titanium nitride film is omitted.

Next, a tungsten film (W; 300 nm) is formed on the titanium nitride film (including the inside of the through-hole) using a CVD (Chemical Vapor Deposition) method. After that, the tungsten film on the interlayer insulating film 104 is removed by CMP (Chemical Mechanical Polishing) and planarized to form plugs 62 and 63 .

Next, in FIG. 4B, a metal film 11 (Pt; 50 nm), a ferroelectric film 12 (PZT; 75 to 85 nm), and a metal film 13 (IrOx; 200 nm) are sequentially formed on the surface of the interlayer insulating film 104. be done. For example, the metal films 11 and 13 are formed by PVD method. The PZT film may be subjected to a crystallization anneal to crystallize it. After that, on the metal film 13, a resist pattern (not shown) is formed in the region where the ferroelectric capacitor 10 is to be formed. A barrier metal such as titanium aluminum nitride (TiAlN) may be formed before forming the metal film 11 .

Next, the metal film 11, the ferroelectric film 12, and the metal film 13 are collectively etched using the resist pattern as a mask, so that the ferroelectric capacitor 10 having, for example, a tapered shape is formed on the interlayer insulating film 104. It is formed. The metal film 11, the ferroelectric film 12 and the metal film 13 formed by patterning are hereinafter also referred to as the lower electrode 11, the insulating film 12 and the upper electrode 13, respectively.

Next, in FIG. 5A, a metal film 21 (TiN; 150 nm) is formed on the interlayer insulating film 104 and the ferroelectric capacitor 10 using the PVD method. Next, a resist pattern RES is formed on the metal film 21 in a region where the capacitor 20 (FIG. 3) is to be formed.

Next, in FIG. 5B, using the resist pattern RES as a mask, the metal film 21 is selectively etched to form one electrode of the capacitor 20 (FIG. 3). After that, the resist pattern is removed. The patterned metal film 21 is hereinafter also referred to as an electrode 21 .

Next, in FIG. 6A, a PVD method or MOCVD (Metal Organic Chemical Vapor Deposition) method is used to cover the ferroelectric capacitor 10 and the electrodes 21 with a protective film 30 (alumina, AlOx; 35 nm or 40 nm). is formed. The protective film 30 may be titanium oxide (TiOx) or hafnium oxide (HfOx). Next, a metal film 22 (TiN; 150 nm) is formed covering the protective film 30 using PVD or MOCVD. The metal film 22 may be a film other than TiN as long as it has conductivity, but it is preferably a low-moisture film and a low-hydrogen content film.

Next, in FIG. 6B, a resist pattern RES is formed on the metal film 22 in a region where the capacitor 20 (FIG. 3) is to be formed, and the metal film 22 is selectively etched using the resist pattern RES as a mask. , the capacitor 20 is formed. In the present embodiment, the protective film 30 of the ferroelectric capacitor 10 can be used to form the insulating film of the capacitor 20, as in FIG. Adding a step of forming an insulating film can be omitted. As a result, the number of manufacturing steps of the semiconductor device 100 can be reduced.

For example, the metal film 22 is etched using a mixed gas of boron trichloride (BCl ₃ ), chlorine (Cl ₂ ) and trifluoromethane (CHF ₃ ) by a reactive ion etching device such as an inductively coupled plasma etching device. will be The flow rate of each etching gas is set to a condition that maximizes the selection ratio between the metal film 22 and the protective film 30 (for example, "metal film 22:protective film 30"="10:1"). The end point of etching is detected by detecting changes in plasma emission intensity. Note that the metal film 22 may be removed by wet etching using ammonia hydrogen peroxide mixture. Thereafter, an interlayer insulating film 106 (not shown) is formed, and a plug connected to the upper electrode 13 is formed to form the structure shown in FIG.

3 to 6, similarly to the embodiment shown in FIG. 1, the capacitor 20 of a desired size can be formed in the semiconductor device 100A while suppressing an increase in the number of manufacturing steps. For example, the capacitor 20 can be formed by using the protective film 30 of the ferroelectric capacitor 10 as an insulating film. can reduce the number of manufacturing steps. In addition, since the capacitor 20 can be formed using the protective film 30 covering the side surface of the ferroelectric capacitor 10, the lower electrode 11, the ferroelectric film 12 and the upper electrode 13 can be protected from contamination, etc., and a desired size can be formed. A capacitor 20 can be formed.

7 to 10 show an example of a method for manufacturing a semiconductor device according to another embodiment. Elements similar to those in FIGS. 1 and 3 are denoted by the same reference numerals, and detailed description thereof is omitted. In this embodiment, electrode 21 of capacitor 20 shown in FIG. 3 is formed at the same time as plug 63 . Other structures of the semiconductor device are the same as those in FIG. For example, a semiconductor device manufactured by the manufacturing method of this embodiment is a ferroelectric memory having memory cells including ferroelectric capacitors. Unless otherwise specified, the material and film thickness of each element are the same as those described with reference to FIGS.

First, in FIG. 7A, a resist pattern RES is formed with an opening in the region where the capacitor 20 is to be formed. Next, in FIG. 7B, a resist pattern RES is formed with openings in regions where the plugs 62 and 63 are to be formed. Using the resist pattern RES as a mask, through holes TH are formed in the interlayer insulating film 104 and the insulating film 203. be done. The etching for forming the through holes TH is stopped when the wirings 52 and 53 in FIG. 3 are exposed.

Next, in FIG. 8A, the resist pattern RES is removed to expose the interlayer insulating film 104 having the through holes TH and the recesses 105 forming the electrodes 21 . The through hole TH is an example of an opening. Next, in FIG. 8B, a titanium film (Ti; 10 nm), a titanium nitride film (TiN: 20 nm), and a tungsten film (W; 300 nm) are formed on the interlayer insulating film 104 in the same manner as in FIG. 4A. are formed sequentially. After that, the tungsten film on the interlayer insulating film 104 is removed by CMP and planarized to form the plugs 62 and 63, and simultaneously with the formation of the plugs 62 and 63, the electrode 21 of the capacitor 20 is formed. That is, the electrodes 21 can be formed using CVD and CMP for forming the plugs 62 and 63 . The plug 62 is an example of a first through electrode.

Next, in FIG. 9A, the ferroelectric capacitor 10 is formed on the plug 62 as in FIG. 5B. Next, in FIG. 9B, a protective film 30 and a metal film 22 are sequentially formed on the interlayer insulating film 104 and the ferroelectric capacitor 10 in the same manner as in FIG. 6A. 10, similarly to FIG. 6B, a resist pattern RES is formed in the region where the capacitor 20 (FIG. 3) is to be formed, and the metal film 22 is selectively etched using the resist pattern as a mask. , the capacitor 20 is formed. Thereafter, an interlayer insulating film 106 (not shown) is formed, and a plug connected to the upper electrode 13 is formed, thereby manufacturing a semiconductor device having a structure similar to that of FIG.

As described above, in the embodiment shown in FIGS. 7 to 10, the same effects as those in the embodiment shown in FIGS. 1 to 6 can be obtained. Furthermore, in the embodiment shown in FIGS. 7 to 10, the electrode 21 of the capacitor 20 can be formed simultaneously with the plugs 62 and 63, so the PVD process for forming only the electrode 21 of the capacitor 20 can be eliminated. As a result, compared with the embodiments shown in FIGS. 3 to 6, the manufacturing process of the semiconductor device can be simplified, and the manufacturing cost of the semiconductor device can be reduced.

11 to 15 show an example of a method for manufacturing a semiconductor device according to another embodiment. Elements similar to those in FIGS. 1 and 3 are denoted by the same reference numerals, and detailed description thereof is omitted. In this embodiment, the electrode 22 of the capacitor 20 shown in FIG. 3 is formed at the same time as the plug 72 connected to the top electrode 13 of the ferroelectric capacitor . Also, the electrode 21 of the capacitor 20 is formed at the same time as the plug 63, as described with reference to FIGS. Other structures of the semiconductor device are the same as those in FIG. For example, a semiconductor device manufactured by the manufacturing method of this embodiment is a ferroelectric memory having memory cells including ferroelectric capacitors. Unless otherwise specified, the material and film thickness of each element are the same as those described with reference to FIGS.

First, in FIG. 11, after the protective film 30 is formed covering the ferroelectric capacitor 10 and the electrode 21, an interlayer insulating film 106 (P-TEOS; P-TEOS; 1500 nm) are formed. After that, the interlayer insulating film 106 is planarized by CMP.

Next, in FIG. 12, a resist pattern RES is formed with an opening in the region where the capacitor 20 is to be formed. etched. After that, the resist pattern RES is removed.

Next, in FIG. 13, a resist pattern RES is formed that opens toward the ferroelectric capacitor 10 . Using the resist pattern RES as a mask, the interlayer insulating film 106 and the protective film 30 are etched until the upper electrode 13 of the ferroelectric capacitor 10 is exposed, thereby forming a through hole TH. After that, the resist pattern RES is removed.

14, a metal film 22 (TiN; 100 nm, for example) is formed on the interlayer insulating film 106 by PVD, and a tungsten film 70 (300 nm) is formed by CVD. For example, the metal film 22 functions as a barrier metal. Next, in FIG. 15, the metal film 22 and the tungsten film 70 on the interlayer insulating film 106 are removed by CMP and planarized to form plugs 72. Simultaneously with the formation of the plugs 72, the electrodes 23 of the capacitors 20 are formed. It is formed. The plug 72 is an example of a second through electrode. Then, a semiconductor device having a structure similar to that of FIG. 3 is manufactured.

As described above, in the embodiment shown in FIGS. 11 to 15, the same effects as those in the embodiment shown in FIGS. 1 to 10 can be obtained. Furthermore, in the embodiments shown in FIGS. 11-15, the electrodes 22 of the capacitors 20 can be formed at the same time as the plugs 72 formed in the interlayer insulating film 106. FIG. That is, the PVD process and CVD process for forming only the electrode 22 of the capacitor 20 can be eliminated. As a result, compared with the embodiments shown in FIGS. 3 to 6, the manufacturing process of the semiconductor device can be simplified, and the manufacturing cost of the semiconductor device can be reduced.

FIG. 16 shows an example of a semiconductor device according to another embodiment. Elements similar to those in FIGS. 1 and 3 are denoted by the same reference numerals, and detailed description thereof is omitted. 4 to 15, FIG. 16 shows the structure above the insulating film 203, omitting the structure from the semiconductor substrate 101 to the interlayer insulating film 103 in FIG. The structure from the semiconductor substrate 101 to the interlayer insulating film 103 is the same as in FIG.

For example, the semiconductor device 100B of this embodiment is a ferroelectric memory having memory cells including ferroelectric capacitors 10, and has a memory cell array including a plurality of memory cells. The upper electrode 13 of the ferroelectric capacitor 10 is connected to the plate line PL through the plug 72 as in FIG.

A plurality of dummy capacitors 10D having the same laminated structure as the ferroelectric capacitors 10 are formed around the memory cell array. For example, the size of the dummy capacitor 10D is the same as the size of the ferroelectric capacitor 10. FIG. Dummy capacitor 10D is an example of a dummy element. In this embodiment, two rows of dummy capacitors 10D are arranged, but the number of rows of dummy capacitors 10D may be other than two. By providing the dummy capacitor 10D around the memory cell array, for example, the influence of halation in the exposure process can be reduced. can do.

As described in FIG. 17, the materials of the lower electrode 11, the ferroelectric film 12 and the upper electrode 13 which constitute the dummy capacitor 10D are the same as those of the lower electrode 11, the ferroelectric film 12 and the upper electrode 13 of the ferroelectric capacitor 10. are the same as the materials of Also, the dummy capacitor 10D is formed at the same time as the ferroelectric capacitor 10 is formed.

A lower electrode 11 of the dummy capacitor 10D is connected to a common voltage line such as a ground line through a plug 64, for example. The semiconductor device 100B has a protective film 30 provided along the top and side surfaces of the ferroelectric capacitor 10 and the top and side surfaces of the dummy capacitor 10D. Moreover, the semiconductor device 100B has a metal film 22 provided to cover the protective film 30 in the formation region of the dummy capacitor 10D. The metal film 22 is connected to a predetermined voltage line such as a power line through a plug 73 formed in the interlayer insulating film 106 .

Capacitor 20 is formed of protective film 30 sandwiched between the side surface of lower electrode 11 of dummy capacitor 10D and metal film 22. As shown in FIG. That is, in this embodiment, the capacitor 20 can be formed using the dummy capacitor 10D arranged around the memory cell array. Semiconductor device 100B may have capacitor 20 having the structure shown in FIG. 3 in addition to capacitor 20 shown in FIG.

17 to 20 show an example of a method of manufacturing the semiconductor device 100B shown in FIG. 17 to 20 show the manufacturing process after the insulating film 203 and the interlayer insulating film 104 in FIG. 3 are formed, like FIGS. 4 to 6 described above.

First, in FIG. 17A, similarly to FIG. 5B, a metal film 11, a ferroelectric film 12 and a metal film 13 are sequentially formed. Film 12 and metal film 13 are selectively etched. As a result, the ferroelectric capacitor 10 and the dummy capacitor 10D are formed on the interlayer insulating film 104. Next, as shown in FIG.

Next, in FIG. 17B, similarly to FIG. 6A, a protective film 30 and a metal film 22 are sequentially formed to cover the ferroelectric capacitor 10 and the dummy capacitor 10D. Next, in FIG. 18, similarly to FIG. 6B, the metal film 22 is selectively etched using a resist pattern (not shown) formed in the formation region of the dummy capacitor 10D as a mask, whereby the capacitor 20 is formed. be.

Next, in FIG. 19, a resist pattern RES opening toward at least one of the dummy capacitors 10D is formed, and using the resist pattern RES as a mask, the interlayer insulating film 106 is etched until the metal film 22 is exposed. After that, the resist pattern RES is removed.

Next, in FIG. 20, a resist pattern RES opening toward the ferroelectric capacitor 10 is formed. Next, using the resist pattern RES as a mask, the interlayer insulating film 106 and the protective film 30 are etched until the upper electrode 13 of the ferroelectric capacitor 10 is exposed, thereby forming a through hole TH. After that, the resist pattern RES is removed. Thereafter, a tungsten film 70 (300 nm) is formed by CVD, and the tungsten film on the interlayer insulating film 106 is removed by CMP to form plugs 72 and 73, thus forming the structure shown in FIG. be. Before forming the tungsten film 70, a titanium nitride film may be formed on the interlayer insulating film 106 by PVD.

As described above, in the embodiment shown in FIGS. 16 to 20 as well, the same effect as in the embodiment shown in FIGS. 1 to 6 can be obtained. For example, the capacitor 20 can be formed by using the protective film 30 of the ferroelectric capacitor 10 as an insulating film. can reduce the number of manufacturing steps. Further, in the embodiments shown in FIGS. 16-20, dummy capacitor 10D can be utilized to form capacitor 20. FIG.

FIG. 21 shows an example of a semiconductor device according to another embodiment. Elements similar to those in FIGS. 1, 3 and 16 are denoted by the same reference numerals, and detailed description thereof is omitted. A semiconductor device 100C shown in FIG. 21 has a dummy capacitor 10E having a larger area than the dummy capacitor 10D shown in FIG. Dummy capacitor 10E is an example of a dummy element. Here, the area is the area of the semiconductor device 100C in plan view, not the cross-sectional area. The area of the dummy capacitor 10E may be further increased by making the length of the dummy capacitor 10E in the depth direction in FIG. 21 larger than the length of the ferroelectric capacitor 10 in the depth direction.

Since the dummy capacitor 10E has the same lamination structure as the ferroelectric capacitor 10, it can be formed using the same manufacturing process as the ferroelectric capacitor 10. FIG. The structure of the semiconductor device 100C is the same as the structure of the semiconductor device 100B shown in FIG. 16, except that the size of the dummy capacitor 10E is different. The manufacturing process of the semiconductor device 100C is the same as the manufacturing process shown in FIGS. 17 to 20, except that the number of plugs 64 to be formed and the shape of the resist pattern for forming the dummy capacitor 10E are different. .

For example, in a ferroelectric capacitor, when the area of the ferroelectric film (PZT film) exceeds a predetermined value, a leak path occurs in the ferroelectric film. Therefore, the electrodes 11 and 13 of the dummy capacitor 10E can be electrically connected by making the area of the dummy capacitor 10E equal to or larger than the area where a leak path occurs in the ferroelectric film (PZT film). That is, the ferroelectric film 12 of the dummy capacitor 10E has a leak path that electrically connects the electrodes 11 and 13 together. Thereby, not only the side surface of the electrode 11 but also the side surface and the upper surface of the electrode 13 can be used as the electrode 21 of the capacitor 20 . As a result, compared with the dummy capacitor 10D of FIG. 16, the facing area of the electrodes 21 and 22 of the capacitor 20 can be increased, and the capacitance value of the capacitor 20 can be increased.

FIG. 22 shows an example of a semiconductor device according to another embodiment. Elements similar to those in FIGS. 1 and 3 are denoted by the same reference numerals, and detailed description thereof is omitted. A semiconductor device 100D shown in FIG. 22 is, for example, a ferroelectric memory having memory cells each including a ferroelectric capacitor 10. FIG. FIG. 22 shows memory cells MC ( FIG. 2 ) including ferroelectric capacitors 10 and formation regions of capacitors 20 . FIG. 22 shows an example in which the wiring layer (insulating films 202 and 103) of the semiconductor device 100D has room to form elements other than wiring. For example, a memory cell of a ferroelectric memory is the 1T1C type shown in FIG. The cross-sectional structure of the memory cell portion including the ferroelectric capacitor 10 is the same as in FIG.

In FIG. 22, the capacitor 20 is formed using the plug 44 formed in the interlayer insulating film 102 and the wiring 54 formed in the interlayer insulating films 202 and 103 (wiring layers). The plug 44 and wiring 54 are examples of the first electrode. For example, the protective film 30 and the metal film 22 are sequentially provided around the plug 44 and the wiring 54 . For example, the protective film 30 is formed over the entire chip of the semiconductor device 100D, and the metal film 22 is formed in the recesses 108 where the plugs 44 and the wirings 54 are formed.

Plug 44 and wiring 54 are connected to each other and function as one electrode of capacitor 20 . That is, one electrode of the capacitor 20 is provided so as to protrude above the semiconductor substrate 101 . One electrode of capacitor 20 formed by plug 44 and wiring 54 corresponds to electrode 21 shown in FIG.

The plugs 44 are connected to each other through the cobalt silicide film 25, which is a metal film formed on the semiconductor substrate 101, and further through the plugs 45, the wiring 55 and the plugs 74 provided on the side of the recess 108, for example. It is connected to a voltage line such as a ground line. The metal film 22 functions as the other electrode of the capacitor 20 and is connected to a voltage line such as a power line through a plug 75 provided on the side of the recess 108 . The cobalt silicide film 25 may be formed on the source/drain regions shown in FIG.

By forming the capacitor 20 three-dimensionally not in the direction along the semiconductor substrate 101 but in the direction orthogonal to the semiconductor substrate 101, the facing area of the pair of electrodes of the capacitor 20 can be increased, and a large capacitance can be obtained with a small formation area. value can be secured. That is, the capacitance value per unit area of the semiconductor substrate 101 can be increased compared to the case where the capacitor 20 is formed planarly.

FIG. 23 shows the shape of the plug 44 and the wiring 54 of FIG. 22 viewed from above the semiconductor device 100D. The plug 44 and the wiring 54 have, for example, a meandering shape in plan view of the semiconductor device 100D. Thereby, the facing area of the pair of electrodes of the capacitor 20 can be further increased, and the capacitance value of the capacitor 20 can be further increased.

24 to 26 show an example of a method of manufacturing the semiconductor device shown in FIG. FIGS. 24 to 26 show manufacturing steps after the ferroelectric capacitor 10 is formed. The plug 44 and the wiring 54 are formed in the step of forming the plug 42 and the step of forming the wiring 52 for connecting the lower electrode 11 of the ferroelectric capacitor 10 to the semiconductor substrate 101, respectively. That is, through holes for the plugs 44 are formed in the insulating film 102, trenches for the wirings 54 are formed in the insulating films 202 and 103, and a tungsten film, which is a conductive material, is formed in the through holes and trenches by the CVD method. . Through holes and grooves are examples of holes.

Thereafter, the plug 44 and the wiring 54 are formed by removing the tungsten film on the insulating film 103 by CMP. As will be described later, plug 44 and wiring 54 function as one electrode of capacitor 20 . That is, one electrode of the capacitor 20 is formed by embedding a conductive material such as tungsten in a hole or groove formed in the interlayer insulating films 102 , 202 , 103 above the semiconductor substrate 101 , thereby forming the other through electrode 42 and the wiring 52 . formed simultaneously with one or both of A titanium film and a titanium nitride film may be sequentially formed before forming the tungsten film.

First, in FIG. 24, the ferroelectric capacitor 10 is formed on the plug 62 as in FIG. 5B. Next, in FIG. 25, a resist pattern (not shown) is formed with an opening for forming the recess 108. Using the resist pattern as a mask, the insulating films 104, 203, 103, 202, and 102 are exposed until the insulating film 201 is exposed. etched. Note that the etching may be performed in a plurality of times. After that, the resist pattern RES is removed. Then, recesses 108 exposing the plugs 44 and the wirings 54 are formed.

Next, in FIG. 26, a protective film 30 and a metal film 22 are formed to cover the top and side surfaces of the ferroelectric capacitor 10, the interlayer insulating film 104, the inner surface of the recess 108, the plugs 44 and the wiring 54 and their surroundings. are formed sequentially. That is, protective film 30 and metal film 22 are provided along the upper surface and side surface of one electrode of capacitor 20 formed by plug 44 and interconnection 54 .

Thereafter, the capacitor 20 is formed by selectively etching the metal film 22 using the resist pattern formed in the region including the recess 108 and its periphery as a mask. After that, interlayer insulating film 106 shown in FIG. 22 is formed, recess 108 is filled with interlayer insulating film 106, plugs 72, 74 and 75 are formed, and semiconductor device 100D having the structure shown in FIG. is manufactured.

One electrode of the capacitor 20 may be formed using either the plug 44 or the wiring 54 alone. Also, the layer used to form one electrode of the capacitor 20 is not limited to the layer shown in FIG. 26, and other layers may be used. For example, a plug formed in the interlayer insulating film 106 of FIG. 22 may be used to form one electrode of the capacitor 20. FIG.

As described above, in the embodiment shown in FIGS. 22 to 26 as well, the same effect as in the embodiment shown in FIGS. 1 to 6 can be obtained. For example, the capacitor 20 can be formed by using the protective film 30 of the ferroelectric capacitor 10 as an insulating film. can reduce the number of manufacturing steps.

Also, one electrode (44, 54) of the capacitor 20 can be formed simultaneously with the plugs 42, 45 and the wirings 52, 55 formed in the interlayer insulating films 102, 202, 103. FIG. That is, the CVD process for forming only one electrode (44, 54) of the capacitor 20 can be eliminated.

Furthermore, in the embodiments shown in FIGS. 22 to 26, the capacitor 20 is three-dimensionally formed in a direction orthogonal to the semiconductor substrate 101 and is formed in a meandering shape in a plan view, thereby forming a pair of capacitors 20. The facing area of the electrodes can be increased. As a result, the capacitor 20 having a large capacitance value can be formed in a small formation area.

27 and 28 show an example of a method for manufacturing a semiconductor device according to another embodiment. Elements similar to those in FIGS. 1, 3 and 22 are denoted by the same reference numerals, and detailed description thereof is omitted. In this embodiment, before forming the recess 108 shown in FIG. 22, a protective film 30a is formed covering the ferroelectric capacitor 10 and the interlayer insulating film 104 as shown in FIG.

Next, in FIG. 28, similarly to FIG. 25, a resist pattern (not shown) having openings for forming recesses 108 is formed. Then, using the resist pattern as a mask, etching is performed until the insulating film 201 is exposed, thereby forming recesses 108 exposing the plugs 44 and the wirings 54 . In this embodiment, since the ferroelectric capacitor 10 is covered with the protective film 30a during formation of the resist pattern and etching up to the insulating film 201, the ferroelectric film 12 and the like of the ferroelectric capacitor 10 are not recessed. Contamination in the process of forming 108 can be suppressed.

Next, a protective film 30b and a metal film 22 are sequentially formed to cover the ferroelectric capacitor 10, the interlayer insulating film 104, the inner surface of the recess 108, and the periphery of the plug 44 and the wiring 54. Next, as shown in FIG. That is, in this embodiment, the protective films 30a and 30b are formed before and after the recess 108 is formed. The subsequent step of patterning the metal film 22 is the same as the description of FIG. Then, a semiconductor device 100D similar to that of FIG. 22 is manufactured.

As described above, in the embodiment shown in FIGS. 27 and 28 as well, the same effects as in the embodiment shown in FIGS. 1 to 6 and the embodiment shown in FIGS. 22 to 26 can be obtained. Furthermore, in the embodiment shown in FIGS. 27 and 28, by covering the ferroelectric capacitor 10 with the protective film 30a before forming the recess 108, contamination of the ferroelectric capacitor 10 during the formation of the recess 108 is suppressed. can do. As a result, deterioration of the characteristics of the ferroelectric capacitor 10 can be suppressed.

The following additional remarks are disclosed with respect to the embodiment shown in FIGS. 1 to 27 above.
(Appendix 1)
a first electrode provided above a semiconductor substrate;
a first element provided above the semiconductor substrate;
an electrically insulating protective film provided to cover the first electrode and the first element and protect the first element;
and a second electrode provided on the opposite side of the first electrode with the protective film interposed therebetween.
(Appendix 2)
The semiconductor device according to Supplementary Note 1, wherein the first element has a lower electrode, an insulating film, and an upper electrode which are stacked in order from the semiconductor substrate side.
(Appendix 3)
3. The semiconductor device according to appendix 1 or appendix 2, wherein the protective film is provided along an upper surface and a side surface of the first element.
(Appendix 4)
The semiconductor device according to appendix 2, wherein the first electrode has the same laminated structure as the first element.
(Appendix 5)
The area of the first electrode is larger than the area of the first element,
The insulating film included in the first electrode has a leak path that electrically connects a lower electrode included in the first electrode and an upper electrode included in the first electrode. 4. The semiconductor device according to Supplementary Note 4.
(Appendix 6)
The semiconductor device further has through electrodes and wiring provided in an insulating film formed above the semiconductor substrate,
3. The semiconductor device according to any one of appendices 1 to 3, wherein the first electrode has the same structure as one or both of the through electrode and the wiring.
(Appendix 7)
the first element and the first electrode are provided on an insulating film formed on the semiconductor substrate;
Supplements 1 to 3, wherein the material of the first electrode is the same as the conductive material arranged in the opening of the insulating film for connecting the first element to the semiconductor substrate. The semiconductor device according to any one of .
(Appendix 8)
The material of the second electrode is the same as the conductive material arranged in the opening of the insulating film provided on the first element in order to connect to the first element. The semiconductor device according to any one of additional notes 1, 2, 3, and 7.
(Appendix 9)
9. Any one of appendices 1 to 8, wherein the first element is a ferroelectric element, and the first electrode, the protective film, and the second electrode constitute a capacitive element. 2. The semiconductor device according to item 1.
(Appendix 10)
forming a first electrode over a semiconductor substrate;
forming a first device over the semiconductor substrate;
forming an electrically insulating protective film covering the first electrode and the first element;
forming a second electrode on a side opposite to the first electrode with the protective film interposed therebetween.
(Appendix 11)
11. The method of manufacturing a semiconductor device according to appendix 10, wherein the step of forming the first element includes a step of stacking a lower electrode, an insulating film, and an upper electrode in order from the semiconductor substrate side.
(Appendix 12)
12. The method of manufacturing a semiconductor device according to appendix 10 or 11, wherein the protective film is formed along the upper surface and the side surface of the first element.
(Appendix 13)
The first electrode is formed by patterning a first conductive film, a first insulating film, and a second conductive film which are formed in order from the semiconductor substrate side, thereby forming the lower electrode, the insulating film, and the conductive film. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the upper electrode is formed at the same time and has the same stacked structure as the first element.
(Appendix 14)
The first electrode is formed by embedding a conductor in a hole or groove formed in an interlayer insulating film above the semiconductor substrate, thereby forming one or both of the through electrode and the wiring at the same time. 13. The method of manufacturing a semiconductor device according to any one of 10 to 12.
(Appendix 15)
15. The method of manufacturing a semiconductor device according to claim 14, wherein the protective film is formed before and after removing the interlayer insulating film around the first electrode.
(Appendix 16)
Before forming the first element, in the step of forming a first through electrode connected to the first element in an insulating film on the semiconductor substrate, using the same material as the first through electrode 11. The method of manufacturing a semiconductor device according to claim 10, further comprising forming the first electrode.
(Appendix 17)
Forming the second electrode using the same material as the second through electrode in the step of forming the second through electrode connected to the first element in the insulating film on the first element. The method of manufacturing a semiconductor device according to appendix 10 or appendix 16, characterized by:

From the detailed description above, the features and advantages of the embodiments will become apparent. It is intended that the claims cover the features and advantages of such embodiments without departing from their spirit and scope. In addition, any improvements and modifications will readily occur to those skilled in the art. Accordingly, the scope of inventive embodiments is not intended to be limited to that described above, but can be relied upon by suitable modifications and equivalents within the scope disclosed in the embodiments.

10 ferroelectric capacitors 10D, 10E dummy capacitor 11 lower electrode 12 ferroelectric film 13 upper electrode 20 capacitors 21, 22 electrode (metal film)
25 cobalt silicide films 30, 30a, 30b protective films 41, 42, 44, 45 plugs 51, 52, 53, 54, 55 wirings 62, 63, 64 plugs 70 tungsten films 72, 73, 74, 75 plugs 100, 100A, 100B, 100C, 100D semiconductor device 101 semiconductor substrates 102, 104, 106 interlayer insulating films 105, 108 recesses 201, 202, 203 insulating film RES resist pattern TH through hole

Claims (5)

a first electrode provided above a semiconductor substrate;
a first element provided above the semiconductor substrate and having a lower electrode, an insulating film, and an upper electrode stacked in order from the semiconductor substrate side;
an electrically insulating protective film provided to cover the first electrode and the first element and protect the first element;
a second electrode provided on the side opposite to the first electrode with the protective film interposed therebetween;
The first electrode is formed by patterning a first conductive film, a first insulating film, and a second conductive film which are formed in order from the semiconductor substrate side, thereby forming the lower electrode, the insulating film, and the conductive film. A semiconductor device characterized by being formed simultaneously with an upper electrode and having the same laminated structure as that of the first element. 2. The semiconductor device according to claim 1, wherein said protective film is provided along an upper surface and side surfaces of said first element. 3. The method according to claim 1, wherein said first element is a ferroelectric element, and said first electrode, said protective film, and said second electrode constitute a capacitive element. The semiconductor device described. forming a first electrode over a semiconductor substrate;
a step of laminating a lower electrode, an insulating film and an upper electrode in this order from the semiconductor substrate side above the semiconductor substrate to form a first element;
forming an electrically insulating protective film covering the first electrode and the first element;
forming a second electrode on the side opposite to the first electrode with the protective film interposed therebetween;
The first electrode is formed by patterning a first conductive film, a first insulating film, and a second conductive film which are formed in order from the semiconductor substrate side, thereby forming the lower electrode, the insulating film, and the conductive film. A method of manufacturing a semiconductor device, characterized in that it is formed simultaneously with an upper electrode and has the same lamination structure as that of the first element. 5. The method of manufacturing a semiconductor device according to claim 4 , wherein said protective film is formed along the upper surface and side surfaces of said first element.

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