JPH04340272A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce a short channel effect in a MOS transistor constituting a memory cell for a semiconductor memory device and to lower the junction capacity between a semiconductor substrate and a source region and a drain region. CONSTITUTION:The part of an active region 2 situated at the lower side of gate electrodes 9 is used as a channel region. Parts in which impurity-implanted regions 20 to 22 are overlapped with source-side active regions 14, 16 are used as source regions. On the other hand, a part in which an impurity-implanted region 11 is overlapped with a drain-side active region 15 is used as a drain region. A MOS transistor is constituted of the channel region, the source regions and the drain region.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-density, large-capacity semiconductor memory device having a MOS type (metal-oxide-semiconductor structure) transistor.

0002

2. Description of the Related Art FIG. 12 shows a memory cell portion of a conventional semiconductor memory device having a MOS type transistor. In this semiconductor memory device, a rectangular active region 72 is formed in the surface region of a semiconductor substrate 70 by a LOCOS isolation method (selective oxidation method) or a trench isolation method. Gate electrodes 73 and 74 are made of polysilicon and intersect with active region 72. Portions of active region 72 covered by gate electrodes 73 and 74 function as channel regions 82 and 81, respectively. A drain region 76 is formed in a portion of the active region 72 sandwiched between gate electrodes 73 and 74. Source regions 75 and 77 are formed in other parts of active region 72 and are arranged adjacent to gate electrodes 73 and 74, respectively.

One MOS transistor is composed of a gate electrode 73, a channel region 82, a source region 75, and a drain region 76.
4, the channel region 81, the source region 77, and the drain region 76 constitute another MOS transistor. These two MOS type transistors share a drain region 76.

Drain region 76 is a bit contact 79
It is connected to a bit line (not shown) via. Source regions 75 and 77 are connected to one electrode of a charge storage capacitor (not shown) via storage contacts 78 and 80, respectively.

One memory cell of the semiconductor memory device is constituted by the two MOS transistors, the bit contact 79, the storage contacts 78 and 80, and the charge storage capacitor. Gate electrodes 73 and 74 function as word lines through which address signals are supplied to memory cells.

The above memory cell is, for example, an n-type M
In the case of having an OS type transistor, the gate electrode 73
Or if a high potential bias is applied to 74, two MO
One of the S-type transistors is turned on. At this time,
When the memory cell is in a read state, the signal charge stored in the capacitor is transferred to the storage contact 78 or 80, the source region 75 or 77, and the channel region 82 or 81 of the MOS transistor in the on state.
and then transferred to the drain region 76. This signal charge is then sent to a sense amplifier (not shown) via bit contact 79 and the bit line. Conversely, when the memory cell is in the write state, signal charges are transferred from the drain region 76 to the capacitor in the opposite direction to the above-described read state. The transferred signal charges are accumulated in the capacitor.

[0007] When manufacturing a MOS transistor for a memory cell as described above, a source region and a drain region are formed by implanting impurity ions into the active region in order to obtain ohmic contact with the electrode material. . Impurity ions are usually implanted into a region (impurity implantation region 71 shown in FIG. 12) that covers the entire surface of a MOS transistor, for example. Since the gate electrodes 73 and 74 function as a mask when implanting impurity ions, the source region and drain region can be formed in a self-aligned manner by implanting the impurity ions. In this case, part of the drain side active region becomes the drain region 76, and part of the source side active region becomes the source regions 75 and 77.

A conventional DRA well known as a semiconductor memory device
Most dynamic random access memories (M) adopt a folded bit line method in consideration of resistance to noise. Therefore, when the active region is rectangular as shown in FIG. 12, each memory cell is arranged as shown in FIG. As shown in this figure, the active regions adjacent to active region 91 are active regions 89 and 9.
0, 92, and 93. The active regions are arranged in rows parallel to the gate electrodes 96 functioning as word lines. The active regions in one row are offset from the active regions in adjacent rows by one half of the active region pitch within each row. For example, as shown in FIG. 13, active regions 88 and 91 are separated from active regions 89 and 92 and active regions 90 and 93 by 1/2 pitch, that is, the distance between active regions 88 and 91. It is off by 1/2.

[0009]

[Problem to be Solved by the Invention] By the way, the element isolation region that electrically insulates between active regions is 4 megabits (4 megabits)
When manufacturing a DRAM (M) or a relatively low-integration semiconductor memory device, a LOCOS isolation method is used to selectively oxidize a silicon substrate. On the other hand, the 16M DR has a fine structure and is highly integrated.
When manufacturing AM or 64M DRAM, it is necessary to form fine element isolation regions with widths of 0.6 to 0.7 μm and 0.4 to 0.5 μm, respectively. However, LOCOS technology is required for fine element isolation regions with a width of 0.4 to 0.7 μm.
It cannot be formed using separation methods. Therefore, when manufacturing a highly integrated semiconductor memory device that requires a fine element isolation region, the element isolation region must be formed using a trench isolation method. In the trench isolation method, for example, a trench is formed in a silicon substrate and the trench is filled with an insulating material to form an element isolation region.

However, the conventional semiconductor memory device described above has the following problems.

1) As shown in FIG. 12, since the impurity ion implantation region 71 covers the entire surface of the MOS transistor, the impurity ions implanted in the impurity implantation region 71 may damage the fine structure of the memory cell. During the heat treatment process for forming, from all interfaces between source regions 77 and 75 and drain region 76, and between channel region 81 and source region 77 and drain region 76,
Heat is also diffused into channel regions 81 and 82 from all boundary portions between channel region 82 and source region 75 and drain region 76 . For this reason, in particular, DRA
In a MOS transistor, which is the smallest transistor used in an M memory cell, the effects of short channel effects such as a decrease in threshold voltage and a decrease in punch-through breakdown voltage cannot be ignored, resulting in an increase in leakage current. the result,
It becomes difficult for the capacitor to hold the signal charge necessary for the storage operation of the memory cell, and the memory cell does not operate normally.

2) As shown in FIG. 12, since the impurity ion implantation region 71 covers the entire surface of the MOS transistor, the source regions 75 and 77 and the drain region 76
The total area is relatively large. Therefore, the junction capacitance generated between the silicon substrate 70 and the source regions 77 and 75 and the drain region 76 increases, and in particular, the parasitic capacitance of the bit line increases, causing an increase in current consumption and a decrease in operating speed.

3) As shown in FIG. 13, in the folded bit line type semiconductor memory device, the distance between active region 91 and active regions 89, 90, 92, and 93 is the same as that between active region 91 and active region 88. It is less than 1/2 of the distance between Therefore, the width of the isolation region to be formed between the active regions becomes non-uniform. However, it is extremely difficult to form element isolation regions with non-uniform widths using the trench isolation method. Therefore, highly integrated 16M DRAM and 64M DRAM
When manufacturing RAM, there are two isolation methods: the LOCOS isolation method, which can form element isolation regions with non-uniform widths, and the LOCOS isolation method, which forms fine element isolation regions with a width of 0.4 to 0.7 μm. Therefore, the process for forming the element isolation region becomes complicated.

The present invention solves the above-mentioned conventional problems, and its purpose is to reduce the short channel effect and reduce the junction capacitance between the semiconductor substrate and the source and drain regions. , memory cell malfunctions are reduced, memory operation reliability is improved, and MOS
An object of the present invention is to provide a semiconductor memory device in which an increase in current consumption and a decrease in driving ability of a type transistor are prevented. Another object of the present invention is to provide a semiconductor memory device having a structure in which active regions can be easily separated using a single element isolation technique.

[0015]

[Means for Solving the Problems] A semiconductor memory device of the present invention includes a plurality of memory cells, each of which has an active region having a MOS type transistor formed in a surface region of a semiconductor substrate, and an active region having a MOS transistor formed in a surface region of a semiconductor substrate. The above object is achieved by having a gate electrode of a MOS type transistor and first and second impurity implanted regions defining a source region and a drain region of this MOS type transistor.

In the semiconductor memory device of the present invention, the gate electrode is formed on the semiconductor substrate so as to divide the active region into a source side active region having a storage contact and a drain side active region having a bit contact. has been done. A portion of the active region located below the gate electrode functions as a channel region of the MOS transistor. Further, the first impurity implantation region is formed in a portion of the source side active region so as to overlap at least a portion of the storage contact and the gate electrode. A portion of the source side active region that overlaps with the first impurity implantation region functions as a source region of a MOS type transistor. Furthermore, the second impurity implantation region is formed in a portion of the drain side active region so as to overlap at least a portion of the bit contact and the gate electrode. A portion of the drain side active region that overlaps with the second impurity implanted region functions as a drain region of a MOS type transistor.

The active regions of each memory cell are preferably arranged in columns parallel to the gate electrode. In this case, the active regions of two adjacent columns are arranged such that all distances between adjacent active regions are approximately equal. Examples of the planar shape of the active region include a T-shape, a Y-shape, a V-shape, and an oblique shape.

[0018]

The semiconductor memory device of the present invention includes a plurality of, for example, T-shaped or Y-shaped active regions having MOS transistors formed on the surface region of a semiconductor substrate. The T-shaped or Y-shaped active regions are arranged in a plurality of rows with alternating phases so that the spacing between the active regions is approximately the same. Therefore, in this case, when forming the element isolation region, it is not necessary to use the LOCOS isolation method that can form an element isolation region with non-uniform width, but only the trench isolation method that can form a fine element isolation region. You can use Therefore, when manufacturing the semiconductor memory device of the present invention, element isolation regions that electrically insulate each active region can be easily formed by a simple process.

Furthermore, in the semiconductor memory device of the present invention, the impurity implantation region for forming the source region is formed so as to overlap with a part of the source side active region and the contact region provided therein, Similarly, an impurity implantation region for forming a drain region is formed so as to overlap with a portion of the drain side active region and the contact region provided therein. By implanting impurity ions into these impurity implanted regions, the overlapping portion of the source side active region and the impurity implanted region becomes the source region, and the overlapping portion of the drain side active region and the impurity implanted region becomes the drain region. Therefore, during heat treatment performed after impurity ion implantation, impurity ions are transferred from the source and drain regions to the channel region through only part of the boundary between the channel region and the source-side active region and drain-side active region. It will spread. Therefore, the effective channel length of the channel region does not become significantly shortened, and the short channel effect can be significantly reduced.

As described above, in the semiconductor memory device of the present invention, since the impurity implantation region overlaps only a portion of the source side active region and the drain side active region, the area of the obtained source region and drain region is is smaller than in a conventional semiconductor memory device in which the impurity implantation region overlaps the entire memory cell. For this purpose, it is possible to reduce the junction capacitance between the semiconductor substrate and the source region and the drain region, thereby reducing the parasitic capacitance of the semiconductor memory device, so that the driving ability of the MOS transistor is not impaired. Can be done.

According to the invention, the active region may have other shapes, such as a V-shape or an oblique shape. Even in that case, the impurity implantation region is a part of the source-side active region and a part of the contact region provided therein, and a part of the drain-side active region and at least part of the contact region provided therein. It is placed so that it overlaps only the section. Therefore, the above-mentioned effects such as reduction in short channel effect and reduction in junction capacitance can be obtained.

[0022]

[Embodiments] Examples of the present invention will be described below.

(Embodiment 1) FIG. 1 is a partial plan view of an embodiment of a semiconductor memory device of the present invention. In the semiconductor memory device of this embodiment, a plurality of T-shaped active regions 2, 3, 4, 5, 6, 7 and 8 are formed on the surface area of the semiconductor substrate 1. A plurality of gate electrodes 9, 9... are formed. active regions 2, 3, 4, 5,
Arrangements 6, 7 and 8 are based on a folded bit line scheme. Portions of the T-shaped active regions 2, 3, 4, 5, 6, 7, and 8 extending convexly downward in the figure are sandwiched between two gate electrodes 9, 9.

Active regions 2, 3, 4, 5, 6, 7 and 8
are arranged in a row parallel to the gate electrodes 9, 9, . The rows of active regions 2, 5, and 8, the rows of active regions 3 and 6, and the rows of active regions 4 and 7 are arranged so that they are alternately out of phase, and the intervals between each active region are all approximately It is made to be uniform. Therefore, even when semiconductor memory devices become highly integrated and the spacing between active regions narrows, the complicated process of using both the LOCOS isolation method and the trench isolation method is unnecessary to form element isolation regions. Therefore, the active regions can be easily separated using only the trench isolation method, which is particularly effective when the distance between each active region is narrow.

FIG. 2 shows the active region 2 of the semiconductor memory device of FIG.
FIG. Two MOSs are formed by an active region 2 and two gate electrodes 9 and 9 that intersect this active region 2.
It constitutes a type transistor. The portion of active region 2 covered by gate electrodes 9 and 9 is a channel region. Reference numbers 14 and 16 indicate source side active regions, and 15 indicates a drain side active region. Storage contacts 17 and 19, which are contact regions, are provided on source side active regions 14 and 16, respectively, and similarly, a bit contact 18, which is a contact region, is provided on drain side active region 15.

Impurity implantation regions 20 and 22 for source-side active regions 14 and 16 cover parts of source-side active regions 14 and 16, and also cover parts of storage contacts 17 and 19, respectively. The impurity implantation region 11 for the drain side active region 15 covers a part of the drain side active region 15 and also covers a part of the bit contact 18 . By implanting impurity ions into these impurity implantation regions 20, 22, and 11, a source region and a drain region are formed. In this case, the overlapping portions of source side active regions 14 and 16 and impurity implanted regions 20 and 22 become source regions, respectively, and the overlapping portions of drain side active region 15 and impurity implanted region 11 become drain regions.

FIG. 3 is a cross-sectional view of the semiconductor memory device taken along line AA' in FIG. In FIG. 3, two other gate electrodes 9 and 9, respectively adjacent to the two gate electrodes 9 and 9 shown in FIG. 2, are also shown. A gate insulating film 36 is formed between the two gate electrodes 9 and 9 and the semiconductor substrate 1 shown in FIG. Two new gate electrodes 9 and 9 shown in FIG. 3 are formed directly on the element isolation region 29. The interlayer insulating film 37 is formed to cover other parts of the substrate 1 and all the gate electrodes 9 except for a part of the active region 2 .

The semiconductor memory device further includes a capacitor 38.
is provided. Each capacitor 38 includes a common upper plate electrode 24, a lower plate electrode 26, and a capacitor dielectric film 25 formed therebetween. The lower plate electrode 26 is formed on the interlayer insulating film 37 and the portion of the active region 22 that is not covered by the interlayer insulating film 37. Portions of active region 2 in contact with lower plate electrode 26 become storage contacts 17 and 19. Impurity implantation regions 20 and 22 for forming source regions are formed in the surface region of semiconductor substrate 1. As shown, storage contacts 17 and 19 are arranged so as to partially overlap impurity implantation regions 20 and 22, respectively.

In the impurity implanted regions 20 and 22, N
Mold diffusion region 28 forms storage contacts 17 and 19
They are each formed by impurity diffusion from N
The mold diffusion region 28 may be separated from the isolation region 29, like the region 28 on the left side of the figure. On the other hand, since the diameter of the storage contact 17 is larger than the width of the gate electrode, the N-type diffusion region 28 on the right side of the figure reaches the isolation region 29.

FIGS. 4, 5, and 6 are cross-sectional views of the semiconductor memory device taken along lines BB', CC', and DD' in FIG. 2, respectively. In FIG. 4, impurity implantation regions 20, 2
2 and 11 are not seen, but an impurity implantation region 11 for forming a drain region appears in FIGS. 5 and 6. Impurity implantation region 11 is provided in the surface region of semiconductor substrate 1 .

In FIG. 6, all the gate electrodes 9, 9, . . . are located on the element isolation region 29. A portion of the active region 2 that is not covered with the interlayer insulating film 37 is in contact with the bit line 27 and functions as a bit contact 18. In the impurity implantation region 11, an N type diffusion region 28 is formed by impurity diffusion from the bit contact 18.

In the semiconductor memory device configured as described above, the impurity implanted regions 20 and 22 are located in the source side active region 1.
4 and 16, the source region is formed only in a portion of source side active regions 14 and 16. Further, only part of the boundary between the source side active regions 14 and 16 and the channel region adjacent thereto becomes the boundary between the corresponding source region and channel region. Similarly, the drain region is formed only in a part of the drain-side active region 15, and only a part of the boundary between the drain-side active region 15 and the adjacent channel region is formed in the boundary between the drain region and the channel region. Become.

In the semiconductor memory device of this embodiment, each MOS
Although the impurity implantation region 20 or 22 of the MOS transistor is formed in the source side active region 14 or 16 of the MOS transistor itself, the structure of the present invention is not limited to this. Two adjacent source-side active regions of different MOS transistors may share one impurity implantation region. Further, two such source-side active regions and a drain-side active region located between them may share one impurity implantation region.

(Embodiment 2) FIG. 7 is a partial plan view of another embodiment of the semiconductor memory device of the present invention. The semiconductor memory device of this embodiment differs from the semiconductor memory device of embodiment 1 only in that it has a Y-shaped active region instead of a T-shaped active region. Therefore, the same constituent parts as those of the semiconductor memory device of the first embodiment are given the same numbers as the constituent parts shown in FIGS. 1 to 6, and will be described below.

In the semiconductor memory device of this embodiment, a plurality of Y-shaped active regions 32 are formed in the surface portion of the semiconductor substrate 1.
, 33, 34, and 35 are formed, and a plurality of gate electrodes 9, 9, . . . are formed on the semiconductor substrate 1. The arrangement of active regions 32, 33, 34 and 35 is based on a folded bit line scheme. Each Y-shaped active region 32,3
Portions 3, 34, and 35 extending downward in the figure are sandwiched between the two gate electrodes 9, 9.

Similar to the first embodiment, the active regions 32, 33,
34 and 35 are arranged in a row parallel to the gate electrodes 9, 9, . The rows of active regions 32 and 35, the rows with active regions 33 and the rows with active regions 34 are arranged so as to be alternately out of phase, so that the intervals between the active regions are all approximately uniform. ing. Therefore, even when semiconductor memory devices become highly integrated and the spacing between active regions narrows, the active regions can be easily isolated using only the trench isolation method.

In the semiconductor memory device of this embodiment, each MOS transistor has an independent impurity implantation region as shown in FIG. 2, but the present invention is not limited to this. As shown in FIG. 10, which will be described later, a plurality of adjacent MOS transistors may share one implantation region.

(Embodiment 3) FIG. 8 is an enlarged plan view of an active region in still another embodiment of the semiconductor memory device of the present invention. In the semiconductor memory device of this embodiment, an active region 51 is formed in the surface region of a semiconductor substrate 50, and a gate electrode 52 is formed on the semiconductor substrate 50. active area 5
1 has a source side active region 53 and a drain side active region 54. A contact region 57 is provided above the drain side active region 54 in the figure, and the source side active region 5
A contact region 56 is provided at the bottom of the figure in FIG. A portion of the active region 51 covered with the gate electrode 52 functions as a channel region 55. The gate electrode 52 and the active region 51 constitute a MOS transistor.

An impurity implantation region 58 for forming a source region covers a part of the source side active region 53 and a part of the contact region 56, and an impurity implantation region 59 for forming a drain region covers a part of the source side active region 53 and a part of the contact region 56. Part of the active region 54 and part of the contact region 57 are covered. Therefore, the source region is formed only in a part of the source-side active region 53, and only a part of the boundary between the source-side active region 53 and the adjacent channel region 55 is formed in the boundary between the source region and the channel region 55. becomes. Similarly, the drain region is formed only in a part of the drain side active region 54,
Only a part of the boundary between the drain side active region 54 and the adjacent channel region 55 becomes the boundary between the drain region and the channel region 55.

In the semiconductor memory device of this embodiment shown in FIG. 8, part of the impurity implantation regions 58 and 59 also extends to the element isolation region, but the present invention is not limited to this. As seen in the modification shown in FIG. 9, the entire impurity implantation regions 68 and 69 may be placed inside the active region 61. Except for the difference in the location of the impurity implantation region, the modification of FIG. 9 has a structure similar to the embodiment shown in FIG. 8.

(Embodiment 4) FIG. 10 is a partial plan view of still another embodiment of the semiconductor memory device of the present invention. In the semiconductor memory device of this embodiment, a plurality of V-shaped active regions 41 are formed in the surface region of a semiconductor substrate 40, and a plurality of gate electrodes 42, 42, . . . are formed on the semiconductor substrate 40. Each active region 41 has two source-side active regions 4
3 and one drain side active region 44. The source side active region 43 and the drain side active region 44 include contact regions 46 and 47, respectively. A portion of the active region 41 covered by the gate electrode 42 functions as a channel region. The active region 41 and the gate electrode 42 intersecting the active region 41 constitute a MOS transistor.

The impurity implantation region 49 covers a portion of each source side active region 43, a portion of each drain side active region 44, and a portion of each contact region 46 and 47. Therefore, the source region is formed only in a part of the source-side active region 43, and only a part of the boundary between the source-side active region 43 and the adjacent channel region becomes the boundary between the source region and the channel region. . Similarly, the drain region is formed only in a part of the drain-side active region 44, and only a part of the boundary between the drain-side active region 44 and the adjacent channel region is formed in the boundary between the drain region and the channel region. Become.

(Embodiment 5) FIG. 11 is a partial plan view of still another embodiment of the semiconductor memory device of the present invention. In the semiconductor memory device of this embodiment, a plurality of oblique active regions 101 are formed in the surface region of a semiconductor substrate 100, and a plurality of gate electrodes 102, 102, . . . are formed on the semiconductor substrate 100.
is formed. Each oblique active region 101 crosses the gate electrode 102 diagonally, and has two source-side active regions 103 and one drain-side active region 104. The source side active region 103 and the drain side active region 104 are connected to contact regions 106 and 107.
Each is equipped with Gate electrode 1 of active region 101
The portion covered by 02 functions as a channel region. An active region 101 and a gate electrode 102 intersecting the active region 101 constitute a MOS transistor. BL indicates an area where bit lines are wired.

The impurity implanted region 109 covers a portion of each source-side active region 103 , a portion of each drain-side active region 104 , a portion of each contact region 106 , and the entire surface of each contact region 107 . Therefore, the source region is formed only in a part of the source-side active region 103, and only a part of the boundary between the source-side active region 103 and the adjacent channel region becomes the boundary between the source region and the channel region. . Similarly, the drain region is formed only in a part of the drain-side active region 104, and only a part of the boundary between the drain-side active region 104 and the adjacent channel region is formed in the boundary between the drain region and the channel region. Become.

As is clear from the above explanation, in the semiconductor memory devices of all the above embodiments, only a part of the boundary between the source side active region and the adjacent channel region is connected to the source region and the channel region. Only a part of the boundary between the drain side active region and the adjacent channel region is the boundary between the drain region and the channel region. Therefore, during the heat treatment process performed after impurity ion implantation, impurity ions are transferred from the source and drain regions to the channel region through only part of the boundary between the source and drain active regions and the channel region. Due to thermal diffusion, the effective channel length of the channel region does not decrease significantly, and even fine design rules are less susceptible to short channel effects. Therefore, malfunctions of the semiconductor memory device can be reduced.

Furthermore, in the semiconductor memory device of the present invention, the impurity implantation region for forming the source region overlaps only a part of the source side active region, and the impurity implantation region for forming the drain region overlaps only a part of the source side active region. Since the impurity implantation region overlaps only a part of the active region, the area of the obtained source region and drain region is smaller than that in the case where the impurity implantation region covers the entire active region. Therefore, the junction capacitance generated between the semiconductor substrate and the source and drain regions is reduced, and thereby the parasitic capacitance of the semiconductor memory device can also be reduced.

Therefore, according to the present invention, by limiting the impurity implantation region as described above, the two effects of reducing the short channel effect and reducing the junction capacitance can be obtained. These two effects become more noticeable when only N- (low concentration) ions are implanted and N+ (high concentration) ions are not implanted in the LDD (Lightly Doped Drain) process.

[0048]

According to the present invention, a semiconductor memory device can be obtained in which the short channel effect is reduced and the junction capacitance between the semiconductor substrate and the source and drain regions is reduced. In such a semiconductor memory device, malfunctions of memory cells are reduced, reliability of storage operations is improved, and an increase in current consumption and a decrease in driving ability of MOS transistors are prevented. Furthermore, by adopting an arrangement in which the distances between the active regions are approximately equal, the active regions can be easily separated using a single element isolation technique.

[Brief explanation of drawings]

FIG. 1 is a partial plan view of a semiconductor memory device of the present invention.

FIG. 2 is an enlarged plan view showing an active region of the semiconductor memory device in FIG. 1;

3 is a cross-sectional view of the semiconductor memory device taken along line AA' in FIG. 2;

4 is a cross-sectional view of the semiconductor memory device taken along line BB' in FIG. 2;

5 is a cross-sectional view of the semiconductor memory device taken along line CC' in FIG. 2;

6 is a cross-sectional view of the semiconductor memory device taken along line DD' in FIG. 2;

FIG. 7 is a partial plan view of another semiconductor memory device of the present invention.

FIG. 8 is an enlarged plan view showing an active region of still another semiconductor memory device of the present invention.

9 is an enlarged plan view showing an active region of a modification of the semiconductor memory device of FIG. 8; FIG.

FIG. 10 is a partial plan view of still another semiconductor memory device of the present invention.

FIG. 11 is a partial plan view of still another semiconductor memory device of the present invention.

FIG. 12 is an enlarged plan view showing a memory cell portion of a conventional semiconductor memory device.

13 is a partial plan view of the conventional semiconductor memory device shown in FIG. 12. FIG.

[Explanation of symbols]

1, 40, 50, 60, 70, 100 semiconductor substrate 2
,3,4,5,6,7,8,32,33,34,35,
41, 51, 61, 72, 88, 89, 90, 91, 9
2, 93, 94, 95, 101 Active region 9, 42, 52, 62, 73, 74, 96, 102
Gate electrodes 11, 20, 22, 49, 58, 59, 68
, 69, 71, 109 impurity implantation region

Claims (1)

[Claims] 1. A semiconductor memory device comprising a plurality of memory cells, each of the memory cells comprising: an active region having a MOS transistor formed in a surface region of a semiconductor substrate; The active region is formed on the substrate so as to be divided into a source-side active region having a storage contact and a drain-side active region having a bit contact, and a portion of the active region located below is a channel of the MOS transistor. a gate electrode of the MOS type transistor functioning as a region; a first impurity implanted region such that a portion of the region functions as a source region of the MOS transistor; a portion of the drain side active region so as to overlap with at least a portion of the bit contact and the gate electrode; a second impurity implantation region formed so that a portion of the drain side active region overlapping with the second impurity implantation region functions as a drain region of the MOS transistor.