JP2010147300A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for reducing a cell area while conforming to design rules. <P>SOLUTION: In an FeRAM 1, an N-type drain region 6 and a source region 7 are formed with an interval each other. Word lines WL1, WL2, ... oppose a region between the drain region 6 and the source region 7. A ferroelectric capacitor 12 is formed on the upper part of the drain region 6. The drain region 6 is connected to a lower electrode 13 of the ferroelectric capacitor 12 via a capacitive contact plug 18. The capacitive contact plug 18 is provided at a position deviated oppositely to the word lines WL1, WL2, ... side with respect to the center of the lower electrode 13 in plan view. With this configuration, the distance between the word lines WL1, WL2, ... and the capacitive contact plug 18 is larger than the distance between the gate electrode 9 and the center of the lower electrode 13 in plan view. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a capacitor.

  As a kind of nonvolatile memory, there is known an FeRAM (Ferroelectric Random Access Memory) that retains data by using a hysteresis (history phenomenon) of a ferroelectric substance.

  There are two types of FeRAM, which are roughly classified according to the difference in cell structure. One has a 1T1C type cell structure including a field effect transistor for selecting a memory cell and a ferroelectric capacitor, and the other has a field effect transistor whose gate insulating film is made of a ferroelectric. It has a 1T type cell structure.

  FIG. 7 is a schematic plan view of a FeRAM having a conventional 1T1C type cell structure.

  The FeRAM includes a P-type silicon substrate (not shown). An element isolation portion (for example, a LOCOS oxide film) is selectively formed on the surface of the silicon substrate, and a plurality of rectangular active regions 101 in plan view are exposed from the element isolation portion. The active regions 101 are arranged in a matrix that is aligned in the longitudinal direction and in a direction orthogonal to the longitudinal direction.

  In the active region 101, two memory cells are formed. Each memory cell has a 1T1C type cell structure.

  N-type impurity regions are formed at both ends and a central portion of the active region 101 in the longitudinal direction in the surface layer portion of the silicon substrate at intervals. The impurity region at one end of the active region 101 forms a drain region of a field effect transistor provided in one memory cell. The impurity region at the other end of the active region 101 forms a drain region of a field effect transistor provided in the other memory cell. The impurity region at the center of the active region 101 forms a source region common to the field effect transistors included in the two memory cells.

  On the silicon substrate, a gate electrode 102 is provided at a position facing each channel region between the source region and each drain region. The gate electrodes 102 of the field effect transistors arranged in a direction orthogonal to the longitudinal direction of the active region 101 are integrated to form one word line WL.

  An interlayer insulating film is stacked on the silicon substrate. On the interlayer insulating film, a ferroelectric capacitor 103 is provided at a position facing the drain region of each memory cell (above one end and the other end in the longitudinal direction of the active region 101). The ferroelectric capacitor 103 has a laminated structure in which a ferroelectric film is interposed between the lower electrode 104 and the upper electrode 105.

  The lower electrode 104 has a substantially square shape in plan view. A first contact plug 106 is provided through the interlayer insulating film between the center portion of the lower electrode 104 and the drain region. The lower electrode 104 is electrically connected to the drain region via the first contact plug 106.

  The upper electrode 105 has a substantially square shape in plan view smaller than the lower electrode 104. Above the central portion of the upper electrode 105, the plate line PL extends in a direction orthogonal to the longitudinal direction of the active region 101. The plate line PL is electrically connected to the upper electrode 105.

  In addition, the bit line BL extends in the longitudinal direction of the active region 101 above the active region 101. The bit line BL is electrically connected to the source region at the center of the active region 101 via the second contact plug 107.

When a voltage is applied between the plate line PL and the bit line BL in a state where the field effect transistor is turned on by applying a voltage to the word line WL, spontaneous polarization is applied to the ferroelectric film of the ferroelectric capacitor 103. Occurs. As a result, data writing is achieved and the polarization state is maintained, so that the data is retained. At the time of reading data, a pulse voltage is applied between the plate line PL and the bit line BL while the field effect transistor is turned on by applying a voltage to the word line WL. When the polarization direction of the ferroelectric film is changed by the application of the pulse voltage, a current flows between the plate line PL and the bit line BL, so that a logic signal “1” or “0” is obtained depending on the presence or absence of the current. be able to.
JP 2004-95915 A

  FeRAM has design rules. In this design rule, the minimum distance between the gate electrode 102 and the first contact plug 106, the minimum distance between the peripheral edge of the lower electrode 104 and the first contact plug 106, the first contact plug 106 and the second contact. A minimum distance from the plug 107 is determined. In order to reduce the area of the memory cell (cell area) while complying with the design rules, it is necessary to devise the layout of each part of the FeRAM.

  Accordingly, an object of the present invention is to provide a semiconductor device capable of reducing the cell area while following the design rule.

  According to a first aspect of the present invention for achieving the above object, a semiconductor layer of a first conductivity type, a first impurity region of a second conductivity type formed in a surface layer portion of the semiconductor layer, and the semiconductor layer A second impurity region of a second conductivity type formed in the surface layer portion at a distance from the first impurity region; and formed on the semiconductor layer, between the first impurity region and the second impurity region. A gate electrode facing the region; a lower electrode formed above the first impurity region; an upper electrode formed on the lower electrode; a lower end connected to the first impurity region; A semiconductor device including a capacitor contact plug connected to the electrode, wherein a distance between the gate electrode and the capacitor contact plug is larger than a distance between the gate electrode and the center of the lower electrode in plan view It is.

  In this semiconductor device, the first conductivity region and the second impurity region of the second conductivity type are formed at a distance from each other in the surface layer portion of the semiconductor layer of the first conductivity type. A gate electrode is formed on the semiconductor layer. The gate electrode is opposed to a region (channel region) between the first impurity region and the second impurity region. A capacitor including a lower electrode and an upper electrode is formed above the first impurity region. The first impurity region and the lower electrode are connected via a capacitance contact plug.

  The distance between the gate electrode and the capacitor contact plug is larger than the distance between the gate electrode and the center of the lower electrode in plan view. Therefore, even when the capacitor and the gate electrode are provided close to each other, the minimum distance determined by the design rule can be ensured between the gate electrode and the capacitor contact plug. Therefore, the cell area can be reduced by bringing the capacitor and the gate electrode closer while following the design rule.

  The semiconductor device includes a plate line formed above the upper electrode, a plate via having a lower end connected to the central portion of the upper electrode in plan view, and an upper end connected to the plate line. May be further provided.

  In this case, if the center of the lower electrode coincides with the center of the upper electrode in plan view, the capacitor contact plug and the plate via are shifted from each other in plan view.

  According to a fourth aspect of the present invention, the semiconductor device further includes an element isolation portion that is selectively formed on the surface of the semiconductor layer and isolates the plurality of active regions from each other, and the first impurity region includes each active region In this case, it is preferable that the second impurity region is formed at two positions spaced apart from each other in a predetermined direction, and the second impurity region is formed at a position off the straight line connecting the two first impurity regions in each active region. This layout allows the first impurity region to be formed without increasing the distance between the two first impurity regions as compared with a layout in which the two first impurity regions and the second impurity region are formed in a straight line. The minimum distance between the capacitor contact plug to be connected and the bit contact plug connected to the second impurity region can be increased.

  In this case, for example, the active region has a first region extending in a predetermined direction, and a second region extending in a direction orthogonal to the predetermined direction from both ends of the first region. The first impurity region is formed at the end of each second region, and the second impurity region is formed at the center of the first region. In this configuration, when a plurality of active regions are provided side by side in a direction orthogonal to a predetermined direction, between two adjacent active regions, the first region of one active region and the second region of the other active region are arranged. The distance in the direction perpendicular to the predetermined direction is the shortest distance, and even if those active areas are shifted in the predetermined direction, the shortest distance cannot be increased.

  Therefore, as described in claim 5, the active region has a V-shape in plan view, the first impurity region is formed at both ends of the active region, and the second impurity region is formed at the bent portion of the active region. More preferably, it is formed. In this configuration, in the two active regions, the active regions are shifted in a predetermined direction so that the bent portion of one active region does not face the end of the other active region in a direction orthogonal to the predetermined direction. By forming, the shortest distance between the active regions can be increased.

  In this case, the semiconductor device includes a bit line formed above the second impurity region and a bit electrically connected to the bit line, the lower end being connected to the second impurity region. A contact plug is further provided, and the gate electrode preferably extends in a direction orthogonal to a straight line connecting the capacitor contact plug and the bit contact plug. With this configuration, the distance between the capacitor contact plug and the bit contact plug can be kept constant, and the shortest distances between the gate electrode, the capacitor contact plug, and the bit contact plug can be maximized.

  According to a seventh aspect of the present invention, the active region has a T-shape in plan view having a linear region extending in a predetermined direction and an orthogonal region orthogonal to the linear region at the center of the linear region, and the first impurity region is The second impurity region may be formed at both ends of the linear region, and the second impurity region may be formed at the end of the orthogonal region.

  As described in claim 8, the semiconductor device may further include a ferroelectric film interposed between the lower electrode and the upper electrode. That is, the semiconductor device may include a ferroelectric capacitor including a lower electrode, an upper electrode, and a ferroelectric film interposed therebetween.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic plan view of an FeRAM according to the first embodiment of the present invention. FIG. 2 is a circuit diagram of the FeRAM shown in FIG. 3 is a schematic cross-sectional view taken along section line III-III of FeRAM shown in FIG. 4 is a schematic cross-sectional view taken along section line IV-IV of the FeRAM shown in FIG.

  The FeRAM 1 includes a plurality of memory cells. Each memory cell has a 1T1C type cell structure. 1 and 2 show a part of the FeRAM 1. In FIG. 2, one memory cell is surrounded by a broken line.

  The FeRAM 1 includes a P-type semiconductor layer 2 as shown in FIGS. The semiconductor layer 2 may be a semiconductor substrate such as a Si (silicon) substrate or a SiC (silicon carbide) substrate, or may be a Si layer or a SiC layer formed by epitaxial growth or a CVD method.

  An element isolation portion 4 (see FIG. 4) is selectively formed on the surface of the semiconductor layer 2 so as to avoid the plurality of active regions 3. The element isolation part 4 may have, for example, an STI (Shallow Trench Isolation) structure in which an insulator is buried in a groove dug relatively shallow from the surface of the semiconductor layer 2 or a LOCOS (Local Oxidation of). A silicon oxide film selectively formed on the surface of the semiconductor layer 2 by the silicon method may be used.

  In FIG. 1, the outline of the active region 3 is indicated by a bold line. The active regions 3 are arranged at a certain interval in the row direction (plate line direction), and form a plurality of rows. Between the rows formed by the active regions 3, a certain interval is provided in the column direction (bit line direction) orthogonal to the row direction. The position of the active region 3 forming one row is shifted by ½ of the interval in the row direction of the two active regions 3 with respect to the position of the active region 3 forming a row adjacent thereto. That is, the active areas 3 are arranged in a staggered manner. Each active region 3 has a V-shape in plan view that bends at an internal angle of 90 degrees. Both end portions 3A of each active region 3 are arranged on one side in the row direction with respect to the bent portion 3B.

  3 and 4, each active region 3 has two N-channel MOSFETs (hereinafter referred to as “NMOS”) 5 in the surface layer portion of the semiconductor layer 2. Impurity regions 6 and 7 are formed. The impurity region 6 is formed at both end portions 3 </ b> A of the active region 3 and forms the drain regions of the two NMOSs 5. The impurity region 7 is formed in the bent portion 3B of the active region 3 and forms a common source region for the two NMOSs 5.

As shown in FIG. 3, a gate insulating film 8 is formed on the semiconductor layer 2 at a position facing the region between the drain region 6 and the source region 7 (the channel region of the NMOS 5). The gate insulating film 8 is made of, for example, SiO ₂ (silicon oxide). A gate electrode 9 is formed on the gate insulating film 8. The gate electrode 9 is made of, for example, doped polysilicon (for example, polysilicon doped with an N-type impurity at a high concentration). A sidewall 10 is formed around the gate electrode 9. The sidewall 10 covers the entire circumference of the side surfaces of the gate insulating film 8 and the gate electrode 9. The sidewall 10 is made of, for example, SiN (silicon nitride) or SiO ₂ .

  As shown in FIGS. 1 and 2, the gate electrodes 9 of the NMOSs 5 arranged in the row direction are integrated to form word lines WL1, WL2,. The word lines WL1, WL2,... Meander and extend above the channel region of the NMOSs 5 arranged in the row direction so as to be orthogonal to the active region 3 in plan view.

As shown in FIGS. 3 and 4, a first interlayer insulating film 11 is stacked on the semiconductor layer 2. The first interlayer insulating film 11 is made of, for example, SiO ₂ .

  A ferroelectric capacitor 12 is disposed on the first interlayer insulating film 11 at a position facing each drain region 6. As shown in FIG. 4, the ferroelectric capacitor 12 has a center on the side of the word line WL1, WL2,... (On the opposite direction of both end portions 3A of the active region 3) with respect to the center of the drain region 6 facing it. It is formed so as to be displaced inward. As shown in FIG. 1, the ferroelectric capacitors 12 are arranged in alignment in the row direction and the column direction as a whole.

  As shown in FIG. 4, the ferroelectric capacitor 12 has a structure in which a lower electrode 13, a ferroelectric film 14, and an upper electrode 15 are laminated on the first interlayer insulating film 11 in this order. In other words, the ferroelectric capacitor 12 has a structure in which the ferroelectric film 14 is interposed between the lower electrode 13 and the upper electrode 15. The ferroelectric capacitor 12 has a trapezoidal cross section with the upper portion narrowed due to difficulty in etching at the time of formation.

  The lower electrode 13 has a substantially square shape in plan view. The lower electrode 13 is made of a conductive material containing a noble metal such as Ir.

The ferroelectric film 14 is made of, for example, PZT (Pb (Zr, Ti) O ₃ : lead zirconate titanate).

The upper electrode 15 has a substantially square shape in plan view smaller than the lower electrode 13. The upper electrode 15 has a structure in which, for example, an IrO ₂ (iridium oxide) film, an Ir (iridium) film, and an IrTa (iridium tantalum) alloy film are laminated on the ferroelectric film 14 in this order. The IrTa alloy film has a hydrogen barrier property.

Each surface of the first interlayer insulating film 11 and the ferroelectric capacitor 12 is covered with a hydrogen barrier film 16 for preventing characteristic deterioration due to hydrogen reduction of the ferroelectric film 14. The hydrogen barrier film 16 is made of, for example, Al ₂ O ₃ (alumina).

A second interlayer insulating film 17 is laminated on the hydrogen barrier film 16. The second interlayer insulating film 17 is made of, for example, SiO ₂ .

  As shown in FIGS. 1 and 2, the FeRAM 1 further includes plate lines PL1, PL2,... And bit lines BL1, BL2, BL3,. The plate lines PL1, PL2,... And the bit lines BL1, BL2, BL3,... Are separated from each other by an interlayer insulating film (not shown) above the second interlayer insulating film 17, for example. Formed on the wiring layer.

  The plate lines PL1, PL2,... Extend substantially linearly via the center of the upper electrode 15 of each ferroelectric capacitor 12 aligned in the row direction. The plate lines PL1, PL2,... Are made of, for example, Al (aluminum).

  The bit lines BL1, BL2, BL3,... Extend linearly via the source regions 7 formed in the active regions 3 arranged in the column direction. The bit lines BL1, BL2, BL3,... Are made of Al, for example.

  As shown in FIG. 4, a capacitance contact plug 18 is buried in the first interlayer insulating film 11 between each drain region 6 and the lower electrode 13 of the ferroelectric capacitor 12 facing the drain region 6. Specifically, a capacitor contact hole 19 penetrating the first interlayer insulating film 11 is formed on the central portion of the drain region 6. A barrier metal 20 is formed on the side surface of the capacitor contact hole 19 and on the portion of the drain region 6 facing the capacitor contact hole 19. The barrier metal 20 is made of, for example, TiN (titanium nitride). The capacitor contact plug 18 is embedded in the capacitor contact hole 19 via the barrier metal 20. Thereby, the lower end of the capacitor contact plug 18 is connected to the central portion of the drain region 6 through the barrier metal 20, and the upper end thereof is connected to the word lines WL1, WL2,. It is connected to a position shifted to the opposite side (outside in the opposing direction of both end portions 3A of the active region 3). The capacitor contact plug 18 is made of, for example, W (tungsten).

  In the second interlayer insulating film 17, a plate via 21 is embedded between the upper electrode 15 of each ferroelectric capacitor 12 and the plate lines PL1, PL2,. Specifically, a plate via hole 22 is formed on the central portion of the upper electrode 15. The plate via hole 22 penetrates the second interlayer insulating film 17, further penetrates the hydrogen barrier film 16, and its lower end reaches the upper electrode 15. A barrier metal 23 is formed on the side surface of the plate via hole 22 and on the portion of the upper electrode 15 and the hydrogen barrier film 16 that faces the plate via hole 22. The barrier metal 23 is made of TiN, for example. The plate via 21 is embedded in the plate via hole 22 via the barrier metal 23. Thereby, the lower end of the plate via 21 is connected to the central portion of the upper electrode 15 through the barrier metal 23, and the upper end thereof is connected to the plate lines PL1, PL2,. In FIG. 1 and FIG. 5 described later, the plate via 21 is indicated by a solid line from the viewpoint of visibility.

  Further, as shown in FIG. 3, a bit contact hole 24 penetrating the first interlayer insulating film 11, the hydrogen barrier film 16 and the second interlayer insulating film 17 are continuously penetrated above each source region 7. Bit via holes 25 are formed in communication with each other. A barrier metal 26 made of the same material as the barrier metal 20 is formed on the side surface of the bit contact hole 24 and on the portion of the source region 7 facing the bit contact hole 24. A bit contact plug 27 made of the same material as that of the capacitor contact plug 18 is embedded inside the barrier metal 26. Thus, the lower end of the bit contact plug 27 is connected to the source region 7 via the barrier metal 26. On the other hand, a barrier metal 28 made of the same material as the barrier metal 23 is formed on the side surface of the bit via hole 25 and on the portion of the hydrogen barrier film 16 and the bit contact plug 27 that faces the bit via hole 25. A bit via 29 made of the same material as that of the plate via 21 is embedded inside the barrier metal 28. The bit contact plug 27 is electrically connected to the bit lines BL1, BL2, BL3,... Via the barrier metal 28 and the bit via 29.

  When the NMOS 5 is turned on by applying a voltage to the word lines WL1, WL2,..., A voltage is applied between the plate lines PL1, PL2,. When applied, spontaneous polarization occurs in the ferroelectric film 14 of the ferroelectric capacitor 12. As a result, data writing is achieved and the polarization state is maintained, so that the data is retained. When reading data, the plate lines PL1, PL2,... And the bit lines BL1, BL2, BL3,... And the NMOS 5 are turned on by applying voltages to the word lines WL1, WL2,. During this period, a pulse voltage is applied. When the polarization direction of the ferroelectric film 14 is changed by the application of this pulse voltage, current flows between the plate lines PL1, PL2,... And the bit lines BL1, BL2, BL3,. The logic signal “1” or “0” can be obtained depending on the presence or absence of.

  As described above, in the FeRAM 1, the N-type drain region 6 and the source region 7 are formed in the surface layer portion of the P-type semiconductor layer 2 with a space therebetween. A gate electrode 9 is formed on the semiconductor layer 2. The gate electrode 9 faces the region between the drain region 6 and the source region 7 (the channel region of the NMOS 5). Above the drain region 6, a ferroelectric capacitor 12 including a lower electrode 13, a ferroelectric film 14 and an upper electrode 15 is formed. The drain region 6 and the lower electrode 13 are connected via a capacitive contact plug 18.

  The capacitor contact plug 18 is provided at a position shifted from the center of the lower electrode 13 on the opposite side to the word lines WL1, WL2,. Thereby, the distance between the word lines WL1, WL2,... (Gate electrode 9) and the capacitor contact plug 18 is larger than the distance between the gate electrode 9 and the center of the lower electrode 13 in plan view. ing. Therefore, even if the ferroelectric capacitor 12 and the gate electrode 9 are provided close to each other, the minimum distance determined by the design rule can be ensured between the gate electrode 9 and the capacitor contact plug 18. Therefore, the cell area can be reduced by bringing the ferroelectric capacitor 12 and the gate electrode 9 closer to each other while following the design rule.

  Further, the drain region 6 is formed at two positions spaced in the column direction in each active region 3, and the source region 7 is off the straight line connecting the two drain regions 6 in each active region 3. Formed in position. More specifically, the active region 3 has a V shape in plan view, the drain region 6 is formed at both end portions 3A of the active region 3, and the source region 7 is formed at the bent portion 3B of the active region 3. ing. With this layout, the capacitance connected to the drain region 6 without increasing the distance between the two drain regions 6 as compared with the layout in which the two drain regions 6 and the source region 7 are formed in a straight line. The minimum distance between the contact plug 18 and the bit contact plug 27 connected to the source region 7 can be increased.

  Further, when attention is paid to one active region 3 and the active region 3 adjacent to the active region 3 in the direction intersecting the row direction and the column direction, the end portion 3A of one active region 3 is the other active region. The active areas 3 are arranged in a staggered manner so that the end portions 3A and the bent portions 3B are not opposed to the three bent portions 3B in the row direction, but are shifted in the column direction. As a result, the shortest distance between the two active regions 3 of interest is greater than the linear distance between the end 3A of one active region 3 and the bent portion 3B of the other active region 3. Therefore, the shortest distance between the active regions 3 can be increased without increasing the distance in the row direction between the bent portions 3B of the two active regions 3 of interest.

  Further, the word lines WL1, WL2,... Formed by the gate electrode 9 meander and extend so as to be orthogonal to the active region 3 in plan view. Thereby, each word line WL1, WL2,... Is orthogonal to a straight line connecting the capacitor contact plug 18 and the bit contact plug 27 in a plan view. Therefore, the distance between the capacitor contact plug 18 and the bit contact plug 27 can be kept constant, and the shortest distances between the gate electrode 9, the capacitor contact plug 18 and the bit contact plug 27 can be maximized. As a result, the capacitor contact plug 18 (drain region 6) and the bit contact plug are secured while securing the distances between the gate electrode 9 and the capacitor contact plug 18 and the bit contact plug 27 to be equal to or longer than the shortest distances defined by the design rules. 27 (source region 7) can be brought close to each other. Therefore, the area of the active region 3 can be reduced, and the cell area can be further reduced.

  FIG. 5 is a schematic plan view of an FeRAM according to the second embodiment of the present invention. FIG. 6 is a circuit diagram of the FeRAM shown in FIG. 5 and 6, parts corresponding to the parts shown in FIGS. 1 and 2 are denoted by the same reference numerals as those parts. In the following, the structure shown in FIGS. 5 and 6 will be described by taking only the differences from the structure shown in FIGS. 1 and 2, and the description of each part given the same reference numeral will be omitted.

  In the FeRAM 51 shown in FIGS. 5 and 6, a plurality of active regions 52 are arranged in a matrix aligned in the row direction and the column direction. In FIG. 5, the outline of the active region 52 is indicated by a bold line. Each active region 52 has a T-shape in plan view having a straight region 52A extending in the column direction and an orthogonal region 52B orthogonal to the straight region 52A at the center of the straight region 52A. The drain region 6 (see FIG. 3) is formed at both ends of the linear region 52A of each active region 52, and the source region 7 (see FIG. 3) is formed at the end of the orthogonal region 52B.

  In the FeRAM 51, the word lines WL1, WL2,... Are located at positions facing the regions other than the drain region 6 (the channel region of the NMOS 5) in the linear region 52A on both sides in the column direction of the orthogonal region 52B of the active region 52. Are formed in a straight line extending in the row direction.

  Also in the FeRAM 51, as in the FeRAM 1 shown in FIG. 1, the capacitor contact plug 18 is provided at a position shifted from the center of the lower electrode 13 on the opposite side to the word lines WL1, WL2,. It has been. Thereby, the distance between the word lines WL1, WL2,... (Gate electrode 9) and the capacitor contact plug 18 is larger than the distance between the gate electrode 9 and the center of the lower electrode 13 in plan view. ing. Therefore, even if the ferroelectric capacitor 12 and the gate electrode 9 are provided close to each other, the minimum distance determined by the design rule can be ensured between the gate electrode 9 and the capacitor contact plug 18. Therefore, the cell area can be reduced by bringing the ferroelectric capacitor 12 and the gate electrode 9 closer to each other while following the design rule.

  Although two embodiments of the present invention have been described above, various design changes can be made to each embodiment within the scope of the matters described in the claims.

  For example, the present invention can be applied not only to FeRAM but also to a DRAM (Dynamic Random Access Memory) including a paraelectric capacitor.

FIG. 1 is a schematic plan view of an FeRAM according to the first embodiment of the present invention. FIG. 2 is a circuit diagram of the FeRAM shown in FIG. 3 is a schematic cross-sectional view taken along section line III-III of FeRAM shown in FIG. 4 is a schematic cross-sectional view taken along section line IV-IV of the FeRAM shown in FIG. FIG. 5 is a schematic plan view of an FeRAM according to the second embodiment of the present invention. FIG. 6 is a circuit diagram of the FeRAM shown in FIG. It is an illustration top view of conventional FeRAM.

Explanation of symbols

1 FeRAM
2 Semiconductor layer 3 Active region 3A End portion 3B Bent portion 4 Element isolation portion 6 Drain region (first impurity region)
7 Source region (second impurity region)
9 Gate electrode 12 Ferroelectric capacitor 13 Lower electrode 14 Ferroelectric film 15 Upper electrode 18 Capacitor contact plug 21 Plate via 27 Bit contact plug 51 FeRAM
52 Active area 52A Linear area 52B Orthogonal area BL1, BL2, BL3 Bit line PL1, PL2 Plate line WL1, WL2 Word line

Claims (8)

A first conductivity type semiconductor layer;
A first impurity region of a second conductivity type formed in a surface layer portion of the semiconductor layer;
A second impurity region of a second conductivity type formed in a surface layer portion of the semiconductor layer and spaced from the first impurity region;
A gate electrode formed on the semiconductor layer and facing a region between the first impurity region and the second impurity region;
A lower electrode formed above the first impurity region;
An upper electrode formed on the lower electrode;
A capacitor contact plug having a lower end connected to the first impurity region and an upper end connected to the lower electrode;
A semiconductor device, wherein a distance between the gate electrode and the capacitor contact plug is larger than a distance between the gate electrode and the center of the lower electrode in plan view. A plate line formed above the upper electrode;
The semiconductor device according to claim 1, further comprising a plate via having a lower end connected to a central portion of the upper electrode in a plan view and an upper end connected to the plate line.   The semiconductor device according to claim 2, wherein the capacitor contact plug and the plate via are shifted from each other in plan view. An element isolation part that is selectively formed on a surface of the semiconductor layer and isolates a plurality of active regions from each other;
The first impurity region is formed at two positions spaced apart in a predetermined direction in each active region,
The semiconductor device according to claim 1, wherein the second impurity region is formed at a position deviating from a straight line connecting the two first impurity regions in each active region. The active area is V-shaped in plan view,
The first impurity region is formed at both ends of the active region,
The semiconductor device according to claim 4, wherein the second impurity region is formed in a bent portion of the active region. A bit line formed above the second impurity region;
A bit contact plug having a lower end connected to the second impurity region and electrically connected to the bit line;
The semiconductor device according to claim 5, wherein the gate electrode extends in a direction orthogonal to a straight line connecting the capacitor contact plug and the bit contact plug. The active region has a T-shape in a plan view having a linear region extending in the predetermined direction and an orthogonal region orthogonal to the linear region at the center of the linear region,
The first impurity region is formed at both ends of the linear region,
The semiconductor device according to claim 4, wherein the second impurity region is formed at an end portion of the orthogonal region.   The semiconductor device according to claim 1, further comprising a ferroelectric film interposed between the lower electrode and the upper electrode.

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