JPS63158870A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce an area, to minimize leakage currents and to increase memory capacitance by forming a first conductivity type semiconductor region having impurity concentration larger than a semiconductor substrate constituting a P-N junction with a source region and introducing a second conductivity type impurity into a region, in which an inversion layer is shaped, and which is the section of the semiconductor region brought into contact with a gate insulating film. CONSTITUTION:A P-type semiconductor region 40a is exposed on the N-type semiconductor region 50 side in a section between an N-type semiconductor region 50 in the surface of a semiconductor base body and an N-type semiconductor region 60 and brought into contact with a gate oxide film 70, and the impurity concentration of the region 40a is larger than that of a semiconductor substrate 10. A device is operated at low voltage by implanting a proper quantity of an N-type impurity to a section being in contact with the gate oxide film 70 in the P-type semiconductor region 40a and changing the section into a P-type semiconductor region 41 in low impurity concentration while the effective channel length of a transfer gate is shortened and operation at high speed is also enabled by introducing the N-type impurity to a section 11 being in contact with the gate oxide film 70 of the P-type semiconductor substrate 10.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor memory device obtained by combining an insulated gate type semiconductor device and a PN junction.

FIG. 1 shows a vertical cross-sectional view of a device conventionally known as a one-transistor, one-capacitor type semiconductor memory device. In FIG. 1, for example, (1G is a P-type semiconductor substrate with a low impurity concentration, a P-type semiconductor region (■) and an oxide film region (■) are formed as a channel stopper on the surface thereof, and further,
N-type semiconductor region.

form ill.

A gate oxide film +7 (1
゜(2), and gate metals ■ and 2 are formed on the gate oxide film (iυ), respectively.Furthermore, an oxide film shield is formed to protect the semiconductor surface and enable multilayer wiring. .- is an electrode taken out from the N-type semiconductor region
N-type semiconductor region l is pit line, gate metal! 81)
is used as a straciline. The stracie line made of Gate Metal (Incorporated) corresponds to the gate part of a MOS capacitor with the N-type semiconductor region as the drain and the gate metal I8D as the gate. By applying a voltage higher than the threshold voltage of the semiconductor substrate surface, an inversion layer can be formed on the surface of the P-type semiconductor substrate 00 under the gate oxide film 1711. The MO3 capacitor with this inversion layer as one electrode is defined as a storage capacitor. In addition, a MOS (MOS) transistor having an N-type semiconductor region as a source, an N-type semiconductor region as a drain, and a gate metal as a gate is used as a transfer gate. When writing a high level l, the bit line is set to a high potential and the word line is applied with a voltage higher than the threshold voltage of the semiconductor substrate surface in contact with the gate oxide film surface.
) The transistor becomes conductive, and the voltage of the N-type conductor region becomes the voltage obtained by subtracting the threshold voltage of the semiconductor substrate surface in contact with the gate oxide film from the potential of the N-type semiconductor region. Electrons are also injected into the inversion layer. From this state, if the word line voltage is lowered below the threshold voltage of the semiconductor substrate surface in contact with the gate oxide film, the transfer gate becomes non-conductive and is inverted, regardless of changes in the bit line voltage. Electrons injected into the layer are fixed. However, the strain line must always be maintained at a threshold voltage higher than the threshold voltage of the surface of the semiconductor substrate in contact with the gate oxide film (2). In addition, when writing 40 U levels, after setting the bit line to a low potential, by applying a voltage higher than the threshold voltage of the semiconductor substrate surface in contact with the gate oxide film [phase] to the word line, the inversion layer The electrons accumulated in the memory 811 are drawn out to the bit line, and then when the word line is lowered below the threshold voltage of the semiconductor substrate surface in contact with the gate oxide film +71, a 10 level l is written in the memory 811. I'll tell you what happened. For reading, after fixing the bit line voltage to a certain floating level, the word line voltage is raised to a threshold voltage or higher of the semiconductor substrate surface in contact with the gate oxide film surface.
This is possible by detecting voltage changes on the bit line.

This nesting can reduce the area occupied by the negative element compared to dynamic MO9 storage elements with 3 or 4 transistors, but it increases the degree of integration from the point of view of large capacity storage devices. is not enough, and also
Three lines, a word line, a bit line, and a storage line, are required, and the wiring and storage area for the storage line consumes a large area, which has the disadvantage of lowering the degree of integration. Since an inversion layer is used, leakage current due to surface states, traps, etc. increases, and the interval between stored information becomes shorter, which may cause problems in system design.

FIG. 2E shows a vertical cross-sectional view of a conventional memory element that compensates for some of the drawbacks of the one-transistor, one-capacity type memory element described above. In FIG. 2, for example, αa is a low impurity concentration P
This is a type semiconductor substrate, on the surface of which a P type semiconductor region 4 and an oxide film region 2 are formed as a channel stopper, and further N type semiconductor regions 1 and 2 are formed. N-type semiconductor region [,11! An oxide film is grown on the semiconductor substrate so as to partially overlap the gate oxide film as a gate oxide film decoy, and a gate metal film is formed on the surface of the gate oxide film.

Furthermore, an oxide film (2) is formed to protect the semiconductor surface and to enable multilayer wiring. (2) is an electrode taken out from the N-type semiconductor region. This memory element is of a two-line type using the N-type semiconductor region ω as a bit line and the gate metal layer as a word line, and the memory capacity uses the junction capacitance between the P-type semiconductor substrate OI and the N-type semiconductor region -. Furthermore, a MOS transistor is used as a transfer gate, with the N-type semiconductor region serving as the drain, the N-type semiconductor region serving as the source, and the gate metal serving as the gate.

When writing a high level ', the bit line is set to a high potential fζ and the word line is set to a voltage Iζ higher than the threshold voltage of the semiconductor substrate surface in contact with the gate oxide ieta, thereby making the transfer gate conductive and converting the N-type semiconductor into a conductive state. The region becomes a potential obtained by subtracting the threshold voltage of the semiconductor substrate surface in contact with the gate oxide film [phase] from the potential of the N-type semiconductor region ω, and the junction between the P-type semiconductor substrate αG and the N-type semiconductor region Iυ Electrons are injected into the potential well sandwiched between the oxide films. From this state, if the word line voltage is lowered below the threshold voltage of the semiconductor substrate surface in contact with the gate oxide film, the transfer gate becomes non-conductive.
Regardless of changes in the bit line voltage, the potential well t and the injected electrons are fixed. In addition, when writing a low level l, after setting the bit line to zero potential, the word line is set to a potential higher than the threshold voltage of the semiconductor substrate surface in contact with the gate oxide film σG, so that the potential well is not injected. If the electrons are pulled out to the bit line and then the word line is rubbed below the threshold voltage of the semiconductor substrate surface in contact with the gate oxide film surface, 10
This means that Urebelke has been written in. For reading, after fixing the potential of the bit line to a fixed floating level, the voltage of the word line is set to be higher than the threshold voltage of the semiconductor substrate surface in contact with the gate oxide film, and the voltage change of the bit line is detected. This becomes possible. Since this element uses the junction capacitance between the P-type semiconductor substrate αe with a low impurity concentration and the N-type semiconductor region as a storage capacitance, the capacitance per unit area is small, and unless the area of the storage capacitor part is made large, the readout The voltage variation of the bit line at the time is not large, which leaves problems in the design of the memory device, and - increasing the area of the memory element has the disadvantage that it is not suitable for large capacity and high integration.

FIG. 3 is a longitudinal cross-sectional view of a conventional memory element that compensates for the drawbacks of the memory element shown in FIG. In Figure 3, Q(l
is a P-type semiconductor substrate with a low impurity concentration, on the surface of which a P-type semiconductor head ■ and an oxide film region ■ are formed as a channel stopper, and at appropriate portions of the semiconductor substrate surface other than the oxide film region ■. Intervals between P-type semiconductor regions with high impurity concentration are formed, and further N-type semiconductor regions are formed. Further, an N-type semiconductor region ω is formed between the P-type semiconductor regions and the surface of the semiconductor substrate, and a PN junction is formed inside the semiconductor substrate. An oxide film is grown on the semiconductor substrate so as to partially overlap the N-type semiconductor regions - and ωE, forming a gate oxide layer 1117G, and a gate metal layer is formed on the gate oxide film (1117G). Furthermore, an oxide film (2) is formed to protect the semiconductor surface and to enable layer wiring.

(2) is an electrode taken out from the N-type semiconductor region ω.

This memory element is of a two-line type using the N-type semiconductor region ω as a bit line and the gate metal as a word line, and the memory capacity uses the junction capacitance between the P-type semiconductor region and the N-type semiconductor region . Further, a MOS transistor with the N-type semiconductor region ω as the drain, the N-type semiconductor region ω as the source, and the gate gate is used as a transfer gate. When writing 1 high level into the storage capacitor, the transfer gate is made conductive by setting the bit line to a high potential and the word line to a voltage higher than the threshold voltage of the semiconductor substrate surface in contact with the gate oxide film surface. State E is established, and electrons are injected into the N-type semiconductor region (2).

The N-type semiconductor region - forms a potential well ' surrounded by the oxide film ■, the P-type semiconductor region I, and the P-type semiconductor substrate OI with a low impurity concentration, and electrons are injected into this potential well and fixed. 4.Write the memory capacity l of the high level register. In addition, when writing the 10U level' into the storage capacity, after lowering the pit line to a low potential, the gate oxide film (
′? By raising the potential of the word line above the threshold voltage of the semiconductor substrate surface in contact with Q, the transfer gate becomes conductive and electrons are extracted to the bit line.
After that, if the potential of the word line is made lower than the threshold voltage of the semiconductor substrate surface in contact with the gate oxide film σG and the transfer gate is made non-conductive, electrons are generated in the potential well of the N-type semiconductor region ■. is not injected, and 10 levels are written. For reading, after fixing the bit line to a constant potential, applying a potential higher than the threshold voltage of the semiconductor substrate surface in contact with the gate oxide film t71 to the word line, the electrons accumulated in the N-type semiconductor region This is possible by detecting the change in the potential of the bit line depending on whether it is drawn out to the bit line or implanted into the N-type semiconductor region group, and detecting this displacement. Since this semiconductor memory device uses internal junction capacitance, surface crystal non-uniformity is less of a problem than memory devices that use gate oxide films, and leakage current is small. In addition, since a PN junction in a semiconductor region with relatively high concentration can be used, it is easy to obtain a capacitance value per unit area equal to or higher than that using a gate oxide film, making it possible to achieve high integration.・
It has the characteristics of being able to obtain a memory cluster suitable for high-density storage, and because it is a two-line system, it provides a degree of freedom in terms of surface area.

However, in the above-mentioned memory element, the area of the PN junction formed by the P-type semiconductor region (iG and the N-type semiconductor region ω) decreases due to mask alignment misalignment during formation of the P-type semiconductor regions.
This may lead to a reduction in the effective storage capacity area.

The present invention has been made in view of the above points, and is a small-sided device that has low leakage current, large storage capacity, and reduces the effective storage capacity area due to mask alignment misalignment. The object of the present invention is to provide a method for manufacturing a two-line type semiconductor memory device.

Hereinafter, the present invention will be explained based on Examples.

FIG. 4 is a longitudinal sectional view of a storage element of the first embodiment of the semiconductor storage device according to the present invention. In FIG. 4, the same reference numerals as in FIG. 3 represent the same components as shown in FIG. (40a) is exposed on the N-type semiconductor region ω side of the part between the N-type semiconductor region This is a highly concentrated P-type semiconductor region.

The operating principle of the memory element of this first embodiment as a memory element is exactly the same as that of the conventional example shown in FIG. The P-type semiconductor region (40a) is a gate oxide film at
As long as it is different, this mask alignment deviation lζ has no effect on the area of the PN junction formed by the P-type semiconductor region (40a) and the N-type semiconductor box area ω. Therefore, there is no reduction in the effective storage capacity area.

However, in this first embodiment, the gate oxide film σ
(Since the threshold voltage of the surface of the semiconductor substrate in contact with Hζ becomes high, the transformer 7 agate cannot be made conductive unless a high potential is applied to the word line.

In order to compensate for this drawback, it is necessary to effectively reduce the impurity concentration in the P type≠conductor area (40a), but there are generally well-known methods for effectively reducing this impurity concentration. This can be achieved by implanting an appropriate amount of N-type impurities into the P-type semiconductor region (40a), since it is sufficient to implant impurities of different conductivity types into the P-type semiconductor region (40a).

A second embodiment of the semiconductor memory device according to the present invention has been improved based on this principle, and the vertical cross-sectional view of the memory element is shown in FIG.

In the memory element of the second example, the P-type semiconductor region (
By implanting an appropriate amount of KN-type impurity into the portion in contact with the gate oxide film (to) of 40a) and making this portion a P-type semiconductor region with a low impurity concentration, a memory element that operates at a low voltage can be obtained, and By introducing the above-mentioned N-type impurity into the portion G11 of the P-type conductive substrate α0 that is in contact with the gate oxide film 1, the effective channel length of the transformer 7 agate can be reduced and high-speed operation can also be made possible. can.

Here, when the N-type impurity is introduced, it becomes an impurity, and the area of the PN junction decreases, which is undesirable.

Therefore, in the above embodiment, by using the implantation method, that is, the ion implantation method, the N-type impurity penetrates shallowly, thereby preventing the reduction in the area of the PN junction as much as possible.

In the present invention, it goes without saying that a similar memory device can be obtained even if the conductivity type of each semiconductor part is set to the opposite conductivity type from that in the embodiment and the polarity of the applied voltage is reversed.

Further, each oxide film is not limited to an oxide film, and may be replaced with a nitride film or other insulating film.

As described in detail above, in the method of manufacturing a semiconductor memory device according to the present invention, the source region and the drain region of the second conductivity type are formed on one principal surface of the semiconductor substrate of the first conductivity type with a predetermined interval apart. , a gate insulating film provided in contact with one main surface of the semiconductor substrate and partially in contact with the source region and the drain region and formed so as to straddle each other; reaches the above-mentioned top surface and comes into contact with the gate oxide film, and the source region F
a conductor region of a first conductivity type having a higher impurity concentration than the semiconductor substrate constituting the source region and the PN junction; In a semiconductor memory device in which an impurity of a second conductivity type is introduced into a region where an inversion layer between the source region and a drain region is formed, the impurity of the second conductivity type is introduced by an implantation method. This method enables the memory element to operate at a low voltage, and the storage capacity that is reduced due to this low voltage operation can be reduced by using a diffusion method when introducing the impurity of the second conductivity type. This has the effect that it can be made smaller than the actual amount.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal cross-sectional view of a memory element of a conventional semiconductor memory device.
#c2 is a vertical cross-sectional view of a memory element of another conventional semiconductor memory device, FIG. 3 is a vertical cross-sectional view of a memory element of yet another conventional semiconductor memory device, and FIGS. 4 and 5 are each a cross-sectional view of a memory element of another conventional semiconductor memory device. FIG. 2 is a vertical cross-sectional view of a memory element of a first and second example. In the figure, αG is a P-type semiconductor substrate (first conductivity type semiconductor substrate), (41, (40a) is a P-type≠conductor region (first conductivity type semiconductor region), - is a source region, N
The top of the conductor (the first semiconductor region of the second conductivity type) is the drain region of the N-type semiconductor region (the second second conductivity type ≠
1 is a gate oxide film (gate@edge film). Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] (1) a source region and a drain region of a second conductivity type formed at a predetermined interval on one principal surface of the semiconductor substrate of the first conductivity type; and a source region and a drain region provided in contact with one principal surface of the semiconductor substrate; and a gate insulating film formed so as to partially contact the drain region and straddle each other, and reach the one main surface on the source region side within the predetermined interval and contact the gate oxide film, and the source region a semiconductor region of a first conductivity type that is provided below and has a higher impurity concentration than the semiconductor substrate forming a PN junction with the source region, and is a portion of the semiconductor region in contact with the gate insulating film. In a semiconductor memory device in which an impurity of a second conductivity type is introduced into a region where an inversion layer between the source region and a drain region is formed, the impurity of the second conductivity type is introduced by an implantation method. A method for manufacturing a semiconductor memory device, characterized by: