JPS5847863B2 - field effect transistor - Google Patents
field effect transistorInfo
- Publication number
- JPS5847863B2 JPS5847863B2 JP56006590A JP659081A JPS5847863B2 JP S5847863 B2 JPS5847863 B2 JP S5847863B2 JP 56006590 A JP56006590 A JP 56006590A JP 659081 A JP659081 A JP 659081A JP S5847863 B2 JPS5847863 B2 JP S5847863B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- layer
- semiconductor region
- region
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005669 field effect Effects 0.000 title claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 89
- 239000000463 material Substances 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 230000010287 polarization Effects 0.000 description 14
- 239000000758 substrate Substances 0.000 description 14
- 230000006870 function Effects 0.000 description 9
- 229920006395 saturated elastomer Polymers 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- LWIHDJKSTIGBAC-UHFFFAOYSA-K tripotassium phosphate Chemical compound [K+].[K+].[K+].[O-]P([O-])([O-])=O LWIHDJKSTIGBAC-UHFFFAOYSA-K 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910000160 potassium phosphate Inorganic materials 0.000 description 1
- 235000011009 potassium phosphates Nutrition 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 229910000859 α-Fe Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】 本発明は電界効果トランジスタに関する。[Detailed description of the invention] The present invention relates to field effect transistors.
電界効果トランジスタとして従来接合型のものと絶縁ゲ
ート型のものとが存するが、倒れもスイッチング素子と
しての機能を有しても記憶素子としての機能を有しない
を普通としていた。There are conventional field effect transistors of junction type and insulated gate type, but they usually have a function as a switching element but not a memory element.
但し特殊な絶縁ゲート型電界効果トランジスタとしてス
イッチング素子としての機能と記憶素子としての機能と
を有するものが存するも、その特殊な絶縁ゲート型電界
効果トランジスタの場合、スイッチング素子としての機
能と記憶素子としての機能との双方を併用し得るもので
ないを普通としていた。However, there are special insulated gate field effect transistors that have the functions of both a switching element and a memory element; Normally, it was not possible to use both functions together.
この為従来の電界効果トランジスタの場合、それを用い
て記憶素子としての機能とスイッチング素子としての機
能との双方を併用する必要のある記憶回路を構成とする
とき、その電界効果トランジスタを少くとも２個要し、
依って斯く電界効果トランジスタを用いて記憶回路を構
成するとき、その記憶回路を小型化するに一定の限度を
有していたと共に記憶回路への情報の書込み又それより
の読出しの速度を高速化すること及び記憶回路への情報
の書込み乃至書換えに必要な電圧を低電圧化することに
一定の限度を有していた等の欠点を有していた。For this reason, in the case of conventional field effect transistors, when using them to configure a memory circuit that requires both the function of a memory element and the function of a switching element, the field effect transistor must be used at least two times. Individually required,
Therefore, when constructing a memory circuit using field-effect transistors, there are certain limits to how small the memory circuit can be made to be, and at the same time, it is difficult to increase the speed at which information can be written to or read from the memory circuit. This method has drawbacks such as a certain limit in reducing the voltage required to write or rewrite information to a memory circuit.
依って本発明は上述せる欠点のない、従って記憶回路を
構成するに適用して好適な新規な電界効果トランジスタ
を提案せんとするもので、以下図面を伴なって詳述する
所より明らかとなるであろつ０
第１図〜第３図は本発明による電界効果トランジスタの
実施例を示し、例えばＰ型の例えはシリコンでなる半導
体基板本体１とその主面上に例えはエビタキシャル威長
法によって形或されたＰ型の例えばシリコンでなる半導
体層２とよりなる基板３を有し、その半導体基板３内に
その半導体層２側の主面４側より、半導体層２による島
状の半導体層５と同様に半導体層２による島状の半導体
領域（但しこの半導体領域は、それが半導体層２による
ものであるので、Ｐ型でなければならないが、その半導
体領域が、実施例としてではあるが後述する如くにその
半導体領域内にその全域に亘ってＮ十型の半導体領域１
３が形威されてなる態様を有するので、へ 型の半導体
領域１３として示されている）とを形威すべく例えばシ
リコン酸化物でなる絶縁層６が半導体基板本体１に達す
る深さで形或され、而して半導体層５内に主面４側より
Ｐ＋型の半導体領域７及び８が、それ等間に半導体層５
による半導体領域９をチャンネル領域として形成すべく
、夫々ソース領域及びドレイン領域として、Ｐ型不純物
の拡散処理、Ｐ型不純物イオンの打込処理等のそれ自体
は公知の種々の方法によって形成されている。Therefore, the present invention aims to propose a novel field effect transistor that does not have the above-mentioned drawbacks and is therefore suitable for use in configuring a memory circuit, as will become clear from the detailed description below with reference to the drawings. 1 to 3 show an embodiment of a field effect transistor according to the present invention. It has a substrate 3 consisting of a P-type semiconductor layer 2 made of silicon, for example, formed by a semiconductor substrate 3, and an island-shaped semiconductor formed by the semiconductor layer 2 is formed in the semiconductor substrate 3 from the main surface 4 side on the semiconductor layer 2 side. Similarly to layer 5, an island-shaped semiconductor region formed by semiconductor layer 2 (however, since this semiconductor region is formed by semiconductor layer 2, it must be of P type; As will be described later, an N0 type semiconductor region 1 is formed throughout the semiconductor region.
3, the insulating layer 6 made of, for example, silicon oxide is shaped to a depth that reaches the semiconductor substrate body 1 to form a F-shaped semiconductor region 13). P+ type semiconductor regions 7 and 8 are formed in the semiconductor layer 5 from the main surface 4 side, and the semiconductor layer 5 is formed between them.
In order to form the semiconductor region 9 as a channel region, a source region and a drain region are formed by various methods known per se, such as diffusion treatment of P-type impurities, implantation treatment of P-type impurity ions, etc. .
この場合半導体領域７及び８の側面は、それ等間の半導
体領域９を介して相対向する面側以外の面側か絶縁層６
に連接し、又半導体領域９の側面は、その半導体領域Ｉ
及び８と連接せる相対向する面側以外の面側か絶縁層６
に連接している。In this case, the side surfaces of the semiconductor regions 7 and 8 are either the side of the insulating layer 6 other than the side facing each other with the semiconductor region 9 between them.
The side surface of the semiconductor region 9 is connected to the semiconductor region I.
and the insulating layer 6 on the surface side other than the opposing surface side connected with 8
is connected to.
又チャンネル領域としての半導体領域９の主面４側の面
上に電荷蓄積性絶縁層１０を介して導電性層１１が第１
のゲート電極として配されている。Further, a first conductive layer 11 is formed on the main surface 4 side of the semiconductor region 9 as a channel region with a charge storage insulating layer 10 interposed therebetween.
It is arranged as a gate electrode.
この場合電荷蓄積性絶縁層１０は、半導体領域９及び導
電性層１１間に、導電性層１１側を正とする電圧が印加
された場合、半導体領域９との界面側を正、導電性層１
１との界面側を負とする分極が、又導電性層１１側を負
とする電圧が印加された場合、半導体領域９との界面側
を負、導電性層１１との界面側を正とする分極が得られ
る態様を以って、電荷を半導体領域９との界面側及び導
電性層１１との界面側に蓄積する性質を有すべく、チタ
ン酸バリウム、チタン酸ジリコン酸鉛、ペロプス力イト
型又はロッシエル塩形若しくはリン酸カリ形等の強誘電
体を含んで形威され、半導体領域７及び８上にも僅かに
延長し且絶縁層６上にも半導体領域９と連接せる位置に
於で僅かに延長している。In this case, when a voltage is applied between the semiconductor region 9 and the conductive layer 11 with the side of the conductive layer 11 being positive, the charge accumulating insulating layer 10 has a positive voltage on the interface side with the semiconductor region 9, and the conductive layer 1
When polarization is applied such that the interface side with the semiconductor region 9 is negative and the voltage that is negative on the conductive layer 11 side, the interface side with the semiconductor region 9 is negative and the interface side with the conductive layer 11 is positive. In order to have the property of accumulating charges at the interface side with the semiconductor region 9 and the interface side with the conductive layer 11 in a manner that allows polarization to be obtained, barium titanate, lead gyriconate titanate, and Perops force are used. It is formed of a ferroelectric material such as a ferroelectric material such as a ferrite type, a Rossiel salt type, or a potassium phosphate type, and extends slightly over the semiconductor regions 7 and 8, and is also located on the insulating layer 6 at a position where it can be connected to the semiconductor region 9. It has been slightly extended at .
又導電性層１１は、多結晶シリコン、金属層等の導電性
材で形威され、電荷蓄積性絶縁層１０上より絶縁層６上
に外方に延長している。The conductive layer 11 is made of a conductive material such as polycrystalline silicon or a metal layer, and extends outward from the charge storage insulating layer 10 to the insulating layer 6.
更に半導体基板３内に、その半導体基板本体１の半導体
領域５下の領域に於ける半導体領域５側に形或されてな
る態様を有する、導電性層１１と対向して半導体領域５
に連接せるＮ 型の半導体領域１２と、上述せる半導体
基板３の半導体層２による島状の半導体領域内にその全
域に亘って形威されてなる態様を有するＮ 型の半導体
領域１３と、半導体基板本体１の半導体領域１２及ひ１
３間の領域に於ける絶縁層６下側に側に形成されてなる
態様を有する半導体領域１２及び１３間にそれ等と連接
して延長せるＮ 型の半導体領域１４とよりなる半導体
領域１５が第２のゲーで極として形成されている。Further, in the semiconductor substrate 3, a semiconductor region 5 is formed opposite to the conductive layer 11, which is formed on the semiconductor region 5 side in a region below the semiconductor region 5 of the semiconductor substrate body 1.
an N-type semiconductor region 12 connected to the semiconductor substrate 3; Semiconductor regions 12 and 1 of substrate body 1
Between the semiconductor regions 12 and 13 formed below the insulating layer 6 in the region between 3 and 3, there is a semiconductor region 15 consisting of an N type semiconductor region 14 connected and extending therebetween. It is formed as a pole in the second game.
尚更に半導体基板３の主面４上に、電荷蓄積性絶縁層１
０及び導電性層１１を覆って延長し且半導体領域７、半
導体領域８、及び半導体領域１５の領域１３を外部に臨
ませる窓１７．１Ｂ、及び１９を穿設せる例えばシリコ
ン酸化物でなる絶縁層１６が形或され、而して半導体領
域７，８及び１３に、絶縁層１６上に延長せる例えば金
属でなる導電性層２０，２１，及び２２が、夫々窓１７
，１８及び１９内を通ってソース電極乃至配線層、ドレ
イン電極乃至配線層、及び第２ゲート電極乃至配線層と
して連結されている。Further, on the main surface 4 of the semiconductor substrate 3, a charge storage insulating layer 1 is provided.
An insulator made of silicon oxide, for example, in which windows 17.1B and 19 are formed, extending over the conductive layer 11 and exposing the semiconductor region 7, the semiconductor region 8, and the region 13 of the semiconductor region 15 to the outside. A layer 16 is formed such that semiconductor regions 7, 8 and 13 are provided with conductive layers 20, 21 and 22, e.g. of metal, which extend over the insulating layer 16, respectively through windows 17.
, 18 and 19 and are connected as a source electrode to a wiring layer, a drain electrode to a wiring layer, and a second gate electrode to a wiring layer.
以上が本発明による電界効果トランジスタの一例構成で
あるが、斯る構成によれば、ソース電極乃至配線層とし
ての導電性層２０及びゲート電極としての導電性層１１
間に一般に■。The above is an example of the configuration of a field effect transistor according to the present invention. According to this configuration, the conductive layer 20 as a source electrode or wiring layer and the conductive layer 11 as a gate electrode.
■ Generally between.
で表わされる電圧を印加することにより、その電圧ｖＧ
が導電性層２０側を基準として正であるか負であるかに
応じて電荷蓄積性絶縁層１０の半導体領域９との界面側
を正又は負、導電性層１１との界面側を負又は正とする
分極を形威せる態様を以って電荷蓄積性絶縁層１０に電
荷が蓄積されるものである。By applying a voltage represented by
is positive or negative with respect to the conductive layer 20 side, the interface side of the charge accumulating insulating layer 10 with the semiconductor region 9 is positive or negative, and the interface side with the conductive layer 11 is negative or negative. Charges are accumulated in the charge accumulating insulating layer 10 in a manner that produces positive polarization.
この関係は、横軸に電圧ｖＧ、縦軸に分極をとって示さ
れている第４図に示す如く、電圧ｖＧが正の値ｖ４より
大なる値である場合に於で絶縁層１０Ｋ半導体領域９と
の界面側を正（→とせる飽和状態の分極が得られている
も、斯る状態より電圧■Ｇの値を■４より小として負の
値■２より小なる値とすれば、絶縁層１０に半導体領域
９との界面側を正（ト）とせる分極が飽和状態より小と
なり、そして負の値■１より小なる値とすれば絶縁層１
０に半導体領域９との界面側を負（一）とせる飽和状態
の分極が得られ、又斯る状態より電圧■Ｇの値を■１よ
り犬として正の値■３より犬なる値とすれば、絶縁層１
０に半導体領域９との界面側を負（−）とせる分極が飽
和状態より小となり、そして正の値■４より犬なる値と
すれば、絶縁層１０に半導体領域９との界面側を正（＋
）とせる上述せる飽和状態の分極が得られるというもの
である。As shown in FIG. 4, where the horizontal axis represents the voltage vG and the vertical axis represents the polarization, this relationship applies to the insulating layer 10K semiconductor region when the voltage vG is larger than the positive value v4. Although polarization in a saturated state where the interface side with If the polarization that makes the interface side with the semiconductor region 9 of the insulating layer 10 positive (G) is smaller than the saturated state, and the negative value is smaller than 1, then the insulating layer 1
A saturated polarization is obtained in which the interface side with the semiconductor region 9 is negative (one) at 0, and from this state, the value of the voltage G becomes a positive value from 1, and a positive value from 3. Then, insulating layer 1
0, the interface side with the semiconductor region 9 becomes negative (-), and the polarization becomes smaller than the saturated state, and if the polarization is set to a value that is more dog than the positive value 4, then the interface side with the semiconductor region 9 becomes the insulating layer 10. Positive (+
), the above-mentioned saturated polarization can be obtained.
又絶縁層１０に半導体領域９との界面側を正（＋）とせ
る上述せる飽和状態が得られている場合、半導体領域９
内に絶縁層１０との界面側より拡がる空乏層が得られて
いるも、絶縁層１０に半導体領域９との界面側を負（−
）とせる上述せる飽和状態の分極が得られている場合、
半導体領域９内には実質的に上述せる空乏層は得られて
いないものである。Further, when the above-mentioned saturated state is obtained in which the interface side with the semiconductor region 9 is positive (+) in the insulating layer 10, the semiconductor region 9
Although a depletion layer that spreads from the interface side with the insulating layer 10 is obtained within the insulating layer 10, the interface side with the semiconductor region 9 is negative (-
), if the above-mentioned saturated polarization is obtained,
Substantially no depletion layer as described above is obtained in the semiconductor region 9.
又ソース電極としての導電性層２０及びゲート電極乃至
配線層としての導電性層２２間に一般にＶ′Ｇで表わさ
れる導電性層２０を基準として正である電圧を印加する
ことにより、チャンネル領域としての半導体領域５内に
それとゲート電極としての半導体領域１５とのなすＰＮ
接合２３より拡がる空乏層が得られるものである。In addition, by applying a positive voltage with respect to the conductive layer 20, which is generally expressed as V'G, between the conductive layer 20 as a source electrode and the conductive layer 22 as a gate electrode or wiring layer, a voltage can be applied as a channel region. A PN formed between the semiconductor region 5 and the semiconductor region 15 as a gate electrode is formed in the semiconductor region 5 of
A depletion layer expanding from the junction 23 is obtained.
従って導電性層２０及び１１間に、導電性層１１側を正
とせる上述せる電圧■Ｇの値■４以上の値を有する電圧
を２値表示で「０」の情報として与えれば、絶縁層１０
に半導体領域９との界面側を正とせる飽和状態の分極が
２値表示で「０」の情報を記憶せるものとして得られ、
又これより導電性層２０及び１１間に導電性層１１側を
負とせる上述せる電圧■Ｇの値■１以下の値を有する電
圧を２値表示で「１」の情報として与えれば、絶縁層１
０に半導体領域９との界面側を負とせる飽和状態の分極
が２値表示で「１」の情報を記憶せるものとして得られ
るものである。Therefore, if the above-mentioned voltage that makes the conductive layer 11 side positive - the value of G 10
A saturated polarization in which the interface side with the semiconductor region 9 is positive is obtained as a binary display that can store information of "0",
Also, from this, if the above-mentioned voltage that makes the conductive layer 11 side negative is applied between the conductive layers 20 and 11, the value of G, and the voltage having a value of 1 or less is given as information of "1" in binary representation, the insulation layer 1
A polarization in a saturated state in which the interface side with the semiconductor region 9 is negative at 0 is obtained as a binary display capable of storing information of "1".
又上述せる２値表示でｒＯＪの情報が記憶されている状
態で、導電性層２０及び２２間に、上述せる半導体領域
９内にＰＮ接合２３より拡がる空乏層が、上述せる半導
体領域９内に絶縁層１０との界面側より拡がっている空
乏層に達するに十分な値を有する導電性層２２側を負と
せる電圧又は正とせる低い電圧を与えれば、半導体領域
７及び８間の非導通状態が得られ、従ってこのことをＩ
ＯＪの情報の記憶を読出したこととし得るものである。Furthermore, in the state in which the rOJ information is stored in the binary representation described above, a depletion layer extending from the PN junction 23 into the semiconductor region 9 described above is formed between the conductive layers 20 and 22 within the semiconductor region 9 described above. Non-conduction between the semiconductor regions 7 and 8 can be achieved by applying a voltage that makes the conductive layer 22 side negative or positive, which has a value sufficient to reach the depletion layer extending from the interface side with the insulating layer 10. state is obtained, and therefore we can refer to this as I
This can be considered as reading out the information stored in the OJ.
更に上述せる２値表示で「１」の情報が記憶されている
状態で、導電性層２０及び２２間にに上述せる電圧を与
えれば、半導体領域７及び８間の領域９の表面側を通る
導通状態が得られ、従ってこのことを「１」の情報の記
憶を読出したこととし得るものである。Furthermore, if the voltage described above is applied between the conductive layers 20 and 22 in a state where the information "1" is stored in the binary display described above, the voltage passes through the surface side of the region 9 between the semiconductor regions 7 and 8. A conductive state is obtained, and this can therefore be regarded as reading out the storage of information of "1".
尚更に導電性層２０及び２２間に上述せる電圧の値より
犬にして、上述せる領域９内にＰＮ接合２３より拡がる
空乏層が領域９の表面に達するに十分な値を有する正の
電圧を与えれば、半導体領域７及び８間の非導通状態が
得られ、従ってこのことにより上述せる２値表示でｒＯ
Ｊ及び「１−１の情報の記憶の倒れをも読出さない所謂
非アクセス状態とし得るものである。Furthermore, a positive voltage having a value sufficient to cause the depletion layer extending from the PN junction 23 to reach the surface of the region 9 in the region 9 described above is applied between the conductive layers 20 and 22, which is different from the voltage value described above. If given, a non-conducting state between semiconductor regions 7 and 8 is obtained, which therefore causes rO in the binary representation mentioned above.
It is possible to create a so-called non-access state in which even information stored in J and 1-1 is not read out.
又上述せる２値表示でｒＯＪ及び「１」の情報の記憶の
何れをも、導電性層２０及び１１間に上述せる電圧■Ｇ
の値ｖ２及び■３間の値を有する電圧を与えて置けば、
又は導電性層２０及び１１間に例等電圧を与えなくても
上述せる情報の記憶状態が保持されるものである。In addition, in the above-mentioned binary display, both rOJ and "1" information storage can be performed by applying the above-mentioned voltage ■G between the conductive layers 20 and 11.
If a voltage with a value between v2 and ■3 is applied,
Alternatively, the above-mentioned information storage state can be maintained even if no voltage is applied between the conductive layers 20 and 11.
依って第１図〜第３図にて上述せる本発明による電界効
果トランジスタの場合、記憶素子としての機能とスイッ
チング素子としての機能とを有し、而してそれ等の機能
を併用し得るという犬なる特徴を有するものである。Therefore, in the case of the field effect transistor according to the present invention described above in FIGS. 1 to 3, it has a function as a memory element and a function as a switching element, and can use these functions in combination. It has the characteristics of a dog.
この為第１図〜第３図にて上述せる本発明による電界効
果トランジスタの場合、その１つを用いて記憶素子とし
ての機能とスイッチング素子としての機能との双方を併
用し得る必要のある記憶回路を構威し得、而して斯る記
憶回路を構威するとき、その記憶回路を小型化すること
が出来ると共にその記憶回路への情報の書込み又それよ
りの読出しの速度を高速化すること及び記憶回路への書
込み乃至書換えに必要な電圧を低電圧化することが出来
、依って記憶回路を構戊するに適用して極めて好適であ
るという犬なる特徴を有するものである。For this reason, in the case of the field effect transistor according to the present invention described above in FIGS. 1 to 3, it is necessary to use one of the field effect transistors to function as a memory element and as a switching element. When constructing such a memory circuit, the memory circuit can be made smaller and the speed at which information can be written to or read from the memory circuit can be increased. In addition, it is possible to reduce the voltage required for writing to or rewriting a memory circuit, and therefore, it has the characteristic that it is extremely suitable for application to constructing a memory circuit.
向上述に於では電荷蓄積性絶縁層１０が、前述せる電荷
を蓄積する性質を有すべく、強誘電体を含んで形或され
ていると述べたが、その態様は強誘電体のみを以って形
威されている態様、前述せる電荷を蓄積する性質を有し
ない例えばシリコン酸化物等の通常の絶縁材中に強誘電
体を分散せしめてなる態様、前述せる絶縁材による２つ
の層間に強誘電体による層を介挿せしめてなる態様を採
り得るものである。In the description of improvements, it has been stated that the charge accumulating insulating layer 10 is formed to include a ferroelectric material in order to have the above-described property of accumulating charges. A mode in which a ferroelectric material is dispersed in a normal insulating material such as silicon oxide, which does not have the property of accumulating electric charges, and a mode in which a ferroelectric material is dispersed in a normal insulating material such as silicon oxide, and a mode in which a ferroelectric material is dispersed between two layers of the insulating material described above. It is possible to adopt an embodiment in which a layer of ferroelectric material is interposed.
又上述に於では本発明の一例を示したに留まり、例えば
半導体基板３のＰ型の半導体基板本体１を絶縁性半導体
基板本体とすることも出来、又半導体基板３がＰ型の半
導体本体のみよりなり、それを半導体層５とせる構威と
することも出来るものである。Further, the above description merely shows an example of the present invention, and for example, the P-type semiconductor substrate body 1 of the semiconductor substrate 3 can be an insulating semiconductor substrate body, or the semiconductor substrate 3 can only be a P-type semiconductor body. It is also possible to use it as the semiconductor layer 5.
又上述に於で電荷蓄積性絶縁層１０が強誘電体を含んで
形或されている場合を述べたが、その絶縁層１０を前述
せる電荷蓄積する性質を有すべく、シリコン又はシリコ
ン窒化物若しくはアルミニウム酸化物を含んで形成する
ことも出来るものである。Further, in the above description, the case where the charge storage insulating layer 10 is formed by containing a ferroelectric material has been described, but in order for the insulating layer 10 to have the above-mentioned charge storage property, silicon or silicon nitride is used. Alternatively, it can also be formed by containing aluminum oxide.
更に上述に於ではゲート電極としての半導体領域１５の
領域１２及び電荷蓄積性絶縁層１０が正に対向関係を有
する場合につき述べたが、その対向関係が僅かにずれた
関係とすることも出来、又半導体領域５に半導体領域１
５に代え金属層を連結せしめてＰＮ接合２３に代えショ
ットキ接合を形威せる構威とすることも出来、尚更に上
述せる「Ｐ」、「Ｐ 」、及び「Ｎ＋」を夫＋
夫ｒＮＪ、ｒＮ＋Ｊ、及び「Ｐ＋」と読替えた構成とす
ることも出来、その他本発明の精神を脱することなしに
種々の変型変更をなし得るであろつ０Furthermore, although the above description has been made of the case where the region 12 of the semiconductor region 15 serving as the gate electrode and the charge storage insulating layer 10 have a exactly opposing relationship, it is also possible to have a relationship in which the opposing relationship is slightly shifted. Also, semiconductor region 1 is placed in semiconductor region 5.
It is also possible to connect metal layers instead of 5 and form a Schottky junction instead of the PN junction 23, and furthermore, the above-mentioned "P", "P", and "N+" can be connected to each other by connecting metal layers to form a Schottky junction. rN+J and "P+" may be used, and various other modifications may be made without departing from the spirit of the present invention.
【図面の簡単な説明】
第１図は本発明による電界効果トランジスタの一例を示
す平面図、第２図及び第３図はその■−■線及び■一■
線上の断面図、第４図は本発明の説明に供する電圧■Ｇ
と分極との関係を示す図である。
図中、３は半導体基板、４は主面、５は半導体層、７，
８，９及び１５は半導体領域、１０は電荷蓄積性絶縁層
、１１，２０．２１及び２２は導電性層を夫々示す。[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a plan view showing an example of a field effect transistor according to the present invention, and FIGS.
The cross-sectional view along the line, Figure 4, shows the voltage ■G used to explain the present invention.
FIG. 3 is a diagram showing the relationship between and polarization. In the figure, 3 is a semiconductor substrate, 4 is a main surface, 5 is a semiconductor layer, 7,
8, 9 and 15 are semiconductor regions, 10 is a charge storage insulating layer, and 11, 20, 21 and 22 are conductive layers, respectively.
Claims (1)
り、第１の導電型を有し且上記半導体層に比し高い不純
物濃度を有する第１及び第２の半導体領域がそれ等間に
上記半導体層による第３の半導体領域をチャンネル領域
として形威すべく夫々ソース領域及びドレイン領域とし
て形成され、上記第３の半導体領域の上記主面側の面上
に電荷蓄積性絶縁層を介して第１の導電性層が第１のゲ
ート電極として配され、上記半導体層に、第１の導電型
とは逆の第２の導電型を有する第４の半導体領域が上記
半導体層との間でＰＮ接合を形成すべく又は第２の導電
性層が上記半導体層との間でショットキ接合を形威すべ
く、第２のゲート電極として連結されてなる事を特徴と
する電界効果トランジスタ。 ２ 特許請求の範囲第１項所載の電界効果トランジスタ
に於で、上記電荷蓄積性絶縁層が強誘電体を含んで形成
されてなる事を特徴とする電界効果トランジスタ。 ３ 特許請求の範囲第１項記載の電界効果トランジスタ
に於で、上記電荷蓄積性絶縁層がシリコン又はシリコン
窒化物若しくはアルミニウム酸化物を含んで形威されて
なる事を特徴とする電界効果トランジスタ。[Scope of Claims] 1. In a semiconductor layer having a first conductivity type, first and second semiconductor layers having a first conductivity type and having a higher impurity concentration than the semiconductor layer are arranged from the main surface side thereof. semiconductor regions are formed between them as a source region and a drain region, respectively, so that the third semiconductor region of the semiconductor layer serves as a channel region, and on the surface of the third semiconductor region on the main surface side. A first conductive layer is disposed as a first gate electrode via a charge storage insulating layer, and a fourth semiconductor region having a second conductivity type opposite to the first conductivity type is provided in the semiconductor layer. is connected as a second gate electrode to form a PN junction with the semiconductor layer or a second conductive layer to form a Schottky junction with the semiconductor layer. field effect transistor. 2. A field effect transistor according to claim 1, wherein the charge storage insulating layer is formed to include a ferroelectric material. 3. The field effect transistor according to claim 1, wherein the charge storage insulating layer contains silicon, silicon nitride, or aluminum oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56006590A JPS5847863B2 (en) | 1981-01-20 | 1981-01-20 | field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56006590A JPS5847863B2 (en) | 1981-01-20 | 1981-01-20 | field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57121271A JPS57121271A (en) | 1982-07-28 |
| JPS5847863B2 true JPS5847863B2 (en) | 1983-10-25 |
Family
ID=11642540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56006590A Expired JPS5847863B2 (en) | 1981-01-20 | 1981-01-20 | field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5847863B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6352168A (en) * | 1986-08-21 | 1988-03-05 | Hitachi Koki Co Ltd | Electrophotographic developing device |
| EP3981856A1 (en) | 2020-09-30 | 2022-04-13 | Stanley Electric Co., Ltd. | Group-iii nitride semiconductor nanoparticles and production method thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005017533A1 (en) * | 2004-12-29 | 2006-07-13 | Hynix Semiconductor Inc., Ichon | Nonvolatile ferroelectric memory device e.g. ferroelectric random access memory device, has ferroelectric layer formed on floating channel layer and word line formed on ferroelectric layer |
-
1981
- 1981-01-20 JP JP56006590A patent/JPS5847863B2/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6352168A (en) * | 1986-08-21 | 1988-03-05 | Hitachi Koki Co Ltd | Electrophotographic developing device |
| EP3981856A1 (en) | 2020-09-30 | 2022-04-13 | Stanley Electric Co., Ltd. | Group-iii nitride semiconductor nanoparticles and production method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57121271A (en) | 1982-07-28 |
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