JPS5910263A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to improve the integration degree by a method wherein the occupation area of one transistor type memory cell composed of an MIS capacity element as a memory means and an MISFET as a switching means for write and read-out purposes is reduced. CONSTITUTION:An SiO2 film 2 serving as a field insulation film is formed on a semiconductor substrate 1 and selectively removed, and thereafter a thin SiO2 film 2' serving as a gate insulation film is formed. Of this SiO2 film 2', the common region of the switching MISFET, e.g., semiconductor region which is to form a common source is selectively removed. Next, polycrystalline Si layers 3 are formed selectively at the parts serving as the gate electrode and bit line of the MIS capacitor. The polycrystalline Si layers 3 are changed into conductors, the source region 4 of the MISFET is diffusion-formed by heat treatment, and a polycrystalline Si thermal oxide film 3'' having insulation property is formed on the surfaces of the conductive polycrystalline Si layers 3'. Thereafter, the gate electrodes 5 of the MISFET of the conductive polycrystalline Si layers are so formed selectively as to overlap on the gate electrodes 3' and the source region 4 of the MIS capacity element via the thermal oxide film 3''.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrode structure of a semiconductor device, particularly an MIS (Met
al-Insulator-8emiconduc
This invention relates to a technique that is effective when applied to a one-transistor (TR8) type memory cell consisting of a capacitive element and a switching MISFET (insulated gate field effect transistor).

The 1TR8 type memory cell is composed of an MIs capacitive element as a storage means and a MISFET as a switching means for writing and reading. Since this memory cell is constituted by a semiconductor integrated circuit, it is desirable to reduce the area occupied by the memory cell and achieve the same degree of integration.

An object of the present invention is to provide an electrode structure that is effective when applied to an ITR8 type memory cell or the like.

The basic structure of the present invention for achieving the above object is as follows:
a semiconductor region of a conductivity type different from the first conductivity type formed on a first portion of a surface of a semiconductor substrate of a conductivity type; a first conductor layer formed on the semiconductor region in contact therewith; and the semiconductor substrate. a second conductive layer formed on a second portion of the surface with an insulating film interposed therebetween; and a second conductive layer formed on a third portion sandwiched between the first portion and the second portion with an insulating film interposed therebetween. 3
It is characterized by comprising a conductor layer.

EMBODIMENT OF THE INVENTION Hereinafter, one invention will be specifically explained with reference to drawings along with an Example.

FIGS. 1(a) to 2(e) and 2 are sectional views of the manufacturing process for explaining the present invention in detail. In the present invention, in order to reduce the cell area of the 1TR8 type memory cell, a MISFET utilizing the principle of CCD (charge coupled device) is used as a switching element. Specifically, a memory cell is formed by the manufacturing process shown in the figure.

(a) A 5in2 film 2 serving as a field insulating film is formed on an n-type semiconductor substrate 1.

(b) Selectively remove the S io2 film 2 on the semiconductor region where the switching MISFET and MIS capacitive element are to be formed, and then remove the thin S + film that will become the gate insulating film.
02 film 2' is formed.

(c) Of the above Sin and film 2', a common region of switching MISFETs formed facing each other, for example, a 5in2 film 2' on a semiconductor region where a common source (region to be connected to a bit line) is to be formed. selectively remove.

(d) A polycrystalline silicon layer 3 is selectively formed on the surface of the substrate at the portions that are to become the gate electrodes and bit lines of the MIS capacitor. At this time, the polycrystalline silicon layer 3 that is to become a bit line is directly connected to the surface of the substrate 1 in a portion that is to become a source region of the switching MISFET.

(e) Depositing a semiconductor impurity (for example, boron) to make the polycrystalline silicon layer 3 conductive. Next, by heat treatment, the source region 4 of the MISFET is diffused and an insulating polycrystalline silicon thermal oxide film 3'' is formed on the surface of the conductive polycrystalline silicon 3'.

Thereafter, as shown in FIG. 2, the gate electrode 5 of the MISFET made of the same conductive polycrystalline silicon layer is connected to the gate electrode 3' of the MIS capacitive element through the polycrystalline silicon thermal oxide film 3''. It is selectively formed so as to overlap the source region 4. Next, an aluminum wiring layer constituting the word line is formed so as to be connected to the gate of the MISFET, and a PSG film for surface protection is formed (Fig. Note that this figure shows a cross-sectional view of a memory cell for 2 bits.

In the lTR8 type memory cell explained above, 1Ml
A predetermined power supply voltage is always applied to the gate electrode constituting the capacitive element 5, and the semiconductor region directly under the gate electrode is made into a depletion layer.

Therefore, as in the present invention, switching MISFET
Even if one region, for example, the drain (region to be connected to the MIS capacitive element) is omitted, the distance between the gate electrode of the MIS capacitive element and the gate electrode of the MISFET is 100 OX to 200 OX, which is the film thickness of the insulating film. Because the distance is only about OA, the spread of the depletion layer due to both gate electrodes overlaps with each other, so carriers can be transferred even without the drain region, and the gate electrodes function as a switching element. This can be easily understood from the fact that it is similar to the operating principle of a CCD (charge coupled device). That is, according to the present invention, by controlling the thickness of the insulating film, it is possible to easily provide a function as a memory cell.

From the above, the pattern of the memory cell according to the present invention is such that the gate electrode of the MIS capacitive element and the gate voltage of the MISFET are formed in separate steps, so that the gate electrodes overlap each other as shown in FIG. Thus, the drain region of the switching MISFET can be omitted. therefore,
This is clearly compared to the conventional memory cell in which the gate electrode 3' of the MIS capacitive element and the gate electrode 5 of the MISFET are formed by patterning a single conductive polycrystalline silicon layer as shown in FIG. The area it occupies can be reduced. In addition, in Fig. 3.

Reference numeral 6 denotes a word line made of aluminum wiring, and CI and C2 are connection points between the word line and the gate electrode of the MISFET. Further, in FIG. 4, the bit line is made up of a diffusion layer, whereas, as shown in FIG. 3, the bit line according to the present invention is made up of a conductive polycrystalline silicon layer. For this reason, the parasitic capacitance of the bit line can be reduced, which is clear from the following equation (1), where C8 is the capacitance value of the MIS capacitive element,
CD is the capacitance value of the parasitic capacitance of the bit line, and Q is the amount of accumulated charge. As a result, the number of memory cells that can be connected to one bit line can be increased, so that together with the above-described improvement in the degree of integration, a large storage capacity can be achieved.

The present invention is not limited to the above embodiments, but can take various embodiments.

For example, an aluminum vapor deposition layer may be used as the electrode of the MISFET. Further, the bit line may be formed of a diffusion layer, but in this case, care must be taken that the parasitic capacitance increases as described above.

Furthermore, in FIG. 3, the word line 6 may be formed of a conductive polycrystalline silicon layer in the vertical direction, and the bit line 3' may be formed of an aluminum wiring in the horizontal direction.

Also, MISFET is an n-channel MIS
It goes without saying that an FET may also be used.

[Brief explanation of drawings]

1(a) to (el) and FIG. 2 show an example of a cross-sectional view of the manufacturing process of a semiconductor memory device according to the present invention, FIG. 3 shows a plan view thereof, and FIG. 4 shows a conventional lTR8 type memory device.・
An example of a plan view of a cell is shown. 1... Substrate, 2. i...5in2 film, 3...polycrystalline silicon layer, 3'...conductive polycrystalline silicon layer,!
... Polycrystalline silicon thermal oxide film, 4... Source, 4'
···drain. 5... Gate electrode (conductive polycrystalline silicon layer), 6.
...Word line (aluminum wiring layer). Figure 1 Figure 4rr Figure 2

Claims (1)

[Claims] 1. A semiconductor region of a conductivity type different from the first conductivity type formed on a first portion of the surface of the semiconductor substrate of the first conductivity type; and a first conductor layer formed on the semiconductor region in contact with the semiconductor region. , a second conductor layer formed on a second portion of the semiconductor substrate surface with an insulating film interposed therebetween; and a third portion sandwiched between the first portion and the second portion with an insulating film interposed therebetween. A semiconductor device comprising: a third conductor layer formed thereon.