JPS59210663A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the area of one transistor type memory cell consisting of a MIS capacitance element and a switching MISFET, and to improve the degree of integration by extending a word line in the same direction as the channel width of the MISFET formed under a gate electrode constituting the memory cell and unifying the gate electrode and the word line. CONSTITUTION:A thick field insulating film 2 is formed to the peripheral section of an n<-> type semiconductor substrate 1, the surface of the substrate 1 surrounded by the insulating film 2 is coated with a thin gate oxide film 2', and an opening is bored made correspond to a source region in a switching MISFET connected to a bit line. Polycrystalline Si films 3 containing a p type impurity are deposited in the opening directly and on other regions through the film 2', a p<+> type source region 4 is formed in the opening through heat treatment, and a gate electrode 3' for an MIS capacitance element is shaped on the source region 4. The films 3' composed of the polycrystalline Si films 3 on the film 2' are surrounded by an SiO2 film 3'', and gate electrodes 5 for the MISFET overlapped between the film 3'' and the electrode 3' are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor memory devices, and particularly to MIS (Met
al-I n5ulator-&m1conduc
tor) capacitive element and switching MI 5FET (
The target is a one-transistor (TR8) type memory cell consisting of an insulated gate field effect transistor).

US Pat. No. 3,387,286 is a patent related to the lTR3 type memory cell.

The 1TR8W memory cell is composed of an MIs capacitive element as a storage means and an MI 5FET as a switching means for writing and reading. Since this memory cell is constructed from a semiconductor integrated circuit, it is desirable to reduce the area occupied by the memory cell and improve the degree of integration.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory device in which the cell area of an ITR8 type memory cell is reduced to improve the degree of integration.

The gist of the present invention to achieve the above object is to provide a common semiconductor region selectively formed in a semiconductor substrate, which extends adjacent to two opposing ends of a common semiconductor region of conductivity type opposite to that of the substrate. a pair of adjacent memory cells formed to sandwich the common semiconductor region in a memory cell formation region of a semiconductor substrate, each memory cell having a channel at the end of the common semiconductor region; A switching MISFET gate electrode formed covering a part of the memory cell formation region adjacent to the end of the common semiconductor region so as to define the width direction; and a capacitive element formed in another portion of the memory cell formation region on the opposite side, the semiconductor memory device comprising: a pair of word lines each extending in a direction parallel to the two ends and electrically connected to the gate electrodes of the pair of memory cells; A semiconductor memory device comprising a bit line extending in a direction crossing the word line and made of a material different from that of the word line.

In explaining the present invention in detail, a semiconductor memory device previously studied by the present inventor will be explained with reference to FIGS.

FIGS. 1(a) to 2(e) and 2 are sectional views illustrating the manufacturing process of a memory device previously studied by the present inventor. In this memory device, ITR8 type memory
MISF uses the principle of CCD (charge coupled device) as a switching element to reduce the cell area of the cell.
It uses ET.

Specifically, a memory cell is formed by the manufacturing process shown in the figure.

(a) A 5i02 film 2 to be a field insulating film is formed on an n-type semiconductor substrate 1.

(b) Selectively remove the Sin film 2 on the semiconductor region where the switching MI 5FET and MIS capacitive element are to be formed, and then remove the thin Sin film 2 that will become the gate insulating film.
, to form a film 2'.

(c) Of the Sio film 2', the 5in2 film 2' on the semiconductor region where the source of the switching MISFET (region to be connected to the bit line) is to be formed is selectively removed.

(d) Polycrystalline silicon layer 3 is applied to the MIS on the surface of the substrate.
It is selectively formed in portions that are to become the capacitor gate electrode and bit line. At this time, the polycrystalline silicon layer 3 that is to become a bit line is directly connected to the surface of the substrate 1 at a portion that is to become a source region of the switching MI 5FET.

(e) Depositing a semiconductor impurity (for example, boron) to make the polycrystalline silicon layer 3 conductive. Next, by heat treatment, the source region 4 of the MI 5FET is diffused and an insulating polycrystalline silicon thermal oxide film 3'' is formed on the surface of the conductive polycrystalline silicon 3'.

Thereafter, as shown in FIG. 2, the gate electrode 5 of the MISFET made of the same conductive polycrystalline silicon layer is connected to the gate electrode 3' of the MIS capacitive element through the polycrystalline silicon thermal oxide film 3''. It is selectively formed so as to overlamp the source region 4. Next, at this time, an aluminum wiring layer constituting the word line is formed on the MI 5F.
It is formed so as to be connected to the gate of ET, and a PSG film for surface protection is formed (not shown). Note that this figure shows a cross-sectional view of a memory cell for 2 bits.

In the ITR8 type memory cell explained above, MI
A predetermined power supply voltage is always applied to the gate electrode constituting the S capacitive element, and the semiconductor region directly under the gate electrode is made into a depletion layer.

Therefore, switching MI as in this memory device
Even if the SFET drain (region to be connected to the MIS capacitive element) is omitted, the distance between the gate electrode of the MIS capacitive element and the gate electrode of the MI 5FET is about 100 A to 2000 A, which is the thickness of the insulating film. Since the depletion layers of both gate electrodes overlap each other due to the fact that the two gate electrodes are separated by only It can be easily understood that the operating principle is similar to that of a coupling element (coupling element).For this reason, the distance between the gate electrode of the MIS capacitive element and the gate electrode of the MISFET may be small (within 3 μm).

From the above, the pattern diagram of the memory cells of this memory device is as shown in FIG.
Since the drain region of the ET can be omitted, the area occupied by the ET can be clearly reduced compared to a conventional memory cell as shown in FIG. In addition, in FIG. 3, 6 is a word line composed of aluminum wiring,
C, , C2 are connection points between the word line and the gate electrode of the MISFET. Furthermore, in FIG. 4, the bit line is composed of a diffusion layer, whereas the bit line is composed of a diffusion layer.
As shown in the figure, the bit line according to the present invention is constructed of a conductive polycrystalline silicon layer. Therefore, the parasitic capacitance of the bit line can be reduced, so that the output detection level Δ■ can be increased as is clear from the following equation (1).

Here, C8 is the capacitance value of the MIS capacitive element, CD is the capacitance value of the parasitic capacitance of the bit line, and Q is the amount of accumulated charge. As a result, the number of memory cells that can be connected to one bit line can be increased, so that together with the above-described improvement in the degree of integration, a large storage capacity can be achieved.

The present invention is a further modification of the above-described memory device, and in FIG. 3, the word line 6 is formed vertically by a conductive polycrystalline silicon layer, and the bit line 3' is formed horizontally by an aluminum wiring. It consists of

According to the layout of the present invention, the word line is
MI formed under the gate electrode that constitutes the memory cell
Since it can extend in the same direction as the channel width of the SFET, the gate electrode constituting the memory cell can be formed integrally with the word line. As a result, the connection point (contact region) between the word line and the gate electrode portion can be omitted, and the area occupied by the memory device can be reduced. Since the bit line extends over the semiconductor substrate via the insulating film as described above, the semiconductor region constituting the memory cell can be locally formed and electrically connected to the bit line. Therefore, as described above, the parasitic capacitance of the bit line can be reduced.

It goes without saying that in the above embodiments, the MISFET may be an n-channel MI 5FET.

[Brief explanation of the drawing]

1(a) to (e) and FIG. 2 show an example of a cross-sectional view of the manufacturing process of a semiconductor memory device for explaining the present invention, FIG. 3 shows a plan view thereof, and FIG. 4 shows a conventional lTR8
1 shows an example of a top view of a type memory cell. DESCRIPTION OF SYMBOLS 1...Substrate, 2.2'...Sin, film, 3...Polycrystalline silicon layer, 3'...Conductive polycrystalline silicon layer,
3"...Polycrystalline silicon thermal oxide film, 4 peak source, 4'
...Drain, 5... Gate electrode (conductive polycrystalline silicon layer), 6... Word line (aluminum wiring layer). Figure 1 Figure 4 (Pυ Figure 2 Figure 3

Claims (1)

[Scope of Claims] A memory cell formation region of a semiconductor substrate extending adjacent to two opposing ends of a common semiconductor region of a conductivity type opposite to that of the substrate selectively formed on the semiconductor substrate. ,
a pair of adjacent memory cells formed to sandwich the common semiconductor region, each memory cell comprising:
a switching MISFET gate electrode formed covering a part of a memory cell formation region adjacent to the end of the common semiconductor region so as to define a channel width direction at the end of the common semiconductor region; and a capacitive element formed in another part of the memory cell formation region on the side opposite to the end of the common semiconductor region with respect to the gate electrode, the semiconductor memory device comprising: The device extends in a direction parallel to the two ends of the common semiconductor region, and includes the pair of memory devices.
A pair of word lines electrically connected to the gate electrodes of the cells, and a word line electrically connected to the common semiconductor region and extending in a direction crossing the pair of word lines, which are different from each other. 1. A semiconductor memory device comprising a bit line made of a material.