JPH0328828B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor memory device employing a multilayer aluminum wiring structure.

Conventionally, a memory cell of a dynamic memory using an insulated gate transistor generally has a cross-sectional structure as shown in FIG. That is, information on the digit wiring 111 is controlled by the gate electrode 108 and is accumulated or released near the interface between the insulating film 103 located below the capacitive gate 105 and the impurity diffusion layer region 104 formed in the silicon substrate 101. Ru. At this time, the information storage retention ability depends on the capacitance between the capacitive gate 105 and the impurity diffusion region 104. Therefore, as device circuits become more highly integrated, a decrease in cell capacity due to a decrease in memory cell area becomes a problem. In order to compensate for this, it is necessary to reduce the thickness of the insulating film 103. However, there are problems with electrical stability and breakdown voltage, and there are limits to how thin the film can be made. In addition, in Figure 1, 1
02 is a field oxide film, 106 and 110 are insulating layers, 107 is a gate oxide film, and 109 is an impurity diffusion region that becomes one of the source and drain regions of the transistor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device having a highly reliable dynamic random access memory that is highly integrated, has a high capacitance value, and is capable of high-speed operation.

The present invention is characterized by a first impurity diffusion region provided approximately in the center of an element formation region adjacent to a field insulation film of a semiconductor substrate, and a first impurity diffusion region provided in contact with the field insulation film at both ends of the element formation region. a first gate electrode provided between the first and second impurity diffusion regions; and a first gate electrode provided between the first and third impurity diffusion regions. an insulating layer provided to entirely cover the field insulating film, the first and second gate electrodes, and the first to third impurity diffusion regions;
A digit wiring made of a first layer of aluminum is connected to the first impurity diffusion region through an opening formed in the insulating layer, and a digit wiring is connected to the second impurity diffusion region through an opening formed in the insulating layer. a first capacitor electrode made of aluminum of the first layer, which is connected and extends on the insulating layer from above the first gate electrode to above the field insulating film; and an opening formed in the insulating layer. a second capacitor electrode made of aluminum of the first layer, connected to the third impurity diffusion region through the hole and extending over the insulating layer from above the second gate electrode to above the field insulating film; , a first nitride film deposited on the top and side surfaces of the digit wiring and the first and second capacitor electrodes;
first and second openings formed in the first nitride film to respectively expose predetermined portions of the first and second capacitor electrodes on the field insulating film; a third capacitor electrode made of a second layer of aluminum extending on the first nitride film between the openings of the second layer; a second nitride film, and a third layer connected to the first capacitor electrode through the first opening formed in the first nitride film and extending toward the center on the second nitride film. a fourth capacitor electrode made of aluminum; and a second capacitor electrode formed on the first nitride film.
a fifth capacitor electrode made of aluminum of the third layer, connected to the second capacitor electrode through an opening of the third layer, and extending toward the center on the second nitride film; a capacitive electrode, the third capacitive electrode and the first nitride film sandwiched therebetween; the fourth capacitive electrode, the third capacitive electrode and the second nitride film sandwiched therebetween; The capacitor of the first dynamic random access memory is constructed from the film portion, and the second capacitor electrode, the third capacitor electrode, the first nitride film portion sandwiched therebetween, and the fifth In the semiconductor integrated circuit device, a capacitor of a second dynamic random access memory is constructed from a capacitor electrode, a third capacitor electrode, and a portion of the second nitride film sandwiched therebetween.

As described above, in the present invention, a capacitor is formed on a transistor, and the capacitor has a multi-stage structure using the first and second nitride films, so that the capacitor has a high degree of integration and a high capacitance value. Furthermore, since the digit line and all capacitor electrodes have a three-layer aluminum structure, high-speed operation is possible. Furthermore, the top and side surfaces of the first and second aluminum digit wires and the first to third capacitor electrodes are coated with a nitride film that provides stability, resulting in a highly reliable device.

A technique related to the present invention will be explained with reference to FIG. A field oxide film 202 and a gate oxide film 203 are grown on a P-type silicon substrate 201 by a conventional method, and a gate electrode 204 and N-type impurity diffusion regions 205 are formed at three locations. At this time, the steps of forming the capacitor insulating layer 103, the impurity diffusion layer 104 for increasing the capacitance, the capacitor gate polycrystalline silicon layer 105, and the insulating layer 106 in the conventional method shown in FIG. 1 become unnecessary. Next, a vapor-phase phosphorus glass layer 206 is grown to a thickness of 1.0 μm as an insulating film, and an opening is provided to connect the first aluminum layer and the impurity diffusion region. Next, first aluminum is deposited to a thickness of 1.0 μm to form a digit line 207 and a capacitor electrode 208 as well as other main wirings. Next, plasma vapor phase grown nitride films 209a and 209b are grown to a thickness of 0.1 μm, and subsequently a vapor phase grown phosphorus glass layer 210 is grown to a thickness of 1.0 μm. Then, the phosphorus glass layer 210 located above the capacitor electrode 208 is removed to expose the nitride film 209b. After that, the second aluminum
A capacitor gate 211 is formed by vapor deposition to a thickness of 1.0 μm, and other main wirings are also formed at the same time.

Therefore, in FIG. 2, a capacitor is formed by the nitride film 209b sandwiched between the first aluminum layer 208 and the second aluminum layer 211.

An embodiment of the invention is shown in FIG.

A field oxide film 302 is formed on a P-type silicon substrate 301, a gate oxide film 304 is formed at two locations in the element formation region between them, and a gate electrode 305 is formed on each gate oxide film. N-type impurity diffusion regions (source, drain) 303 are formed in the semiconductor substrate between both gate electrodes and between each gate electrode and the field oxide film. A vapor-phase phosphorus glass layer 306 is grown to a thickness of 1.0 .mu.m as an insulating film over the entire structure, and openings are provided for connecting the first aluminum layer and the impurity diffusion region. Next, a first layer of aluminum is deposited to a thickness of 1.0 μm, and a digit line 307, first and second capacitor electrodes 308, and other main wiring (not shown) are simultaneously formed. Next, the first plasma vapor phase grown nitride film 30
9a and 309b are grown to a thickness of 0.1 μm, and subsequently, a vapor phase grown phosphorus glass layer 310 is grown to a thickness of 1.0 μm. Then, the phosphor glass layer 310 located above the first and second capacitor electrodes 308 is removed to expose the respective first nitride films 309b. Thereafter, a second layer of aluminum is deposited to a thickness of 1.0 μm to form the third capacitor electrode 311 simultaneously with other main wiring (not shown). This second aluminum layer 31
1 does not entirely cover the first aluminum layer 308, and the fourth and fifth capacitor electrodes 31 are made of the first aluminum layer 308 and the third aluminum layer.
Remove each part to connect 3. After that, plasma vapor phase grown nitride films 312a, 312
b is grown to a thickness of 0.1 μm, and the first aluminum layer 308
An opening is provided to connect the third aluminum layer 313 and the third aluminum layer 313, and a third layer of aluminum is deposited to a thickness of 1.0 μm to form the fourth and fifth capacitor electrodes 313. Therefore, in this embodiment, the nitride film 309b between the first aluminum layer 308 and the second aluminum layer 311, the second aluminum layer 311 and the third aluminum layer 31 shown in FIG.
A capacitor is formed by the nitride film 312b between the capacitor 3 and the nitride film 312b. It is also possible to increase the capacitance area by increasing the number of aluminum layers in the embodiment shown in FIG. 3 to four or more.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the prior art. FIG. 2 is a sectional view showing technology related to the present invention. FIG. 3 is a sectional view showing an embodiment of the present invention. In the figure, 101 is a silicon substrate, 10
2 is a field oxide film, 103 is a capacitive oxide film, 1
04 is a high capacity impurity diffusion layer, 105 is a capacitive gate polycrystalline silicon layer, 106 is an insulating oxide film, 10
7 is a gate oxide film, 108 is a gate polycrystalline silicon layer, 109 is an impurity diffusion layer, 110 is a vapor phase grown phosphorus glass layer, 111 is an aluminum wiring layer, 2
01, 301 is a silicon substrate, 202, 302 is a field oxide film, 203, 304 is a gate oxide film, 204, 305 is a gate polycrystalline silicon layer,
205, 303 are impurity diffusion layers, 206, 306
is a vapor phase grown phosphorus glass layer, 207, 307 is the first
Digit wire with layered aluminum, 20
5, 305 is the first layer of aluminum capacitor electrode, 209a, 209b, 309a, 309b
is a plasma vapor phase grown nitride film, of which 209b and 309b (shaded areas) are capacitive parts, 210, 31
0 is a vapor phase grown phosphorus glass layer, 211, 311 is a capacitive electrode made of second layer aluminum, 312
312b is a plasma vapor grown nitride film, of which 312b (shaded area) is a capacitive part, and 313 is a capacitive electrode made of third layer aluminum.

Claims (1)

[Claims] 1. A first impurity diffusion region provided almost at the center of an element formation region adjacent to a field insulating film of a semiconductor substrate, and a second impurity diffusion region provided at both ends of the element formation region in contact with the field insulating film, respectively. a third impurity diffusion region, a first gate electrode provided between the first and second impurity diffusion regions, and a second gate electrode provided between the first and third impurity diffusion regions. a gate electrode, an insulating layer provided to entirely cover the field insulating film, the first and second gate electrodes, and the first to third impurity diffusion regions; and an opening formed in the insulating layer. A digit wiring made of a first layer of aluminum is connected to the first impurity diffusion region through a hole, and a digit wiring is connected to the second impurity diffusion region through an opening formed in the insulating layer and extends over the insulating layer. a first capacitor electrode made of aluminum of the first layer extending from above the first gate electrode to above the field insulating film; and the third impurity diffused through an opening formed in the insulating layer. the second region and on the insulating layer.
a second capacitor electrode made of the first layer of aluminum extending from above the gate electrode to the field insulating film, and the top and side surfaces of the digit wiring and the first and second capacitor electrodes. first and second openings formed in the first nitride film to respectively expose predetermined portions of the first and second capacitor electrodes on the first nitride film and the field insulating film; and,
a third capacitor electrode made of a second layer of aluminum extending on the first nitride film between the first and second openings, and deposited on the top and side surfaces of the third capacitor electrode. a second nitride film provided as a
A fourth layer made of aluminum as a third layer is connected to the first capacitor electrode through the first opening formed in the first nitride film and extends toward the center on the second nitride film. and a third layer connected to the second capacitor electrode through the second opening formed in the first nitride film and extending toward the center on the second nitride film. a fifth capacitor electrode made of aluminum;
the third capacitor electrode and the first nitride film sandwiched therebetween; the fourth capacitor electrode, the third capacitor electrode, and the second capacitor electrode sandwiched therebetween; First from the nitride film part
The second capacitor electrode, the third capacitor electrode, the first nitride film sandwiched therebetween, the fifth capacitor electrode, and the fifth capacitor electrode constitute the capacitor of the dynamic random access memory. 1. A semiconductor integrated circuit device, wherein a capacitor of a second dynamic random access memory is constructed from a capacitor electrode of No. 3 and a portion of the second nitride film sandwiched therebetween.