JP2839874B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which can be miniaturized without lowering the reliability of a charge storage capacitor. 2. Description of the Related Art High integration of dynamic random access memory (dRAM) has been realized at a remarkable speed, and the current mainstream has shifted from 64 Kbits to 256 Kbits.
Mass production of M-bit dRAM has also begun. This high integration has been achieved by miniaturization of device dimensions. However, adverse effects such as a decrease in the S / N ratio and signal inversion (so-called soft error) due to α-rays become apparent due to the decrease in capacitance (capacity) associated with miniaturization, which poses a major problem in reliability. ing. For this reason, in order to increase the capacitance of the capacitor, a trench-capacitor cell (trench capacitor cell) using a trench wall dug in the substrate, or an IEE, an international electronic device meeting, or the like. Technical Digest (IEEE, Int. Electron Dev
ices Meeting Tech. Dig.) Novel high density, Stacked capacitor MOS RA by Koyanagi, Sunami, Hashimoto, and Ashikawa et al. in pp348-351, Dec (1978).
Stacked-capacitor cells (stacked-capacitor cells) with a stacked capacitance section, as discussed in the literature entitled "M" and the like, have come to be expected as an alternative to conventional planar-type capacitors. Of which
Unlike the grooved capacitor, the latter does not require the advanced technology of drilling fine grooves in the substrate, so it will attract attention as a capacitor structure when further miniaturization of elements is required in the future. Have been. FIG. 10 is a cross-sectional view of a dRAM having a conventional stacked capacitor. The manufacturing method will be described briefly. First, an oxide film 3-2 for insulating and isolating elements is selectively grown on a single crystal substrate 3-1. Next, a gate oxide film 3-3 of the transistor is grown. Polycrystalline silicon containing impurities is deposited as the gate electrode 3-4, and after processing, the diffusion layer 3 is formed by ion implantation using the gate electrode 3-4 and the isolation oxide film 3-2 as a mask. -5 and 3-6 are formed. Next, the diffusion layer 3-
A capacitor lower electrode 3-8 is formed by depositing and processing polycrystalline silicon 3-8 containing impurities on the region 6. At this time, since the capacitor lower electrode 3-8 is also formed on the gate electrode 3-4 and the inter-element isolation oxide film 3-2, the capacitor area is larger than that of a conventional flat capacitor using only a flat surface. It is possible to Note that the gate electrode 3-4 is covered with an interlayer insulating film 3-7 such as an oxide film. An oxide film or the like is formed on the capacitor lower electrode 3-8 formed as described above, to form a capacitor insulating film 3-9. By further depositing and processing a conductor thereon, a plate electrode 3-10 is formed to complete the capacitor. Further, an interlayer insulating film 3-11 is deposited thereon, a contact L3-12 is opened so that a part of the diffusion layer 3-5 of the transistor is exposed, and then a conductor layer serving as a data line is formed. Form 3-13. According to the above-described manufacturing method, it is possible to increase the capacitance of the capacitor compared to a planar type dRAM cell in which a capacitor is formed only on the substrate plane. However, in the above-mentioned conventional stacked capacitance type capacitor cell, the capacitor lower electrode 3-8 cannot be made sufficiently large for the following two reasons, and the element has a small size. The problem that the capacitance of the capacitor decreases with the increase in the size of the memory circuit has been remarkable, and it has been difficult to configure a highly integrated memory circuit. That is, first, in order to electrically connect the data line 3-13 and the diffusion layer 3-5, the contact hole 3-12 is necessary.
In addition, a margin for processing must be considered between the contact hole 3-12 and the plate electrode 3-10. for that reason,
This is because it is necessary to form the plate electrode 3-10 avoiding the contact hole 3-12 and a portion necessary for the allowance, and the area cannot be increased. Of these, the alignment margin is required to prevent the plate electrode 3-10 from being exposed when the contact hole 3-12 is formed, and as a result, the data line 3-13 and the plate electrode 3-10 from being short-circuited. No.
2.In order to improve the reliability of the capacitor, the lower electrode 3-8 of the capacitor must be completely covered with the plate electrode 3-10. Need to be smaller than the plate electrode 3-10. Therefore, for the above reason, the capacitor lower electrode 3-8
Cannot be increased, resulting in a problem that the capacitance of the capacitor is reduced. On the other hand, since the capacitor capacitance is inversely proportional to the thickness of the capacitor insulating film, a more highly integrated memory circuit is constructed using the above-mentioned conventional stacked capacitor type capacitor cell, and the capacitor insulating film is required to secure the necessary capacitor capacitance. It is also conceivable to make 3-9 thinner. However, reducing the thickness of the capacitor insulating film 3-9 is not practical because there is a problem that the reliability of the capacitor is reduced due to an increase in leakage current and the like. In contrast to the cell structure in which the data line is arranged on the stacked capacitance type capacitor, a cell structure in which the stacked capacitance type capacitor is arranged on the data line to increase the capacitance is disclosed in, for example, Japanese Utility Model Application Publication No. No. 178894 or JP-A-59-231851. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having a large capacitor capacity and capable of miniaturization. [0010] According to the present invention, a semiconductor device is provided.
A substrate and a first conductive type semiconductor surface of the semiconductor substrate.
First and second halves showing a second conductivity type formed apart from each other
A conductive region and the first region on the surface of the semiconductor substrate;
A gate insulating film located between the semiconductor device and the second semiconductor region;
And a word line formed on the gate insulating film.
A field effect transistor for switching and the first semiconductor region.
To the data line connected to the second region and the second semiconductor region.
A first capacitor electrode connected to the first capacitor;
A capacitor insulating film formed on the capacitor electrode;
A second capacitor electrode formed on the capacitor insulating film;
And a charge storage capacitor composed of
A memory cell is composed of the transistor and the storage capacitor
Semiconductor memory device, comprising: the first semiconductor region;
The second semiconductor region is an element isolation film in a first longitudinal direction.
Formed between the first and second semiconductor regions.
In a second longitudinal direction intersecting the first longitudinal direction,
A data line extending in the first semiconductor region;
Connected through a conductor layer and extends in the first longitudinal direction.
And the first capacitor electrode is connected to the second semiconductor region.
Connected via a conductor layer to the data line.
Is what it is. According to the present invention, since the capacitor electrode is located on the bit line, the capacity can be increased. Then, the data lines are bent on the word lines avoiding the contact holes so as to be crossed and extended. With such a configuration, the configuration of the cell layout is simplified, that is, the active region surrounded by the element isolation oxide film pattern is formed.
The pattern of the (region in which the switching transistor is formed) is formed in a simple rectangular shape, and the line width of the word line can be sufficiently ensured as the cell becomes finer. In addition, a data line is drawn from a diffusion layer, ie, an impurity layer (data line contact) through a self-aligned contact hole defined by a sidewall insulating film, and a conductive layer formed in the contact hole is formed. Has been done through. For this reason, along with the miniaturization of the contact hole, the conductor layer plays a role of alleviating the step difference of the data line contact, and has an effect of preventing the data line from being disconnected. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In one embodiment of the present invention, a plate electrode (FIG. 10, 3-1) which became a problem in the conventional stacked type capacitor cell was used.
0), contact holes (Fig. 10, 3-12) and plate electrodes (Fig. 1
(3, 13-13) The structure is such that there is no need for machining allowance with the lower electrode of the capacitor (FIGS. 10 and 3-8). That is, in the present invention, as shown in FIG.
A capacitor consisting of a capacitor 1-16, a capacitor insulating film 1-17, and a plate electrode 1-18 is arranged above the data line 1-12 via an interlayer insulating film 1-13 and a contact hole 1-14 is formed. Electrical conduction is obtained between the lower electrode 1-16 and the diffusion layer 1-6. In FIG. 1, 1-1 is a semiconductor single crystal substrate, 1-12 is an element isolation region, 1-3 is a gate oxide film, and 1-
4 is a gate electrode, 1-5 is a diffusion layer, 1-7 and 1-10 are interlayer insulating films,
1-11 are contact holes. By adopting the structure as shown in FIG. 1, the contact L1-11 is connected to the plate electrode 1-1.
8, there is no opening inside, and the plate electrode 1-18 and the contact hole 1-11 are completely non-interfering in position, and there is no need to consider the processing allowance. Therefore, the plate electrode
1-18 can be formed integrally on the entire surface of the cell. Therefore, there is no need for a margin for processing the plate electrode 1-18 and the capacitor lower electrode 1-16. For the above reasons, the capacitor lower electrode 1
-16 can be designed very large. That is,
In the semiconductor memory device according to the present invention, the capacitor area can be increased, and a sufficient capacitor capacity can be secured without reducing the thickness of the capacitor insulating film. Therefore, miniaturization can be achieved without lowering the reliability. Hereinafter, a cell manufacturing process will be described with reference to FIGS. 2 to 6 based on an embodiment relating to the present invention. First, as shown in FIG. 2, an SiO 2 film for electrically isolating elements is grown on a semiconductor single crystal substrate 2-1 by a known LOCOS method or the like. Assume 2. Next, the gate oxide film 2-
3 and low-resistance polycrystalline silicon and S
The gate electrode 2-4 and the interlayer insulating film 2-7 are formed by depositing an iO2 film by a CVD method and processing it using a usual lithography and dry etching technique. After this, CV
After depositing a SiO2 film on the entire surface by D method and applying anisotropic dry etching to form a sidewall insulating film 2-19,
Diffusion layers 2-5 and 2-6 having different conductivity types from the substrate 2-1 are formed in a self-aligned manner using an ion implantation method or the like. Thereafter, a heat treatment is performed to activate the introduced impurities. It is also possible to use a known diffusion layer structure of a slow electric field type for the diffusion layers 2-5 and 2-6. Next, as shown in FIG. 3, the diffusion layers 2-5 and 2-6
Then, a contact hole exposing a part of the contact hole is opened, low-resistance polycrystalline silicon is deposited by a CVD method, and conductor layers 2-8 and 2-9 are formed by ordinary lithography and dry etching techniques. Thereafter, the whole is covered with a thick SiO2 film by the CVD method, and then a contact hole 2-11 is formed by a usual lithography and dry etching technique, and only a part of one of the conductor layers 2-9 is exposed. Here, a conductor layer to be the data line 2-12 is formed by a CVD method or a sputter method, and is patterned by lithography and dry etching. Here, a method of forming a contact hole directly reaching the diffusion layer 2-5 without using the conductor layer 2-9 is also possible. The method shown in FIG. 3 is excellent in that a fine contact hole with suppressed directional etching can be obtained. Although low-resistance polycrystalline silicon is used as the data line material in this structure, a low-resistance metal such as Al, a high-melting metal such as W, a silicon compound thereof, or a laminated film of these may be used. is there. Next, after covering the whole with an insulating film such as a SiO2 film, a contact hole 2-14 is formed by lithography and dry etching techniques to expose a part of the conductor layer 2-8. In the related structure of the present invention, it is important that the data line 2-12 and the contact hole 2-14 shown in FIG. 4 do not overlap in a plane. One way to achieve this is to use data lines 6-8 as shown in the layout shown in FIG.
The pattern (hatched portion) is bent and crossed on the word line 6-2, avoiding the contact hole 6-3, and extends over the element isolation oxide film 6-1. With such a configuration, the configuration of the cell layout is simplified, that is, the pattern of the active region (the region where the switching transistor is formed) surrounded by the element isolation oxide film (LOCOS) 6-1 pattern is simplified. It has a rectangular shape.
Is sufficiently secured. In the data line 4-8 layout shown in FIG. 7, the data line 4-8 is located at the contact hole 4-3.
(See FIG. 4), and the line width of the data line 4-8 cannot be sufficiently secured. In order to ensure a sufficient line width of the data line 4-8 punched at the contact hole 4-3, a partial wide wiring at the contact hole 4-3 is required. Next, by performing anisotropic dry etching of the interlayer insulating film 2-15, as shown in FIG.
The interlayer insulating film 2-15 is left only on the side wall 2-14. Thereafter, a lower capacitor electrode 2-16 is formed. Low resistance polycrystalline silicon
It is deposited by a CVD method. At this time, if the thickness of the deposited low-resistance polycrystalline silicon is made smaller than the radius of the contact hole 2-14, the capacitor lower electrode 2-16 has a recess inside the contact hole, and this recess can also be used as the capacitor area. It is convenient. Next, as shown in FIG. 6, the lower electrode 2 is formed by lithography and dry etching techniques.
Pattern 16 On the surface of the lower capacitor electrode 2-16, a capacitor continuous film 2-17 is formed. In this embodiment, a SiO2 film formed by oxidizing polycrystalline silicon by a thermal oxidation method was used as the capacitor insulating film.
A high-dielectric-constant insulating film such as a Si3N4 film or tantalum pentoxide formed by the D method or a laminated film of these can also be used. Finally, CV is applied to the low-resistivity polycrystalline silicon to become the plate electrode 2-18.
Formed over the entire surface by D method. Thereafter, a contact hole having an opening in the plate electrode 2-18 is provided around the memory array as necessary, and the data line 2-12 and the gate electrode 2-4 are taken out above the plate electrode 2-18. Make connections with peripheral circuits. Through the above steps, the semiconductor memory device of the present invention is completed. In this embodiment, the capacitor lower electrode is used.
2-16 and the plate electrode 2-18 were made of low-resistance polycrystalline silicon.
It is also possible to use a low resistance metal such as 1 or Au, a high melting point metal such as W, a silicon compound thereof, or a laminated film of these. FIG. 7 is a layout diagram of a capacitor cell according to the present invention, and FIG. 8 is a schematic diagram of a layout diagram of a conventional stacked capacitor cell. Although FIGS. 7 and 8 show the case of two intersection cells, the present invention is also applicable to one intersection cell. In both figures, the alignment margin, line width, and space width are the same. In the cell configuration shown in FIG. 7, the plate electrode covers the entire surface of the cell, and the plate electrode 5-5 shown in FIG.
Such an opening is not required. This is seen in the conventional stacked type capacitor cell due to the structure in which the capacitor portion is lifted up to the upper part of the data line. This is because it is no longer necessary to consider the alignment between the plate electrode 5-5 and the contact hole 5-6. As a result, the capacitor lower electrode 4-4 can be enlarged within a range that does not affect the capacitor lower electrode of an adjacent cell, so that the capacitor area can be significantly increased even with the same cell area. The capacitor area of the conventional stacked capacitance type capacitor cell is 60 times the cell area even if the side wall of the capacitor lower electrode is taken into account.
%. According to the present invention, the structure in which the capacitor portion is lifted up to the upper part of the data line allows the capacitor area to be reduced.
It reaches more than 130% of the cell area, and the capacitor area can be more than doubled. Actually, as a result of trial production according to the layout of FIG. 7, the capacitor area reached 140% of the cell area, confirming the effect of the present invention. Moreover, FIG.
Data line 6-8 (shaded area) as shown in the layout shown in
Are bent and crossed on the word line 6-2 avoiding the contact hole 6-3, and are extended in a pattern on the element isolation oxide film 6-1. With this configuration, the configuration of the cell layout is simplified, that is, the element isolation oxide film (LOCO
S) The pattern of the active region (the region where the switching transistor is formed) surrounded by the 6-1 pattern is made a simple rectangular shape, and the line width of the word line 6-2 can be sufficiently ensured while miniaturizing the cell. The data line extraction (data line contact) from the diffusion layer, that is, the impurity layer is performed as shown in FIGS.
As shown in the figure, the process is performed via a contact hole formed by self-alignment defined by the sidewall insulating film 2-19, and via a conductor layer 2-9 formed in the contact hole. For this reason, along with the miniaturization of the contact hole, the conductor layer plays a role of alleviating the step difference of the data line contact, and has an effect of preventing the data line from being disconnected.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a main part of a semiconductor memory device according to an embodiment related to the present invention. FIG. 2 is a fragmentary cross-sectional view showing an example of the manufacturing process of the semiconductor memory device according to the embodiment of the present invention; FIG. 3 is an essential part cross sectional view showing an example of a manufacturing step of a semiconductor memory device which is an embodiment related to the present invention; FIG. 4 is a fragmentary cross-sectional view showing an example of the manufacturing process of the semiconductor memory device according to the embodiment related to the present invention; FIG. 5 is a fragmentary cross-sectional view showing an example of the manufacturing process of the semiconductor memory device according to the embodiment related to the present invention; FIG. 6 is a fragmentary cross-sectional view showing an example of the manufacturing process of the semiconductor memory device according to the embodiment related to the present invention; FIG. 7 is a plan layout diagram of a semiconductor memory device according to an embodiment related to the present invention; FIG. 8 is a plan layout diagram of a conventional semiconductor memory device. FIG. 9 is a plan layout diagram of the semiconductor memory device according to the embodiment of the present invention; FIG. 10 is a cross-sectional view of a main part showing a semiconductor memory device having a conventional structure. [Explanation of Signs] 1-1 Semiconductor single crystal substrate 1-2 Device isolation oxide film 1-3 Gate oxide film 1-4 Gate electrode 1-5 Diffusion layer 1-6 Diffusion layer 1-7 Interlayer insulation film 1-10 Interlayer insulating film 1-11 Contact hole 1-12 Data line 1-13 Interlayer insulating film 1-14 Contact hole 1-16 Capacitor lower electrode 1-17 Capacitor insulating film 1-18 Plate electrode

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Shinpei Iijima 1-280 Higashi-Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Teruaki Kisu 1448, Josuihoncho, Kodaira-shi, Tokyo SII Engineering Co., Ltd. (56) References JP-A-54-91083 (JP, A) JP-A-57-93566 (JP, A) JP-A-57-120295 (JP, A) JP 58-215067 (JP, A) JP-A-59-231851 (JP, A) JP-A-61-258467 (JP, A) JP-A-62-36853 (JP, A) JP-A-62-145765 (JP, A) A) JP-A-63-209157 (JP, A) JP-A-55-178894 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/108 H01L 21/822 H01L 21 / 8242 H01L 27/04

Claims (1)

(57) [Claims] A semiconductor substrate and a first conductivity type semiconductor substrate having a second conductivity type formed on the first conductivity type semiconductor surface of the semiconductor substrate so as to be spaced apart from each other;
And a second semiconductor region; a gate insulating film located on the surface of the semiconductor substrate between the first and second semiconductor regions; and a word line formed on the gate insulating film. and use the field-effect transistor, said a data line connected to the first semiconductor region, a first calibration, which are electrically connected to the second semiconductor region
Has a Pashita electrodes, the a first capacitor insulating film formed on the capacitor electrode, and a charge storage capacitor which is composed of a second capacitor electrode formed on the capacitor insulating film, the transistor and the in a storage capacity <br/> Sita a semiconductor memory device the memory cell, the first and the first semiconductor region and said second semiconductor region
Is formed in the longitudinal direction by an element isolation film, and is formed between the first and second semiconductor regions in the first longitudinal direction.
A word line extends in a second longitudinal direction intersecting the data line , and the data line is connected to the first semiconductor region via a conductor layer.
Connected to each other and extending in the first longitudinal direction, wherein the first capacitor electrode is connected to the second semiconductor region.
Connected via the body layer and placed on the data line
The semiconductor memory device, characterized in that that.