JPS59231851A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To produce the title memory cell with the largest storage region and the smallest invalid region by a method wherein the storage region of memory data is formed upon a word line layer and a bit line layer. CONSTITUTION:The first interinsulatinglayer film 5 and the second interinsulatinglayer film 5a are provided on a diffusion region 2 such as source.drain and separated lower electrode layer 10 for capacitor is formed on the film 5. Next the exposed pert is covered with a thin Si3N4 film 11 whereon an upper electrode layer 12 for capacitor is deposited and a throughhole 12a is made therein. Then the layer 12 is again covered with another Si3N4 film 11 filling the throughhole 12a. Later another throughhole 9a reaching the diffused region 2 is made by means of dryetching process and the overall surface is coated with a lower electrode topmost layer 10a filling the throughhole 9a. At this time, any invalid region for data storage such as contact part may be diminished by means of repeating said processes to form multiple lower electrode layers 10 finally covered with the topmost layer 10a with a cell capacitor provided on a layer above a word line and a bit line.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a one-transistor type semiconductor memory cell.

A conventional semiconductor memory cell of this type has been formed, for example, as shown in FIG. FIG. 1(a) is a cross-sectional view of a semiconductor memory cell, and FIG. Figure 1 (a) fc space 1 is an isolation region such as LOCOS, 2 is a north drain diffusion layer of a MOS transistor, 3 is a first gate layer forming a capacitor, 4 is a gate of a MOS transistor and a word 5 is an insulating interlayer film, and 6 is a contact 1.7 which connects the bit line and the north diffusion layer of the MO3+- Lancek. In addition, in FIG. 1 fbl, 2a is an active region excluding the isolation region;
8 is the memory cell area in this example. This memory cell operates to store bit line information in the capacitor formed by the first gate layer 3 by conduction of the MO3 transistor. This storage region is represented by the overlapping portion of the activation region 2a and the first gate layer 3, as shown by the diagonal lines in FIG. It cannot be made very large because of the ineffective area for isolation of the contact part 6 with the LOGO 8, etc.Especially, as the memory cell area tends to decrease due to higher density, the ineffective area does not become much smaller. Therefore, this storage region becomes smaller and smaller, and there is a strong possibility that it will no longer be possible to secure a sufficient amount of stored charge.Furthermore, when considering measures against knot errors caused by the incidence of alpha rays, etc., this kind of The memory cell structure has the disadvantage that it is not suitable for future increases in memory density and capacity.

In order to eliminate these drawbacks, the present invention has developed a semiconductor memory cell in which the storage information storage area is formed in a layer above the word line layer and bit line layer, thereby minimizing the invalid area and ensuring a large storage area. This is what we provide.

The present invention will be explained in detail below with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, and FIG. 2a) is a cross-sectional view of a memory cell, and FIG. 2b+ is a layout diagram of FIG. 2A viewed from above. Parts corresponding to those in Figure 1 are numbered the same. FIG. 2 (In Al, the first gate layer 30 in FIG. 1 is replaced with a carrier-poor/yuetsu lower electrode layer 10, 10a, and a thin insulating film]-1, 1, 1a,

Upper electrode layer for capacitor] 2 and 13 are formed on the second insulating interlayer film 5a formed on the MO8I line, the word line, and the pit line. 9a is the lower electrode layer for the capacitor which has a laminated structure] 0°10a etc.
OS) Ranjisk's 1! This is a through hole for a contact connected to the drain diffusion layer, and by filling the inside thereof with 10a when forming the uppermost layer of the lower electrode for the capacitor, each of the lower electrode layers 10 and 10a is connected to the drain diffusion layer. There is. - Ushita, 12a in Fig. 2+b)
is a through hole in the capacitor upper electrode layer excluding the top layer.

To form this memory cell structure, an element isolation region such as LOCO8 is formed by selective oxidation or the like. next,
After forming the gate oxide film, the gate (in this example, word line) 4 of the MOS transistor is formed. Next North 1
・The rain diffusion layer 2 is formed by self-alignment. Next, an insulating interlayer film 5 is deposited, and then through holes for contacts 6 are opened. Next, a bit line layer 7 is formed.

Thereafter, a second insulating interlayer film 5a is further deposited. The thickness of this film should be about the same as that of the insulating interlayer film 5 (for example, several thousand angstroms), and the thickness of the film should be approximately the same as that of the insulating interlayer film 5 (for example, several thousand angstroms). A Keep the 'fi' amount small.

A basic example of the subsequent manufacturing process is shown in FIG. 3, in which a lower electrode layer 10 for a capacitor is deposited without cutting, and the space between adjacent cells is etched to form a lower electrode layer 10 for a capacitor (see FIG. 3). ). Next, a thin insulating film 11 such as a silicon thermal nitride film is
(Figure (b)). Next, the upper electrode layer 12 for the capacitor is deposited, and a through hole 12a is formed in a part of the upper electrode layer 12 to electrically connect the upper layer and the lower layer (Fig.
C)). Next, a thin insulating film 1 is formed again (Figure (d))
). Repeat the steps from Figure (a) to Figure (di) as many times as necessary.
Diffusion layer 2 (C) is opened in Plan 1. The formation of this through hole is done using groove forming technology, which has recently been developed.
This is fully possible by using the para-enoching process. Further, this through hole is formed in the through hole provided in the capacitor lower electrode layer 12a (Fig.
e)).

Next, deposit the two layers 10a of the lower electrode for cavitation 1, and form the drain diffusion layer 2 using the through pole 9a.
Connect with. Thereby, the plurality of capacitor lower electrode layers 10 are connected to the capacitor lower electrode uppermost layer 10a.

　　I will do it.

The subsequent manufacturing process is as shown in Figure 2 (at).
After forming a thin insulating film (uppermost insulating film) 11a similar to the above, a capacitor upper electrode uppermost film 13 is formed 1'. Note that the plurality of capacitor lower electrode layers J2 and the capacitor lower electrode uppermost layer 3 are connected at the chip periphery. However, it is not shown in FIG.

In such a memory cell structure, the cell gap capacitor can be formed in a layer above the word lines and bit lines, eliminating the conventionally existing invalid areas such as word line areas and contact areas with bint lines that cannot be used to store information. , a large storage area can be efficiently secured as shown by diagonal lines in FIG. 2 fbl. Furthermore, in the present invention, since the capacitor layer can be constructed in a laminated structure, the memory cell capacity can be made sufficiently large. 1. On the other hand, if you think about it, the effective area as a capacitor increases due to the stacked structure, so it is possible to increase the memory capacity without making the insulating film extremely thin, as shown in l↑ and lla. It has the advantage of being secure.

As explained above, in the semiconductor memory cell according to the present invention, since the capacitor is formed in the soil layer from the MOS transistor, the bit line, and the word line, the storage information storage area can be maximized, and the interlayer The storage capacity is not affected much by misalignment, and a large memory cell capacity can be secured with a small memory cell area, making it ideal as a memory cell for high-density, large-capacity memory. If we add the capacitor as shown in Figure 1(a)
Since it is not formed by a depletion layer formed by the diffusion region shown in 2, knot errors are less likely to occur even when α rays are incident, and there is an advantage that a highly reliable memory cell can be provided.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are a cross-sectional view and a plan layout diagram showing an example of a conventional one-transistor semiconductor memory cell, and FIG. 2(a) (bl is a cross-sectional view and a plan layout diagram showing an example of the present invention). Layout diagram, Figure 3 (al (b) (cl (
dl fe) (fl is a cross-sectional view showing an example of the 3fi process in the main part of this project. j...Isolation regions such as LOGO8, 2. Source/drain diffusion layer, 3. Forming a capacitor. 1/7th
'-+ layer (upper electrode for capacitor), 4... second gate layer, 5... insulating interlayer film, 5a... second insulating interlayer film, 6... contact 1-17 - bit line, 2a・
・Activation region, 8 Memory cell area, 9a ・Through hole, 10... Lower electrode layer for capacitor, 11.
... Thin insulating film, 12... Upper electrode layer for capacitor, 10a... Lower electrode uppermost layer for capacitor, Jla insulating film layer" two layers, ] 3. Upper electrode uppermost layer for Gichobanta,
12a - Upper electrode layer through pole for cabbage. Patent applicant: Nippon Telegraph and Telephone Public Corporation Representative: Hakusui Tsuneo -yyz2. 1 figure, 5a) 5a 12a a ``), 5a

Claims (1)

[Claims] One MO8+- transistor, and a bit line, a capacitor, and a word line connected to the north, drain, and gate terminals of the MO8+ transistor, respectively, for storing information.
In a transistor type memory cell, the MOS transistor, word line, and bit line formed on a semiconductor substrate, and a lower electrode layer for a capantor, an insulating film, and a through hole for a capacitor are provided above the word line and bit line. A two-part electrode layer, a plurality of capacitor layers formed by stacking layers of an insulating film as one unit, and a capacitor layer formed on the capacitor layer, the MOS) drain of the transistor and the through layer on the semiconductor substrate. Using the hole part, the two uppermost layers of the lower electrode for the capacitor, the uppermost layer of the insulating film formed on the uppermost layer of the lower electrode for the capacitor, and the uppermost layer of the insulating film formed on the uppermost layer of the lower electrode for the capacitor. A semiconductor memory cell having a capacitor upper capacitor formed thereon.