JPH08288475A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE: To improve reliability even if a capacitor electrode is thinned and increase capacitance by bringing a capacitor electrode into contact through a conductor layer and forming it to extend on a bit line. CONSTITUTION: First and second conductor layers 2-8, 2-9 are pattern-formed in each semiconductor region and a bit line in contact with the second conductor layer 2-9 is formed. Thereafter, layer insulation films 2-13, 2-15 are deposited on a bit line and a contact hole is provided to the layer insulation films 2-13, 2-15 to exposed the first conductor film 2-8 partially. A capacitor electrode 2-16 is formed to form an electrical contact to the first conductor layer 2-8 and to extend on a bit line. That is, a capacitor electrode does not come into direct contact by lowering to a semiconductor region but come into contact through the conductive layer 2-8 and is formed to extend on a bit line. Capacitance can be increased in this way.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a method of manufacturing a semiconductor memory device which can be miniaturized without lowering the reliability of a charge storage capacitor.

[0002]

2. Description of the Related Art High integration of dynamic random access memory (dRAM) has been realized at a remarkable speed, and the current mainstream has shifted from 64K bits to 256K bits.
Mass production of M-bit dRAM has started. This high integration has been achieved by miniaturization of device dimensions. However, due to the reduction of capacitors (capacitance) due to miniaturization, adverse effects such as a decrease in S / N ratio and signal inversion due to α rays (so-called soft error) become apparent, which is a major issue in terms of reliability. ing. For this reason, in order to increase the capacity of the capacitor, a grooved type capacitor cell (trench capacitor cell) that uses the groove wall dug in the substrate, or IEE, Eterna Electron Device Deviating Meeting Meeting Technical digest (IEEE, Int, Electron Devi
ces Meeting Tech, Dig.) pp348-351, Dec (1978) Koyanagi, Sunami, Hashimoto and Ashikawa et al. "Novel high density, Stacked capacitor MOS RA"
Stacked type capacitor cells (stacked type capacitor cells), which have been discussed in the literature entitled "M", etc., in which the capacitive parts are stacked, have been expected to replace conventional planar type capacitors. Out of
Unlike the grooved capacitor, the latter stacked capacitor does not require the advanced technology of drilling fine grooves in the substrate, so it will be noted as a capacitor structure when further miniaturization of the device is required in the future. Has been done.

FIG. 10 shows a sectional view of a dRAM having a conventional stacked capacitor. The manufacturing method will be briefly described.

First, an oxide film 3-2 for insulating and isolating elements is selectively grown on a single crystal substrate 3-1. Next, the gate oxide film 3-3 of the transistor is grown. Polycrystalline silicon containing impurities is deposited as the gate electrode 3-4, processed, and then the diffusion layer 3 is formed by ion implantation using the gate electrode 3-4 and the element isolation oxide film 3-2 as a mask. -5 and 3-6 are formed. Next, the diffusion layer 3-
The capacitor lower electrode 3-8 is formed by depositing and processing polycrystalline silicon 3-8 containing impurities on the region 6. At this time, the capacitor lower electrode 3-8 is formed on the gate electrode 3-4 and the element isolation oxide film 3-2, so that the capacitor area is larger than that of the conventional planar capacitor that uses only a flat surface. It is possible to The gate electrode 3-4 is covered with an interlayer insulating film 3-7 such as an oxide film. An oxide film or the like is formed on the capacitor lower electrode 3-8 formed as described above to form a capacitor insulating film 3-9. A plate electrode 3-10 is formed by further depositing and processing a conductor on this to complete the capacitor.

Further, an interlayer insulating film 3-11 is deposited on this, and a contact layer L3-12 is opened so that a part of the diffusion layer 3-5 of the transistor is exposed. Form 3-13.

The above manufacturing method makes it possible to increase the capacitance of the capacitor compared to the planar type dRAM cell in which the capacitor is formed only on the plane of the substrate.

[0007]

However, in the above-mentioned conventional stacked capacitance type capacitor cell, the capacitor lower electrode 3-8 cannot be made sufficiently large for the following two reasons, and with the miniaturization of the element, The problem that the capacity of the capacitor was reduced remarkably occurred, and it was difficult to construct a highly integrated memory circuit. That is, first, the contact hole 3-12 is required to electrically connect the data line 3-13 and the diffusion layer 3-5. Further, it is necessary to consider a machining alignment margin between the contact hole 3-12 and the plate electrode 3-10. Therefore, it is necessary to form the plate electrode 3-10 while avoiding the contact hole 3-12 and the portion necessary for the alignment margin, and the area cannot be increased. The alignment margin is necessary to prevent the plate electrode 3-10 from being exposed when the contact hole 3-12 is formed, and as a result, the data line 3-13 and the plate electrode 3-10 to be shorted. No. 2
In order to increase the reliability of the capacitor, the lower electrode 3-8 of the capacitor needs to be completely covered by the plate electrode 3-10, and the lower electrode 3-8 of the capacitor is only the machining allowance. It must be smaller than the plate electrode 3-10. Therefore, due to the above reasons, the capacitor lower electrode 3-8
However, there is a problem in that the capacity of the capacitor cannot be increased and the capacity of the capacitor becomes small as a result. On the other hand, the capacitance of the capacitor is inversely proportional to the thickness of the capacitor insulation film. Therefore, in order to configure a more highly integrated memory circuit using the conventional stacked capacitance type capacitor cell and to secure the required capacitor capacity, the capacitor insulation film is required. A means of further thinning 3-9 may be considered. However, thinning the capacitor insulating film 3-9 is not practical because there is a problem that the reliability of the capacitor is lowered due to an increase in leak current and the like. An object of the present invention is to provide a semiconductor memory device which has high reliability even when miniaturized and has a large capacitor capacity.

[0008]

According to the present invention, the capacitor electrode is formed so as not to go directly down to the semiconductor region to make a contact, but to make a contact via the conductor layer and to extend on the bit line. To do.

[0009]

According to the present invention, since the capacitor electrode is contacted via the conductor layer, the depth of the contact hole in the interlayer insulating film on the conductor layer can be made shallow and fine. Since the capacitor electrode can be formed so as to extend on the bit line, the capacity can be increased.

[0010]

EXAMPLE In the present invention, the plate electrode (FIGS. 10 and 3-10), the contact hole (FIGS. 10 and 3-12) and the plate electrode (FIGS. 10 and 3-13), which have been problems in the conventional stacked type capacitor cell, have been problems. ) The structure is such that a machining alignment margin with the capacitor lower electrode (FIGS. 10 and 3-8) is unnecessary. That is, in the present invention, as shown in FIG. 1, a capacitor including a capacitor lower electrode 1-16, a capacitor insulating film 1-17, and a plate electrode 1-18 is provided above the data line 1-12 and the interlayer insulating film 1-13. And the contact hole 1-14 is formed so that conduction is obtained between the capacitor lower electrode 1-16 and the diffusion layer 1-6.

In FIG. 1, 1-1 is a semiconductor single crystal substrate, 1-12 is an element isolation region, 1-3 is a gate oxide film, 1-
4 is a gate electrode, 1-5 is a diffusion layer, 1-7 and 1-10 are interlayer insulating films,
1-11 is a contact hole. With the structure shown in FIG. 1, the contact element L1-11 becomes the plate electrode 1-1.
8 There is no opening inside, and the plate electrode 1-18 and the contact hole 1-11 are completely non-interfering in position, and it is not necessary to consider the machining alignment margin. Therefore, the plate electrode
1-18 can be formed integrally on the entire surface of the cell. Therefore, there is no need for a machining alignment margin between the plate electrode 1-18 and the capacitor lower electrode 1-16.

For the above reasons, the capacitor lower electrode 1
The 16 can be designed to be extremely large. That is,
According to the present invention, in the semiconductor memory device, it is possible to increase the capacitor area, and it is possible to secure a sufficient capacitor capacity without thinning the capacitor insulating film. Therefore, further miniaturization can be achieved without lowering reliability.

An embodiment of the present invention will be described below with reference to FIGS.

First, as shown in FIG. 2, a SiO2 film for electrically isolating elements from each other is grown on a semiconductor single crystal substrate 2-1 by a known LOCOS method or the like to form an inter-element isolation oxide film 2-. Set to 2. Next, using a normal thermal oxidation film, the gate oxide film 2-
3 is grown, and low resistance polycrystalline silicon and S
A gate electrode 2-4 and an interlayer insulating film 2-7 are formed by depositing an iO2 film by a CVD method and processing it by using ordinary lithographic and dry etching techniques. After this, CV
After the SiO2 film is deposited on the entire surface by the D method and anisotropic dry etching is performed to form the sidewall insulating film 2-19,
Diffusion layers 2-5 and 2-6 having different conductivity types from the substrate 2-1 are formed in a self-aligned manner by using an ion implantation method or the like. After that, a heat treatment is performed to activate the introduced impurities. It is also possible to use a known electric field relaxation type diffusion layer structure for the diffusion layers 2-5 and 2-6.

Next, as shown in FIG. 3, diffusion layers 2-5, 2-6
A contact hole exposing a part of the above is opened, low resistance polycrystalline silicon is deposited by a CVD method, and conductor layers 2-8 and 2-9 are formed by ordinary lithographic and dry etching techniques. After that, the whole is covered with a thick SiO 2 film by a CVD method, and then a contact hole 2-11 is formed by a usual lithography and dry etching technique to expose only a part of one conductor layer 2-9. Here, a conductor layer to be the data line 2-12 is formed by the CVD method, the sputtering method or the like, and is patterned by the lithographic and dry etching methods. Here, it is possible to form a contact hole directly reaching the diffusion layer 2-5 without using the conductor layer 2-9, but it is also possible to reduce the alignment margin between the contact hole and the diffusion layer, The method shown in FIG. 3 is superior to the method shown in FIG.

As the data line material, low resistance polycrystalline silicon is used in this embodiment, but a low resistance metal such as Al, a high melting point metal such as W, a silicon compound thereof, or a laminated film of these may be used. Is.

Next, after covering the whole with an insulating film such as a SiO2 film, contact holes 2-14 are formed by lithographic and dry etching techniques to expose a part of the conductor layer 2-8. In the structure of the present invention, it is important that the data line 2-12 and the contact hole 2-14 do not overlap in a plane. As one method of achieving this, even if the layout is allowed to overlap as shown in FIG.
There is a method of removing the data line of the overlapping portion at the time of formation. As another method, there is also a method in which the layout is configured as shown in FIG. 9 so that the structure does not overlap.

Then, the interlayer insulating film 2-15 is anisotropically dry-etched to form contact holes as shown in FIG.
The interlayer insulating film 2-15 is left only on the side wall of 2-14. After that, it becomes the capacitor lower electrode 2-16. Low resistance polycrystalline silicon
It is deposited by the CVD method. At this time, if the film thickness of the low-resistance polycrystalline silicon to be deposited is made smaller than the radius of the contact hole 2-14, the lower capacitor electrode 2-16 has a recess inside the contact hole, and this recess can also be used as the capacitor area. So convenient.

Next, as shown in FIG. 6, the capacitor lower electrode 2- is formed by lithographic and dry etching techniques.
Pattern 16 A capacitor cascading film 2-17 is formed on the surface of the capacitor lower electrode 2-16. In this embodiment, as the capacitor insulating film, a SiO2 film formed by oxidizing polycrystalline silicon by a thermal oxidation method is used.
A Si3N4 film formed by the D method, a high dielectric constant insulating film such as tantalum pentoxide, or a laminated film thereof can also be used. Finally, CV is applied to the low resistance polycrystalline silicon that will become the plate electrodes 2-18.
Formed on the entire surface by D method. After this, if necessary, around the memory array, a contact hole having an opening is provided in the plate electrode 2-18, and the data line 2-12 and the gate electrode 2-4 are taken out to the upper part of the plate electrode 2-18. Connect to peripheral circuits. Through the above steps, the semiconductor memory device of the present invention is completed.

In this embodiment, the capacitor lower electrode
2-16 and plate electrodes 2-18 were made of low-resistance polycrystalline silicon.
It is also possible to use a low resistance metal such as l or Au, a high melting point metal such as W, a silicon compound thereof, or a laminated film thereof.

[0021]

The layout of the capacitor cell according to the present invention is shown in FIG. 7, and the layout of the conventional stacked type capacitor cell is shown in FIG.
Although FIG. 7 and FIG. 8 show the case of a two-intersection cell, the present invention
It is also applicable to intersection cells. Note that the alignment margin, line width, and space width are the same in both figures.

In the embodiment shown in FIG. 7, the plate electrode covers the entire surface of the cell, and the plate electrode 5-5 shown in FIG.
No such opening is required. This was found in the conventional stacked type capacitor cell due to the structure of the present invention in which the capacitor portion is lifted to the upper part of the data line. Plate electrode 5-
This is because it is no longer necessary to consider the combination of 5 and the contact hole 5-6. As a result, the capacitor lower electrode 4-4 is
Since the size can be increased within a range that does not affect the lower capacitor electrodes of adjacent cells, it is possible to significantly increase the capacitor area even with the same cell area. The area of the capacitor in the conventional stacked capacity type capacitor cell is
Even if the side wall of the lower electrode of the capacitor is taken into consideration, it reaches only about 60% of the cell area.

On the other hand, according to the present invention, the capacitor area reaches 130% or more of the cell area, and the capacitor area is
It is possible to increase it more than twice. As a result of actually making a prototype according to the layout of FIG. 7, the capacitor area reached 140% of the cell area, confirming the effect of the present invention.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to the embodiment of the present invention.

FIG. 3 is a main-portion cross-sectional view showing an example of manufacturing process of a semiconductor memory device in accordance with an embodiment of the present invention.

FIG. 4 is a main-portion cross-sectional view showing an example of manufacturing process of a semiconductor memory device in accordance with an embodiment of the present invention.

FIG. 5 is a main-portion cross-sectional view showing an example of manufacturing process of the semiconductor memory device in accordance with one embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view showing an example of a manufacturing process of the semiconductor memory device according to the embodiment of the present invention.

FIG. 7 is a plan layout view of a semiconductor memory device according to an embodiment of the present invention.

FIG. 8 is a plan layout view of a semiconductor memory device having a conventional structure.

FIG. 9 is a plan layout view of a semiconductor memory device according to another embodiment of the present invention.

FIG. 10 is a main-portion cross-sectional view showing a semiconductor memory device having a conventional structure.

[Explanation of symbols]

 1-1 Semiconductor single crystal substrate 1-2 Isolation oxide film between elements 1-3 Gate oxide film 1-4 Gate electrode 1-5 Diffusion layer 1-6 Diffusion layer 1-7 Interlayer insulation film 1-10 Interlayer insulation film 1- 11 Contact hole 1-12 Data line 1-13 Interlayer insulation film 1-14 Contact hole 1-16 Capacitor lower electrode 1-17 Capacitor insulation film 1-18 Plate electrode

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Atsushi Hiraiwa 1-280, Higashi Koikeku, Kokubunji, Tokyo, Central Research Laboratory, Hitachi, Ltd. (72) Shinhei Iijima 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Teruaki Kizu 1448, Kamisuihonmachi, Kodaira-shi, Tokyo Hitachi Ultra Engineering Engineering Co., Ltd.

Claims (4)

[Claims] 1. A switching transistor forming at least a pair of semiconductor regions, a gate insulating film and a gate electrode is formed on a main surface of a semiconductor substrate, and first and second conductor layers are patterned on each of the semiconductor regions. Forming a bit line in contact with the second conductor layer, and then depositing an interlayer insulating film on the bit line,
A contact hole is formed so that a part of the first conductor film is exposed, and an electrical contact is made to the first conductor layer,
A method of manufacturing a semiconductor memory device, comprising forming a capacitor so as to extend on the bit line. 2. A switching transistor forming at least a pair of semiconductor regions, a gate insulating film and a gate electrode is formed on a main surface of a semiconductor substrate, and first and second conductor layers are patterned on each of the semiconductor regions. Forming a bit line in contact with the second conductor layer, and then depositing an interlayer insulating film on the bit line,
A contact hole is formed so that a part of the first conductor film is exposed, and an electrical contact is made to the first conductor layer,
A first capacitor electrode is patterned so as to extend on the bit line, a capacitor insulating film along the surface of the first capacitor electrode is covered, and a second capacitor electrode is formed so as to cover the capacitor insulating film. Manufacturing method of semiconductor memory device. 3. The method of manufacturing a semiconductor memory device according to claim 2, wherein the capacitor insulating film is a single layer film of a material selected from Si3N4 and tantalum pentoxide or a laminated layer thereof. 4. A switching transistor forming at least a pair of semiconductor regions, a gate insulating film and a gate electrode is formed on the main surface of a semiconductor substrate, and first and second conductor layers are patterned on each of the semiconductor regions. Forming a bit line in contact with the second conductor layer, and then depositing a first interlayer insulating film on the bit line, and arranging the first interlayer insulating film on the first conductor film. An opening is provided, a second interlayer insulating film is deposited on the first interlayer insulating film having the opening, and the second interlayer insulating film is anisotropically dry-etched so that the first interlayer insulating film is located at the opening. A contact hole is formed by exposing a part of the conductor film and leaving a part of the second interlayer insulating film as a sidewall in the opening of the first interlayer insulating film, and making an electrical contact with the first conductor layer. And extend above the bit line The method of manufacturing a semiconductor memory device, and forming a capacitor as.