JPS63104464A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the degree of preciseness in formation of the title semiconductor memory as well as to contrive reduction in its area by a method wherein a pair of transistors are connected or isolated in the first and the second grooves, with which the transistors are isolated in the direction of a word line and a bit line, or the pair of gate electrodes, which are connected or isolated utilizing the difference width of the grooves, are formed. CONSTITUTION:A capacitor insulating film 32, consisting of an SiO2 or the like, is formed on the lower wall surface of the grooves 24 and 25 on which a channel stopper 31 is formed on the lower part of the grooves, and a conductive plate 33 consisting of polycrystalline Si or the like is buried in the grooves. The left side and the right side capacitors are formed with a pair of electrodes consisting of the plate 33, which pinches the insulating film 32 on the left and right wall surfaces of the groove 24, and a substrate 30, and a capacitor is formed on the left and right sides of the groove 25 respectively. On the upper wall surface of the grooves 24 and 25 and on the circumference of the upper aperture part, a gate insulating film 34 such as the oxide film of SiO2 or the like is formed, and the gate electrode 35 of polycrystalline Si or the like is formed inside the film 34 surrounding each island 23. The left and right gate electrodes 35 and 35 of the first groove 24 are coupled with each other. The side wall-like electrode 35 on the left and right sides of the second groove 25 are isolated, and an N<+> type source and drain layer 36 is formed under the gate insulating film 34 on the surface of the substrate 30. On the gate insulating film 34 of the surface of the substrate 30, an intermediate insulating film 37 of SiO2 or the like and the bit line 21 of Al or the like are connected to the source and the drain layer 36, and a protective film 38 is coated.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention provides a dynamic RA)
The present invention relates to semiconductor memories such as (hereinafter simply referred to as DRAMs) and their manufacturing methods.

(Prior art) Conventionally, as a technology in this field, Japanese Patent Application Laid-Open No. 58-13
There was a device described in Japanese Patent No. 7245, and its configuration will be described below with reference to the drawings.

FIG. 2 is a cross-sectional view of a one-transistor type memory cell in a conventional DRA).

This memory cell has a P-type Si substrate 1, on which a field oxide film 2 is formed for electrically isolating a plurality of memory cells formed thereon. A trench 3 for forming a capacitor is formed in the area where the memory cell is to be formed and is separated by the field oxide film 2, and a two-layer capacitor insulating film 4-1 is formed on the Si substrate 1 including the wall surface inside the trench 3. , 4-2 are selectively formed. A conductive plate 5 made of polycrystalline Si or the like is selectively deposited in and around the upper portion of the groove 3, and a first interlayer oxide film 6 is formed thereon. On the Si substrate 1 in the vicinity of i+'l's 3, an l-gate oxide film 7 is selectively formed, connected to the capacitor insulating film 4-1, and a gate electrode is formed on the oxide films 1 to 7. At the same time, an N-type source/drain layer 9 is formed on the gate oxidized FIA 7'-Tτ. Furthermore, wires (Pi 1 to Wire) 10, such as 8 and 1, are deposited via the second interlayer insulating film 9.

The plate 5 and Si substrate 1 serving as electrodes and the insulating films 4-1 and 4-2 constitute a capacitor, and the gate electrode 8 and source/drain layer 9 constitute a HOS transistor.

In the above configuration, the potential of the word line (not shown) is set to H or L level, and the IO8 transistor is turned on.
The level on the ) line (10) is written to the capacitor, and the accumulated charge in the capacitor is written to the bit line (10).
0) Reading upward 9. Does this type of DRAM require a capacitor? Since it is formed within Il'r 3, a relatively large capacitor capacity can be obtained with a small area.

Next, a method of manufacturing the above DRAM will be explained.

First, a field oxide film 2 is selectively formed on a Si substrate using photolithography, and grooves 3 are formed by etching at locations where memory cells are to be formed, separated by the field oxide film 2. Thereafter, capacitor insulating films 4-1 and 4-2 are deposited on the Si substrate 1 including the inside of the groove 3, and a plate made of polycrystalline Si or the like is formed on the entire surface. 808) Plate 5 where the transistor is to be formed
is removed by photoetching.

The plate 5 is oxidized and a first interlayer oxide film 6 is formed thereon, and the oxide film 6 is used as a mask.
, 4-2 are removed by etching, and the exposed portion 81 of the substrate 1-1 is oxidized to form a gate oxide film 7. after that,
By selectively depositing the gate electrode 8 on the gate oxide film 7 and implanting ions such as phosphorus, a type of source is formed between the plate and the undeposited portion of the gate electrode 8. - Train layer 9 is formed.

Next, after depositing a second interlayer insulating film 9, holes for wiring reaching the source/drain layer 9, gate electrode 8, and plate 5 are formed, and wirings 10 such as Aρ are selectively deposited. Ba,
A one-transistor type memory cell as shown in FIG. 2 is obtained.

Note that instead of the field oxide film 2, an isolation groove 11 is formed by photolithography, and polycrystalline S is formed in the groove 11.
It is also possible to isolate adjacent memory cells by filling them with i, etc.

(Problems to be Solved by the Invention) However, in the DRAM formed as described above, mutual interference between each memory cell due to an increase in the density of memory cells is prevented by using the field oxide film 2 or isolation groove 1, which is an isolation region.
However, due to the formation of these films 2 or grooves 11, the reduction of the integrated density area is subject to certain limitations. Moreover, in the DRAM manufacturing method, the field oxide film 2 or the isolation trench 11 is selectively formed by photolithography, but not only does the number of manufacturing steps increase to form the film 2 or the trench 11, but Since the photolithography technique is used, a margin is required for mask alignment, and there is a problem that the area in which the film 2 or the groove 11 is formed cannot be significantly reduced.

The present invention provides a semiconductor memory and its memory which solves the problems of the prior art, such as the fact that there are certain restrictions on reducing the integration density area due to the formation of isolation regions, and the fact that the manufacturing time increases by about 2 F. A manufacturing method is provided.

(Means for Solving the Problems) In order to solve the above problems, the first invention has a plurality of word lines and bit lines formed on a semiconductor substrate, and a plurality of word lines and bit lines formed at each intersection of the word lines and the bit lines. In a semiconductor memory comprising a plurality of charge storage capacitors and charge transfer transistors connected and arranged in a matrix, a plurality of first transistors are provided for separating the intersections in the word line direction.
grooves, and a plurality of second banks for separating the intersections in the bit line direction. Furthermore, the capacitors are respectively extended in the first and second pans so as to surround each of the intersection points, and the transistors are installed in the first and second 2+IIi so as to surround each of the intersection points. and connects the pair of transistors in the first σ piece 1'lS to each other, and connects the pair of transistors 1 to 1 in the second groove to each other.
The transistors are separated from each other.

In addition, in the method for manufacturing a semiconductor memory according to the second invention, a memory cell insulating film is formed on a semiconductor substrate in which first and second anchors having different widths are formed in a matrix, and a proprietary electrically conductive film is further formed on the semiconductor substrate. After forming a plate film, the entire surface is etched to form a plate in the first and second grooves. Next, a gate insulating film is formed on the wall surface of the plate in the first and second trenches and on the surface of the semiconductor substrate, and a gate electrode film is further formed thereon, and then the entire surface is etched to form a gate insulating film on the wall surface of the plate in the first and second grooves and on the surface of the semiconductor substrate. In the second trench, one of a pair of connected gate electrodes and one of a pair of separated gate electrodes is formed using the difference in width.

(Function) According to the first invention, since the semiconductor memory is configured as described above, the capacitor and transistor formed in the vertical direction of the first and second grooves are arranged so as to reduce the mounting area of the memory cell. Work at.

In addition, in the manufacturing method of the second invention, the plate film is etched over the entire surface and the plate is formed in the groove using self-line, which improves the formation accuracy and reduces the formation area compared to the conventional method using photolithography. The size can be reduced and the number of steps can be reduced. Furthermore, the entire surface of the gate electrode film is etched to form a connected pair of gate electrodes and a separated pair of gate electrodes in the groove using self-alignment, which eliminates the photolithography process and thereby improves formation accuracy. The formation area can be reduced. Therefore, the above-mentioned problem can be eliminated.

(Example) Figure 3 shows an example of the present invention (DRA)! FIG. 1 (8) is a sectional view taken along the line A-A in FIG. 3, and FIG. 1 (B) is a sectional view taken along the line B-B in FIG. As shown, this DRAM has N number of word lines 20 arranged in the horizontal direction and N number of pins 1 to 21 arranged in the vertical direction which are almost orthogonal to the word line 20. In the vicinity of the orthogonal point between the word line 20 and the B... line 21, there is an island 23 connected via the contact 1 to the hole 22 7.
are arranged in a matrix. Each island 23 is surrounded by a first groove 24 formed in the direction of the bit line 21 and a second groove 25 with a width W2 (>Wl) formed in the direction of the word line 20. They are separated from each other in a certain way. A capacitor that also serves as isolation is buried inside these Q4424.25, and a HO
3) A transistor is formed. These capacitors and 1 (cross section of OS transistor) f1vJ structure are shown in Figure 1 (
In FIG. 1, a [ ) type semiconductor substrate 3 made of SIS is shown in A) and (B).
0 has the 1st. A second channel 24.25 is formed, and a channel stop 31 is formed below each groove 24.25.
]〇- A capacitor insulating film 32 made of an oxide film such as 5HO2 is formed on the lower wall surface of the valley groove 24.25, and a conductive film made of polycrystalline Si etc. is further formed inside the insulating film 32. For example, in one first filler 24 in FIG. A plate 33 and a substrate 30, on which a capacitor is formed, also sandwich an insulating film 32 on the left side wall.
The left capacitor is formed. Also in the single second loop 25 in FIG. 1(8), capacitors are formed on the right and left sides of the loop 25, respectively.

The upper wall surface within the valley groove 24.25 and its valley groove 24.25
A gate insulating film 34 made of an oxide film such as SiO2 is formed around the upper end opening, and a polycrystalline film is formed inside the gate insulating film 34 in the valley grooves 24° 25 in a manner surrounding each island 23. A gate electrode 35 made of Si or the like is formed. Here, in one first trench 24 in FIG. 1(A), the gate electrode 35 formed on the gate insulating film 34 on the right side wall is connected to the gate electrode of the right MOS transistor on the left side wall. Gate insulating film 3
The gate electrodes 35 formed on the left side) HO8) constitute the gate electrodes of the transistors on the left side, respectively.These left and right gate electrodes 35.35 are interconnected and
It constitutes the word line 20 in the figure. On the other hand, in the eleven second grooves 25 in FIG. The sidewall electrode 35 of the left HOS transistor formed on the gate insulating film 34 on the wall surface is separated from each other. Furthermore, an N+ type source/drain layer 36 is formed below the insulation film 34 on the surface side of the substrate 30. These gate insulating films 34. The gate electrode 35 and the 'source train layer 36 constitute a HO21 helangistor.

Further, on the surface of the substrate 30 from the goo 1 to the insulating film
A 6-bit line 21 on which an intermediate insulating film 37 such as O2 and a bit line 21 such as A are deposited is connected to a source/drain layer 36 through a contact hole 22. A protective film 38 is deposited on the bit line 21 to protect it.

FIG. 4 is a wiring diagram of FIG. 3. At each intersection of a plurality of word lines 20 and bit lines 21, a) HO8) transistor TR and a capacitor C are connected in series to the bit line 21, and the gate electrode of the transistor TR is connected to the word line. There is.

In the above configuration, one of the word lines 20 is selected, it is set to H or L level, the HOS transistor TR is turned on, and the level on the line 21 is written to the capacitor C. The charge accumulated in the capacitor C is read onto the bit line 21.

According to the DRAM of this embodiment, a channel stopper 31 having an isolation function, a capacitor C, and a transistor TR (803) having an isolation function are arranged in the vertical direction of the first and second grooves 24 and 25 so as to surround the island 23. Because of this, the mounting area of each memory cell can be significantly reduced.

FIG. 5 is a capacitance value characteristic diagram of the capacitor C, where the horizontal axis is the depth of the capacitor C (μm), and the vertical axis is the capacitance value (fF) of the capacitor C. The capacitance value of capacitor C increases almost in proportion to its depth. Second Lecture 24
．． If the depth of the capacitor C is 4 μm, and the depth of the HOS transistor TR is 1 μm, then the depth of the capacitor C is 3 μm, and the capacitance value at that time is about 60 fF.
Therefore, it can be seen that a sufficient capacitance value can be obtained even when considering the operation of the memory cell and soft errors caused by alpha rays.

Next, the manufacturing process examples in Figures 1-(A) and (B) are shown in Figure 6.
This will be explained with reference to FIGS. (1) to (6). In addition, the left sectional view in FIGS. 6(1) to (6) is shown in FIG. 11(A).
The cross-sectional view on the right side corresponds to the side of FIG. 1(B), respectively.

(a) Process CVD (Chemical Vapor Deposits) in Fig. 6 (1)
A total of 40 SiO2 films 40 for use as a mask are formed on the P-type Si substrate 30 using a method such as ion). next,
Photolithography is performed, and a second iH'124.25 is formed by RTE method or the like. For example, when the depth of 7424.25 is about 4)-tm, the 5H02 film 40 is
,000 to 10,000 people is sufficient.After that,
24. At the bottom of 25, for example, add boron ions 8F + 5~9X1013 ions 7, /d, 20~
Channel stopper 31 by driving at about 40 keV, etc.
form.

(b) Did you thermally oxidize the process substrate 30 in FIG. 6(2)? ? A memory cell insulating film 32 made of S, O2, etc. is formed to a thickness of approximately 100 to 300 layers on the wall surface within the space and on the surface of the S1 substrate 30. This insulating film 32 is formed on a 5jO2 film or the like. A two-layer M structure in which a nitride film or the like is grown by the PcVD method may be used. Then, for example, 1, P
After growing polycrystal 5i41 to a thickness of about 1 μm on the insulating film 32 by the cVD method, impurities are introduced into the polycrystal 5i41 to improve conductivity.

(C) The entire surface is etched to remove the polycrystal 5i41 on the substrate 30 and the upper part in the groove 24.25, and a hole made of the polycrystalline 5i41 is formed in the groove 24.25. rate 33 is formed. At this time, in order to prevent damage to the Si substrate 30 during etching, it is desirable to have a large etching selection ratio between the polycrystalline 5141 and the insulating film 32.

(d) Inside the groove 24, 25 located on the process plate 33 of FIG. 6(4) and the substrate 3
After removing the capacitor insulating film 32 on the substrate 30 by etching, a gate insulating film 34 having a thickness of about 100 to 500 layers is formed on the exposed surface of the substrate 30 by thermal oxidation or the like.

Next, the polycrystalline Si layer that will become the gate electrode is Ho.

A film 42 of metal, silicide, polycide, etc. according to W, Published, pt.
i' Formed on the ridge film 34. (e) Step shown in FIG. 6(5) The entire surface of the pA 42 is etched by RIE method or the like to form the gate insulating film 34 in the grooves 24 and 25. after that,
For example, As+ ions are irradiated from above the substrate 30 at 40 keV.
An N+ type source train layer 36 is formed on the Si substrate 30 by implanting approximately 10X 1016 (cn-2>).

(1') In step 5102 of FIG. 6(6), the intermediate insulating film 37 made of PSG, BPSG, As5G, etc. is heated to about 4,000 to 10,000 OOA.
-16-, -- is grown by CVD method etc., and then the intermediate insulating film 37 and the gate insulating film 34 are grown.
The contact hole 22 is formed at a predetermined location of the ridge, A
, Q, etc. are selectively formed, and a protective film 38 is formed thereon, RA)I as shown in FIG. 1 is obtained.

In the manufacturing method of this embodiment, the plate 33, the gate electrode 35, etc. are formed by self-line, so compared to the conventional method using photolithography, there is no need for alignment margins for masks, etc., and the minimum line width is also the same as that of the Catholic Church. You can make it bigger. For example, even if we use a 1 μm width that can be achieved with current reduction exposure machines, the memory cell size will be about 10 μm, which is equivalent to a 48-bit DRAM.
It can be made into a size that can be mounted on. Further, the two photolithography steps can also be simplified. Note that the semiconductor memory and the method for manufacturing the same according to the present invention are not limited to the illustrated embodiments, and can be modified in various ways. In the above embodiment, the 1 (O3) transistor TR in the 1-transistor type memory cell is an N-channel type, but it can be modified to a P-channel type, or a memory cell having two or more of these 1-IOS transistors. The present invention can also be applied to. Furthermore, the present invention can be applied to other semiconductor memories in which Ho81 to transistors are configured as bipolar transistors or MJ81 to transistors.

(Effects of the Invention) As explained in detail above, according to the first invention, since the capacitor and the transistor are formed in the vertical direction of the first and second sections, the mounting area of the memory cell can be reduced. .

Further, according to the second invention, since the capacitor, gate electrode, etc. are formed by self-line, it is possible to omit two photolithography steps, thereby improving the formation precision and reducing the formation area.

[Brief explanation of the drawing]

1-(A) and (B) are cross-sectional views of a memory cell showing an embodiment of the present invention, FIG. 2 is a cross-sectional view of a conventional memory cell, and FIG. 3 is a semiconductor memory showing an embodiment of the present invention. Figure 4 is the wiring diagram of Figure 3, Figure 5 is the capacitance value characteristic diagram of the capacitor in Figure 1, and Figures (1) to (6) are the manufacturing diagram of Figure 1. It is a process diagram. 20...word line, 21...bit line, 22...curved contact hole, 23...island, 24...first track, 25... ...second anchor,
30...Semiconductor substrate, 31...Curved channel stopper, 32...Capacitor insulating film, 33...
...Plate, 34...Gate insulating film, 35
. . . Gate electrode, 36 . . . Source/drain layer. Applicant's agent: Takashi Kakimoto

Claims (1)

[Claims] 1. A plurality of word lines and bit lines formed on a semiconductor substrate, and a plurality of charge storage capacitors and charges connected to each intersection of these word lines and bit lines and arranged in a matrix. A semiconductor memory comprising a transfer transistor, a plurality of first grooves for separating each of the intersections in the word line direction, and a plurality of second grooves for separating each of the intersections in the bit line direction. a pair of capacitors are provided in the first and second grooves so as to include each of the intersection points, and a pair of the transistors are provided in the first and second grooves so as to surround each of the intersection points. a pair of transistors each extending over the capacitor, and connecting the pair of transistors in the first groove to each other and separating the pair of transistors in the second groove from each other. semiconductor memory. 2. A memory cell insulating film is formed on a semiconductor substrate in which first and second grooves of different widths are formed in a matrix, and a conductive plate film is further formed on the semiconductor substrate, and then the entire surface is etched. forming a plate in the first and second grooves, forming a gate insulating film on the wall surface on the plate in the first and second grooves and on the surface of the semiconductor substrate, and further forming a gate electrode film thereon. and then etching the entire surface to form one of a pair of connected gate electrodes and a pair of separated gate electrodes in the first and second grooves by utilizing the difference in their widths. A method for manufacturing a semiconductor memory, comprising: