JP2809138B2 - Ferroelectric capacitor structure - Google Patents
Ferroelectric capacitor structureInfo
- Publication number
- JP2809138B2 JP2809138B2 JP7164836A JP16483695A JP2809138B2 JP 2809138 B2 JP2809138 B2 JP 2809138B2 JP 7164836 A JP7164836 A JP 7164836A JP 16483695 A JP16483695 A JP 16483695A JP 2809138 B2 JP2809138 B2 JP 2809138B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- ferroelectric
- capacitor
- film
- capacitance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は強誘電体メモリに関し、
特に強誘電体の残留分極を利用する不揮発性メモリに関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory,
In particular, the present invention relates to a nonvolatile memory utilizing remanent polarization of a ferroelectric.
【０００２】[0002]
【従来の技術】強誘電体メモリに用いられる強誘電体容
量は、図２（ａ）に示すように白金等からなる下部電極
２１上に強誘電体３を成膜しその上に上部電極２２を形
成するタイプのものが用いられている（Ｗ．Ｉ．ＫＩＮ
ＮＥＹ他 ＩＥＤＭ ８７ Ｔｅｃｈ．ｄｉｇ．ｐｐ８
５０）。2. Description of the Related Art As shown in FIG. 2A, a ferroelectric capacitor used in a ferroelectric memory is formed by forming a ferroelectric film 3 on a lower electrode 21 made of platinum or the like, and forming an upper electrode 22 thereon. Is used (WIKIN).
NEY et al. IEDM 87 Tech. dig. pp8
50).
【０００３】半導体基板２０上にＭＯＳトランジスタを
形成し、その後層間絶縁膜２３を形成する。ゲート電極
２６はワード線に、ソース２８はビット線になる。その
上に導体膜パターンを形成して容量の下部電極を兼ねる
駆動線２１とし、駆動線２１上に強誘電薄膜３を堆積
し、その上に上部電極２２を形成する。さらに層間絶縁
膜２４を全面に堆積し、上部電極２２及びドレイン上の
層間絶縁膜２３、２４を開口してＡｌ配線２９で接続す
る（図２（ｂ））。[0005] A MOS transistor is formed on a semiconductor substrate 20 and then an interlayer insulating film 23 is formed. The gate electrode 26 becomes a word line, and the source 28 becomes a bit line. A conductive film pattern is formed thereon to form a drive line 21 also serving as a lower electrode of a capacitor. The ferroelectric thin film 3 is deposited on the drive line 21, and an upper electrode 22 is formed thereon. Further, an interlayer insulating film 24 is deposited on the entire surface, and the upper electrode 22 and the interlayer insulating films 23 and 24 on the drain are opened and connected by an Al wiring 29 (FIG. 2B).
【０００４】[0004]
【発明が解決しようとする課題】ところが、メモリの集
積度が高くなりそれに伴ってメモリセル面積が縮小され
ると、データ読み出しの際に強誘電体の分極反転により
流れ出る電荷量が小さくなり、検出限界量を下回る事が
考えられる。However, when the degree of integration of the memory is increased and the area of the memory cell is reduced accordingly, the amount of charge flowing out due to the polarization reversal of the ferroelectric during data reading is reduced, and the detection amount is reduced. It may be below the limit.
【０００５】電荷量とセル容量の面積とは比例関係にあ
るので、必要電荷量を確保するためには、ある一定の面
積を確保する事が必要である。ＤＲＡＭでは図３に示す
ように、スタック電極３１の側壁にも容量絶縁膜３３と
プレート電極３２を形成することで容量面積を確保する
構造を用いている。しかし、強誘電体容量の特性は強誘
電体膜の結晶方位に依存し、更にその結晶方位は下部電
極の結晶方位に依存するので、このＤＲＡＭの技術をそ
のまま用いることができない。Since the charge amount and the area of the cell capacitance are in a proportional relationship, it is necessary to secure a certain area in order to secure the required charge amount. In the DRAM, as shown in FIG. 3, a structure is used in which a capacitance insulating film 33 and a plate electrode 32 are also formed on the side wall of the stack electrode 31 to secure a capacitance area. However, the characteristics of the ferroelectric capacitor depend on the crystal orientation of the ferroelectric film, and furthermore, the crystal orientation depends on the crystal orientation of the lower electrode, so that the DRAM technology cannot be used as it is.
【０００６】本発明の目的は、メモリセル面積が縮小さ
れた場合にも、データ読み出しに必要な面積を有するセ
ル容量を提供することにより、強誘電体メモリの高集積
化を可能にすることにある。An object of the present invention is to provide a cell capacitor having an area necessary for data reading even when the memory cell area is reduced, thereby enabling high integration of a ferroelectric memory. is there.
【０００７】[0007]
【課題を解決するための手段】本発明にかかる強誘電体
容量は、容量電極を何層にも重ねそれぞれの電極上に強
誘電体薄膜を成膜し、１層おきにそれぞれの電極を接続
するという多層構造の容量にすることにより、強誘電体
薄膜の結晶方位をそろえたまま、メモリセル面積を増大
させずに容量面積を増大することができる。According to the ferroelectric capacitor of the present invention, a plurality of capacitor electrodes are stacked, a ferroelectric thin film is formed on each electrode, and the electrodes are connected every other layer. In this case, it is possible to increase the capacity area without increasing the memory cell area while keeping the crystal orientation of the ferroelectric thin film aligned.
【０００８】[0008]
【実施例】半導体基板上に、ＭＯＳトランジスタ等のデ
バイス（図示せず）を形成する。その上に層間絶縁膜を
堆積し、トランジスタのドレイン上の層間絶縁膜を除去
し、コンタクトホールを開口する。その上にＴｉＮや、
Ｗ等の高融点金属膜、あるいはそのシリサイド膜を堆積
し、その上にＰｔ膜を堆積する。その後パターニングし
て図１（ａ）の容量電極１−１とする。DESCRIPTION OF THE PREFERRED EMBODIMENTS A device (not shown) such as a MOS transistor is formed on a semiconductor substrate. An interlayer insulating film is deposited thereon, the interlayer insulating film on the transistor drain is removed, and a contact hole is opened. On top of that, TiN
A high melting point metal film such as W or a silicide film thereof is deposited, and a Pt film is deposited thereon. Thereafter, patterning is performed to obtain the capacitor electrode 1-1 in FIG.
【０００９】次に、容量電極１−１上にＰＺＴ、ＰＬＺ
Ｔ、あるいはＰｂＴｉＯ3 等の強誘電体薄膜３を形成す
る。次いでＰｔ膜を堆積し、パターニングする。このと
き容量電極１−１と１−２を接続させるためのＰｔプラ
グ配線１１−１を貫通させるための開口部も形成してお
く。このようにして容量電極２−１を形成する。Next, PZT and PLZ are placed on the capacitance electrode 1-1.
T, or forming a ferroelectric thin film 3, such as PbTiO 3. Next, a Pt film is deposited and patterned. At this time, an opening for penetrating the Pt plug wiring 11-1 for connecting the capacitance electrodes 1-1 and 1-2 is also formed. Thus, the capacitance electrode 2-1 is formed.
【００１０】次に強誘電体薄膜３を堆積し、その上にＰ
ｔ膜を堆積し、パターニングする。このとき容量電極２
−１と２−２を接続するためのＰｔプラグ配線１２−１
を貫通させるための開口部も形成しておく。このように
して容量電極１−２を形成する。Next, a ferroelectric thin film 3 is deposited, and P
A t film is deposited and patterned. At this time, the capacitance electrode 2
Plug wiring 12-1 for connecting -1 and 2-2
An opening for penetrating through is also formed. Thus, the capacitor electrode 1-2 is formed.
【００１１】同様にしてその上層の強誘電体薄膜３、容
量電極１−２、１−３、２−２、プラグ配線１１−２、
１２−２を順次形成する。最上層の容量電極２−３は当
然ながらプラグ配線を貫通させるための開口部は不要で
ある。Similarly, the upper ferroelectric thin film 3, capacitor electrodes 1-2, 1-3, 2-2, plug wiring 11-2,
12-2 are sequentially formed. Of course, the uppermost layer capacitor electrode 2-3 does not require an opening for penetrating the plug wiring.
【００１２】図１（ｂ）は図１（ａ）のＡＡ′の上面図
である。容量電極２−１が開口され、容量電極２−１と
接触しないように絶縁されてプラグ配線１１−１が貫通
している。FIG. 1B is a top view of AA 'in FIG. 1A. The capacitor electrode 2-1 is opened, and the plug wiring 11-1 is insulated so as not to contact the capacitor electrode 2-1 and penetrates.
【００１３】図１（ａ）では奇数番目の電極と偶数番目
の電極をそれぞれ三層ずつ形成した例を示しているが、
二層あるいは四層でもよい。FIG. 1A shows an example in which three odd-numbered electrodes and three even-numbered electrodes are formed.
Two or four layers may be used.
【００１４】一般にｎ層形成した場合、容量電極１−ｎ
と１−（ｎ＋１）とはプラグ配線１１−ｎで接続し、容
量電極２−ｋと２−（ｋ＋１）とはプラグ配線１２−ｋ
で接続する。またプラグ配線１１−ｎと容量電極２−
ｎ、及びプラグ配線１２−ｋと容量電極１−（ｋ＋１）
とはそれぞれ互いに絶縁されている。Generally, when an n-layer is formed, the capacitance electrode 1-n
And 1- (n + 1) are connected by a plug wiring 11-n, and the capacitance electrodes 2-k and 2- (k + 1) are connected by a plug wiring 12-k.
Connect with. The plug wiring 11-n and the capacitor electrode 2-
n, plug wiring 12-k and capacitance electrode 1- (k + 1)
Are insulated from each other.
【００１５】以上説明した容量構造によればそれぞれの
電極上に成膜される強誘電体薄膜の配向は図２に示した
従来の強誘電体容量構造と同じになり、しかも積層され
ているので、読み出し電荷は面積の増大に応じて増加す
る。According to the above-described capacitor structure, the orientation of the ferroelectric thin film formed on each electrode is the same as that of the conventional ferroelectric capacitor structure shown in FIG. The read charge increases as the area increases.
【００１６】[0016]
【発明の効果】以上説明したように、積層構造強誘電体
容量を用いることにより、強誘電体の配向をそろえたま
ま、メモリセル面積を増大させずに容量面積を増大する
ことが可能となり、メモリを高集積化してメモリセル面
積を縮小した場合にも、メモリ動作に必要な電荷量を確
保することが出来る。As described above, by using a ferroelectric capacitor having a laminated structure, it is possible to increase the capacitance area without increasing the memory cell area while keeping the ferroelectric orientation uniform. Even when the memory is highly integrated and the memory cell area is reduced, the amount of charge required for the memory operation can be ensured.
【図１】本発明の第１の実施例の説明図である。FIG. 1 is an explanatory diagram of a first embodiment of the present invention.
【図２】従来技術の説明図である。FIG. 2 is an explanatory diagram of a conventional technique.
【図３】ＤＲＡＭに用いられている従来技術の説明図で
ある。FIG. 3 is an explanatory diagram of a conventional technique used for a DRAM.
１ 容量電極１ ２ 容量電極２ ３ 強誘電体薄膜 ４ 層間絶縁膜 １１ プラグ配線１ １２ プラグ配線２ ２０ 半導体基板 ２１ 下部電極 ２２ 上部電極 ３１ スタック電極 ３２ プレート電極 ３３ 容量絶縁膜 REFERENCE SIGNS LIST 1 capacitor electrode 1 2 capacitor electrode 2 3 ferroelectric thin film 4 interlayer insulating film 11 plug wiring 1 12 plug wiring 2 20 semiconductor substrate 21 lower electrode 22 upper electrode 31 stack electrode 32 plate electrode 33 capacitance insulating film
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０１Ｌ 27/108 29/788 29/792 (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 27/10 451 H01L 21/822 H01L 21/8242 H01L 21/8247 H01L 27/04 H01L 27/108 H01L 29/788 H01L 29/792──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 identification code FI H01L 27/108 29/788 29/792 (58) Investigated field (Int.Cl. 6 , DB name) H01L 27/10 451 H01L 21/822 H01L 21/8242 H01L 21/8247 H01L 27/04 H01L 27/108 H01L 29/788 H01L 29/792
Claims (1)
互に形成し、奇数番目の電極と偶数番目の電極をそれぞ
れコンタクトプラグで接続し、奇数番目および偶数番目
の電極を接続するコンタクトプラグをそれぞれ偶数番目
および奇数番目の電極に設けられた開口部を貫通するよ
うに配置したことを特徴とする強誘電体容量構造。1. A formed alternately electrode and the ferroelectric thin film on the interlayer insulating film, connects the odd-numbered electrodes and even-numbered electrodes in each contact plug, odd and even
Contact plugs that connect the
And through the openings provided in the odd-numbered electrodes.
A ferroelectric capacitor structure characterized by being arranged as follows .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7164836A JP2809138B2 (en) | 1995-06-30 | 1995-06-30 | Ferroelectric capacitor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7164836A JP2809138B2 (en) | 1995-06-30 | 1995-06-30 | Ferroelectric capacitor structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0917970A JPH0917970A (en) | 1997-01-17 |
| JP2809138B2 true JP2809138B2 (en) | 1998-10-08 |
Family
ID=15800854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7164836A Expired - Fee Related JP2809138B2 (en) | 1995-06-30 | 1995-06-30 | Ferroelectric capacitor structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2809138B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5461128B2 (en) * | 2009-09-18 | 2014-04-02 | 日本電信電話株式会社 | Stacked MIM capacitor and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0770684B2 (en) * | 1985-04-23 | 1995-07-31 | 工業技術院長 | Capacitors for semiconductor integrated circuits |
| JPH05190797A (en) * | 1992-01-08 | 1993-07-30 | Seiko Epson Corp | Semiconductor memory device |
-
1995
- 1995-06-30 JP JP7164836A patent/JP2809138B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0917970A (en) | 1997-01-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980630 |
|
| LAPS | Cancellation because of no payment of annual fees |