JPH0575057A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase the capacitance of a cell capacitor by forming a bit line, reverse bit line and a word line below a capacitor electrode. CONSTITUTION:A bit line 10, a reverse bit line 11 and word line (gate electrode) 5 are formed below the lower electrode 14 of the capacitor. Therefore, the area of a lower electrode 14 and an upper electrode 15 of the capacitor is not limited by the bit line 10 and reverse bit line 11, so that the capacitor can be formed all over the area for the memory cell except processing margin and aligning margin. By doing this, a larger capacitance for the capacitor can be obtained even if the cell area is the same.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
More specifically, the present invention relates to a semiconductor memory device including two transistors and one capacitor in terms of an equivalent circuit.

[0002]

2. Description of the Related Art The simplest dynamic RAM in the past
As such, there is known a dynamic RAM composed of one transistor and one capacitor as shown in FIGS. This turns on the gate with a transistor
By turning off, the charge amount of the capacitor is changed and the data is stored in an arbitrary memory cell.

FIG. 11 is a cross-sectional view showing a DRAM cell. This DRAM cell has a capacitor sandwiching a thin film having a large dielectric constant in order to increase the capacitance per area. In the figure, (1) shows a silicon substrate, and by forming an element isolation region (2), a sidewall is formed through an oxide film (4) on the silicon substrate (1) in which an element formation region is secured. A gate electrode (5) is formed together with (6). The gate electrode (5) is provided as a word line on the silicon substrate (1). Source / drain regions (3) are formed at both ends of the gate electrode (5) on the surface layer of the silicon substrate (1). A capacitor lower electrode (64) having a contact with the source / drain region (3) extends over the gate electrode (5), the source / drain region (3) and the element isolation region (2) to form an insulating film (8). The capacitor upper electrode (65) is laminated on the capacitor lower electrode (64) through the dielectric (66). Further, an interlayer insulating film (67) is formed on the capacitor upper electrode (65).
Are stacked. Also, the capacitor lower electrode (64)
The source / drain region (3) opposite to the source / drain region (3) having a contact with the bit line (6
0) is connected.

[0004]

In the above semiconductor memory device, it is necessary to increase the capacitance of the capacitor in order to hold the charge accumulated in the capacitor.
Since there is a trade-off between increasing the cell capacitance and reducing the cell size, there has been a problem that various measures are required to reduce the size of the cell.

Further, as shown in FIGS. 10 and 11,
The upper and lower electrodes (64, 65) of the capacitor are connected to the bit line (6
0), the capacitor upper and lower electrodes (64, 65) cannot be located outside the bit line (60), and the area of the capacitor upper and lower electrodes (64, 65) with respect to the memory cell is bit. There was the problem of being limited by the line (60) and the inverted bit line (not shown).

Further, when one memory cell is composed of two transistors / one capacitor, the source / drain formed on the silicon substrate (1) in order to connect the transistor and the capacitor inside the memory cell. It is necessary to connect the region (3) and the capacitor upper electrode (65), and the capacitor insulating film (66) and the capacitor upper electrode (65) must be processed in the memory cell. However, when a ferroelectric film containing a Pb component is used as the capacitor insulating film (64), it is difficult to process the ferroelectric film by RIE and there is a problem in manufacturing technology. ..

The present invention has been made in view of the above problems, and an object of the present invention is to provide a highly reliable semiconductor memory device capable of obtaining a larger capacitor capacitance even with the same cell area.

[0008]

According to the present invention, there is provided a semiconductor memory device having a bit line, an inverted bit line and a word line, wherein one memory cell is composed of two transistors and one capacitor. There is provided a semiconductor memory device in which a capacitor includes a capacitor upper electrode, a capacitor insulating film, and a capacitor lower electrode, and the bit line, an inverted bit line, and a word line are formed below the lower electrode of the capacitor.

Further, a semiconductor memory device in which one memory cell is composed of two transistors and two capacitors and has a bit line, an inverted bit line and a word line,
The capacitor includes a capacitor upper electrode, a capacitor insulating film, and a capacitor lower electrode. The two upper electrodes of the capacitor and the two capacitor insulating films of the capacitor are integrally formed, and the capacitor further includes the capacitor. There is provided a semiconductor memory device in which the bit line, the inverted bit line and the word line are arranged below the lower electrode of the.

A paraelectric film can be used as the capacitor insulating film of the capacitor constituting the semiconductor device of the present invention, but a ferroelectric film such as PZT or PLZT is preferable. The film thickness is preferably 50 to 3000 Å. Further, by forming the capacitor on the transistor, the word line is arranged below the capacitor.

Further, in the present invention, Pt, W, Ti and Ti are used as the capacitor lower electrode and the capacitor upper electrode.
W, TiN and each silicide can be used,
The film thicknesses of the capacitor lower electrode and the capacitor upper electrode are preferably 1000 to 5000Å and 500 to 2000Å, respectively. Moreover, polysilicon, silicide, or the like can be used as the gate electrode, and the film thickness thereof is 500 to 25.
00Å is preferable, and polysilicon, silicide, W, Ti, Al-Si are used as the bit line and the inverted bit line.
Can be used, and the film thickness is 1000-
4000Å is preferred.

Further, as the oxide film, a SiO ₂ film, S
An iO ₂ / SiN film or the like can be used, and the film thickness thereof is preferably 500 to 5000 Å.

[0013]

According to the above structure, since the bit line, the inverted bit line and the word line are formed below the lower electrode of the capacitor, the area of the lower electrode and the upper electrode of the capacitor is limited by the bit line and the inverted bit line. Without being processed, the capacitor is formed to fill the cell area excluding the processing margin and the alignment margin for the memory cell, and a larger capacitor capacity can be obtained.

Also, the two upper electrodes and 2 of the capacitor
When the two capacitor insulating films are integrally formed, a memory for connecting the source / drain regions formed on the semiconductor substrate and the capacitor upper electrode in order to connect the transistor and the capacitor. It is not necessary to process the capacitor insulating film which is the ferroelectric film and the upper electrode in the cell, and the manufacturing yield and reliability are improved. At this time, the first capacitor and the second capacitor shown in FIG. 8 can be considered as substantially one capacitor.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a DRAM including a transistor and a capacitor according to the present invention will be described with reference to the drawings. It should be noted that components having the same functions as those of the conventional example are designated by the same reference numerals. As shown in FIGS. 1 and 2, in the DRAM of the present embodiment, (1) indicates a silicon substrate, and the element isolation region (2) is formed to secure the element formation region. Source / drain regions (3) are formed in the surface layer of the substrate (1). In addition, on the silicon substrate (1), the source / drain region (3) and the source / drain region (3)
And a gate electrode (5) on which a sidewall (6) is formed is laminated via a SiO ₂ film (4) as a gate oxide film, and a first electrode is formed on the gate electrode (5).
SiO ₂ film (7) is formed. Further, these silicon substrate (1), gate electrode (5) and first SiO 2
_{A second} SiO ₂ film (8) is laminated on the ₂ film (7). A bit line (10) is connected and formed on one of the source / drain regions (3), and a third SiO 2 layer is further formed on the gate electrode (5) and the bit line (10).
_Two films (9) are formed. Further, on the third SiO ₂ film (9), the source / bit connected to the bit line (10)
A capacitor lower electrode (14) connected on the source / drain region (3) opposite to the drain region (3),
It is formed from the gate electrode (5) to the bit line (10). Further, as a capacitor insulating film, for example, a PZT film (16) is formed on the capacitor lower electrode (14).
The capacitor upper electrode (15) is laminated via the. Therefore, as shown in FIG. 3, the two transistors (12) and (13) and one capacitor (21) form one capacitor.
A memory cell is formed, and a bit line (10), an inverted bit line (11) and a word line (gate electrode (5)) are formed below the capacitor lower electrode (14).

Next, a method of manufacturing the DRAM thus configured will be described with reference to FIGS. FIG. 4 is a schematic sectional view taken along the line AA ′ in FIG. 1, and FIG.
It is a B'line schematic sectional drawing. First, a LOCOS element isolation region (2) is formed on a P-type silicon substrate (1), and then a gate oxide film of 80 to 12 is formed by a known method.
A SiO ₂ film (4) having a thickness of 0 Å and polysilicon, for example, 1000 Å and a SiO ₂ film 1000 Å are sequentially deposited, and a gate electrode (5) and a first SiO ₂ film (7) are formed by a photoetching process. Form. Then, using the gate electrode (5) and the first SiO ₂ film (7) as a mask, for example, P is ion-implanted at a concentration of about 1 × 10 ¹³ cm ⁻² to form the source / drain regions (3). .. After that, about 1500 Å SiO ₂ is laminated on the gate electrode (5) and the first SiO ₂ film (7), and by RIE,
A sidewall (6) is formed on the gate electrode (5) and the first SiO ₂ film (7) (FIGS. 4A and 5).
(A)).

Then, a second S is formed on the silicon substrate (1).
After depositing about 1000Å of the iO ₂ film (8), the contact portion (19) between the bit line (10) and the first transistor (12), the inverted bit line (11) and the second transistor (13) are formed. The contact part (20) is opened by photoetching. Then, for example, polysilicon is laminated on the silicon substrate (1) and etched by a known method to form the bit line (10) and the inverted bit line (11). Furthermore, these bit lines (10),
A third SiO ₂ film (9) is laminated on the inverted bit line (11) and the gate electrode (5) to a thickness of about 1000Å (FIG. 4).
(B) and FIG. 5 (b)).

Then, the third SiO ₂ film (9) and the second
A contact portion (17) between the first transistor (12) and a capacitor lower electrode (14) formed in a later step is opened in the SiO ₂ film (8) of FIG.
(C)), and W on it, for example, 1500-3000
After depositing about Å, a desired capacitor lower electrode (14) is formed by a photo etching process. Further, a PZT film (16) having a thickness of about 1000Å is laminated on the capacitor lower electrode (14) as a capacitor insulating film. Then, the PZT film (16), the third SiO ₂ film (9) and the second SiO ₂ film (8) are contacted with the second transistor (13) and the capacitor upper electrode (15) formed in a later step. The part (18) is opened by a photoetching process (FIG. 5C), and W is further added to 1500 to 3000.
The capacitor upper electrode (15) is formed by stacking about Å and etching by the same method as above.

Thereafter, an NSG (not shown) as an interlayer insulating film and a BPSG (not shown) as an interlayer insulating film are laminated on the capacitor upper electrode (15) by about 1500 Å, and about 6000 Å, respectively.
A memory cell is formed. In the above embodiment,
The contact portion (19) between the first transistor (12) and the bit line (10) and the contact portion (20) between the second transistor (13) and the inverted bit line (11) are connected to the word line (5). Although the case where the first transistor (1) and the first transistor (1
2) and the capacitor lower electrode (14) contact part (17), the second transistor (13) and the capacitor upper electrode (15) contact part (18), the first transistor (12) and the bit line. The contact portion (19) with (10) and the contact portion (20) with the second transistor (13) and the inverted bit line (11) may be arranged opposite to the word line (5). .. Also, for example,
As shown in FIG. 6, a contact portion (19) between the first transistor (12) and the bit line (10) and a contact portion (20) between the second transistor (13) and the inverted bit line (11). ) And may be arranged on different sides with respect to the word line (5).

Next, another embodiment will be described with reference to FIGS.
It will be explained based on. 7 is different from the above embodiment.
And as shown in FIG.
a, 34b) is formed by being divided into two over almost the entire memory cell. D configured in this way
The RAM will be described with reference to FIG.

Similar to the above embodiment, the source / drain regions (3) are formed on the surface layer of the silicon substrate (1),
On the silicon substrate (1), in order, a SiO ₂ film (4), a gate electrode (5), a first SiO ₂ film (7), a sidewall (6), a second SiO ₂ film (8), and a bit. Line (1
0) and a third SiO ₂ film (9) are laminated (FIG. 4).
(A), (b)).

Then, as in the above embodiment, a contact portion (47) between the first transistor (12) and the capacitor lower electrode (34a) which will be formed in a later step, and a second transistor (13) which will be formed in a later step. Lower electrode of capacitor (3
4b) is opened by a photo-etching process in the contact part (48) (FIG. 4 (c)), and then, for example, W is deposited to about 1500 to 3000 Å in the same manner as in the above embodiment, and then photo-etching is performed. The first capacitor lower electrode (34a) and the second capacitor lower electrode (3
4b) is formed (FIG. 4 (c)).

Then, the first capacitor lower electrode (34
a) and on the second capacitor lower electrode (34b) and substantially over the entire memory cell, as in the above embodiment.
Laminate the membranes (16). Then, W is further deposited on the PZT film (16) to a thickness of about 1500 to 3000 Å and etched by the same method as described above to form the capacitor upper electrode (15). At this time, P in the memory cell
It is not necessary to etch the ZT film (16).

Thereafter, an NSG (not shown) as an interlayer insulating film and a BPSG (not shown) as an interlayer insulating film are laminated on the capacitor upper electrode (15) to a thickness of about 6000 Å, respectively.
A memory cell is formed. In the above embodiment,
The contact portion (49) between the first transistor (12) and the bit line (10) and the contact portion (50) between the second transistor (13) and the inverted bit line (11) are connected to the word line (5). Although the case where the first transistor (1) and the first transistor (1
2) and the contact portion (47) between the first capacitor lower electrode (34a) and the second transistor (13)
Of the capacitor lower electrode (34b) of the
8), the first transistor (12) and the bit line (1
0) and a contact portion (5) between the second transistor (13) and the inverted bit line (11).
0) may be arranged opposite to the word line (5). Further, for example, as shown in FIG. 9, the contact portion (49) between the first transistor (12) and the bit line (10), the second transistor (13) and the inverted bit line (11) are formed. The contact portion (50) and the contact portion (50) may be arranged on different sides with respect to the word line (5).

[0025]

According to the semiconductor memory device of the present invention,
Since the bit line, the inverted bit line, and the word line are formed below the lower electrode of the capacitor, the area of the lower electrode and the upper electrode of the capacitor is not limited by the bit line and the inverted bit line. Processing allowance,
A capacitor can be formed to fill the cell area excluding the alignment margin, and a larger capacitor capacity can be obtained. In addition, the capacitor manufacturing
Since it can be performed after the formation of the inverted bit line and the word line, even if the ferroelectric film that is relatively weak to a high temperature is used as the capacitor insulating film, the processing temperature after forming the capacitor insulating film is higher than the processing temperature at the time of forming the ferroelectric film. It is not necessary to perform heat treatment, and it is possible to prevent deterioration of the characteristics of the ferroelectric film.

Further, when the two upper electrodes of the capacitor and the two capacitor insulating films are integrally formed, in order to connect the source / drain regions formed on the semiconductor substrate to the upper electrodes of the capacitors. ,
It is not necessary to process the capacitor insulating film, which is a ferroelectric film, and the upper electrode in the memory cell, and a semiconductor memory device having high reliability can be manufactured with high yield.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a schematic sectional view of the semiconductor memory device in FIG.

FIG. 3 is an equivalent circuit diagram of the semiconductor memory device in FIG.

FIG. 4 is a schematic cross-sectional view taken along the line AA ′ in FIG. 1 for explaining the manufacturing process of the semiconductor memory device according to the present invention.

FIG. 5 is a schematic cross-sectional view taken along the line BB ′ in FIG. 1 for explaining the manufacturing process of the semiconductor memory device according to the present invention.

FIG. 6 is a plan view showing another embodiment of the semiconductor memory device according to the present invention.

FIG. 7 is a plan view showing still another embodiment of the semiconductor memory device according to the present invention.

8 is an equivalent circuit diagram of the semiconductor memory device in FIG.

FIG. 9 is a plan view showing still another embodiment of the semiconductor memory device according to the present invention.

FIG. 10 is a plan view showing a conventional semiconductor memory device.

11 is a schematic cross-sectional view taken along the line AA ′ in FIG.

[Explanation of symbols]

 5 gate electrode (word line) 10 bit line 11 inverted bit line 12 first transistor 13 second transistor 14 capacitor lower electrode 15 capacitor upper electrode 16 PZT film (capacitor insulating film) 21 capacitor 31a first capacitor 31b second capacitor 34a second First capacitor lower electrode 34b Second capacitor lower electrode

Claims (3)

[Claims] 1. A semiconductor memory device comprising a memory cell including two transistors and one capacitor, and having a bit line, an inverted bit line and a word line, wherein the capacitor is a capacitor upper electrode, a capacitor insulating film and A semiconductor memory device comprising a lower electrode of a capacitor, and the bit line, an inverted bit line and a word line are formed below the lower electrode of the capacitor. 2. A semiconductor memory device comprising a memory cell composed of two transistors and two capacitors and having a bit line, an inverted bit line and a word line, wherein the capacitor comprises a capacitor upper electrode, a capacitor insulating film and a capacitor insulating film. The capacitor upper electrode is formed by integrating the two capacitor upper electrodes and the two capacitor insulating films, and the bit line, the inverted bit line, and the word line are further below the capacitor lower electrode. A semiconductor memory device comprising: 3. The semiconductor memory device according to claim 1, wherein a ferroelectric film is used as the capacitor insulating film.