JPH0590532A - Semiconductor storage device - Google Patents
Semiconductor storage deviceInfo
- Publication number
- JPH0590532A JPH0590532A JP24771491A JP24771491A JPH0590532A JP H0590532 A JPH0590532 A JP H0590532A JP 24771491 A JP24771491 A JP 24771491A JP 24771491 A JP24771491 A JP 24771491A JP H0590532 A JPH0590532 A JP H0590532A
- Authority
- JP
- Japan
- Prior art keywords
- ferroelectric
- capacitor
- gate electrode
- electrode
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 30
- 239000003990 capacitor Substances 0.000 claims abstract description 34
- 230000005669 field effect Effects 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 54
- 239000000758 substrate Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 8
- 239000010409 thin film Substances 0.000 claims description 8
- 239000000126 substance Substances 0.000 abstract description 13
- 230000010287 polarization Effects 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 19
- 238000000034 method Methods 0.000 description 17
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 11
- 239000011229 interlayer Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000001066 destructive effect Effects 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical compound [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- -1 and among them Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005621 ferroelectricity Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000011780 sodium chloride Substances 0.000 description 1
- 238000003980 solgel method Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/223—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using MOS with ferroelectric gate insulating film
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
Landscapes
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体記憶素子に関す
る。さらに詳しくは、強誘電体キャパシタを使用した非
破壊読み出しが可能な半導体記憶素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. More specifically, it relates to a non-destructive readable semiconductor memory element using a ferroelectric capacitor.
【０００２】[0002]
【従来の技術】従来より提案されている強誘電体キャパ
シタを使用した半導体記憶素子としては大きく分ける
と、１つのセルに１つのトランジスタと１つのキャパシ
タを有するタイプ（以下、１Tr・１Capa／１cellタイプ
という）と金属膜・強誘電体膜・半導体層（以下、MFS
という）構造がある。2. Description of the Related Art A semiconductor memory device using a ferroelectric capacitor proposed hitherto is roughly classified into a type having one transistor and one capacitor in one cell (hereinafter, referred to as 1Tr · 1Capa / 1cell type). And metal film / ferroelectric film / semiconductor layer (hereinafter MFS)
There is a structure.
【０００３】このうち１Tr・１Capa／１cellタイプのも
のは図12〜13に示されるように強誘電体キャパシタ１と
MOSFETのソースまたはドレインとを接続したものであ
る。なお、図12〜13において、２は強誘電体、３は下部
電極、４は拡散層、５はゲート電極、６は第１層間絶縁
膜、７は第２層間絶縁膜、８はAl配線層、９はフィール
ド酸化膜である。Of these, the 1Tr / 1Capa / 1cell type is a ferroelectric capacitor 1 as shown in FIGS.
It is connected to the source or drain of the MOSFET. 12 to 13, 2 is a ferroelectric, 3 is a lower electrode, 4 is a diffusion layer, 5 is a gate electrode, 6 is a first interlayer insulating film, 7 is a second interlayer insulating film, and 8 is an Al wiring layer. , 9 are field oxide films.
【０００４】この方式のものは、図14に示される強誘電
体のヒステリシスにおいて、ＡまたはＢの状態を判定す
るために一度Ｃまで電界がかけられる。そして、そのと
き流れる電流によりＡまたはＢを判定するものである。In this system, an electric field is once applied up to C in order to judge the state of A or B in the hysteresis of the ferroelectric substance shown in FIG. Then, A or B is determined by the current flowing at that time.
【０００５】つぎにMFS 構造は、図15に示されるよう
に、半導体基板12上に直接強誘電体膜11を形成し、該強
誘電体膜11の分極反転電荷により下部の半導体に反転層
を形成するというものである。なお図15において、10は
ゲート電極、13は不純物拡散領域でゲート領域とソース
領域を構成する。Next, in the MFS structure, as shown in FIG. 15, a ferroelectric film 11 is directly formed on a semiconductor substrate 12, and an inversion layer is formed on a semiconductor below by a polarization inversion charge of the ferroelectric film 11. It is to form. In FIG. 15, 10 is a gate electrode, and 13 is an impurity diffusion region which constitutes a gate region and a source region.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、前述し
た強誘電体を使用した半導体記憶素子のうち１Tr・１Ca
pa／１cellタイプのものは、破壊読み出しであるうえ
に、ＡまたはＢを判定するために必要とされる残留分極
が比較的大きい（Capa面積が１μｍ2 のとき、約10μC/
cm2 は必要とされている）という問題がある。However, among the semiconductor memory elements using the above-mentioned ferroelectric, 1Tr.1Ca is used.
The pa / 1 cell type is not only destructive read-out, but also has a relatively large remanent polarization required to judge A or B (when the Capa area is 1 μm 2 , it is about 10 μC /
cm 2 is needed).
【０００７】一方、MFS 構造は、蓄積電荷量ではなく蓄
積電荷密度を必要とするため、電極面積を広く取る必要
がなく、したがって要求される残留分極も約１μC/cm2
以下と比較的小さい。On the other hand, since the MFS structure requires the accumulated charge density rather than the accumulated charge amount, it is not necessary to take a large electrode area, and therefore the required remanent polarization is about 1 μC / cm 2
It is relatively small as below.
【０００８】しかしながら、半導体基板上に直接性質の
異なる強誘電体膜を形成するのは困難であり、このため
Ｆ／Ｓの界面に SiO2 などのバッファ層を設けることが
提案されている（特開昭50-57345号公報参照）。However, it is difficult to directly form a ferroelectric film having different properties on a semiconductor substrate. Therefore, it has been proposed to provide a buffer layer such as SiO 2 at the F / S interface (special feature). See Kaisho 50-57345).
【０００９】しかし、バッファ層を設けると強誘電体と
バッファ層の積層コンデンサ構造となり、強誘電体にか
かる電圧が低下し、このため印加電圧を大きくしなけれ
ばならなくなるという問題がある。However, when the buffer layer is provided, a laminated capacitor structure of a ferroelectric substance and a buffer layer is formed, and the voltage applied to the ferroelectric substance decreases, so that there is a problem that the applied voltage must be increased.
【００１０】また、この構造では、バッファ層の有無に
かかわらず結晶性の良い強誘電体薄膜をうるのは困難で
ある。Also, with this structure, it is difficult to obtain a ferroelectric thin film having good crystallinity regardless of the presence or absence of a buffer layer.
【００１１】本発明は、叙上の事情に鑑み、前記従来技
術の有する欠点が解消された強誘電体使用の半導体記憶
素子を提供することを目的とする。すなわち本発明の目
的は、非破壊読み出しが可能であり、結晶性の良い強誘
電体膜が形成された半導体記憶素子を提供することであ
る。In view of the above circumstances, it is an object of the present invention to provide a semiconductor memory device using a ferroelectric material, in which the drawbacks of the prior art described above are solved. That is, an object of the present invention is to provide a semiconductor memory element in which a ferroelectric film having non-destructive readability and good crystallinity is formed.
【００１２】[0012]
【課題を解決するための手段】本発明の半導体記憶素子
は、第１導電型の半導体基板表面に間隔をおいて形成さ
れた２つの第２導電型の半導体領域のあいだの前記基板
表面に誘電体薄膜が設けられており、該誘電体薄膜上部
に導電膜が形成されゲート電極とした電界効果型トラン
ジスタと、強誘電体を２つの導電体電極ではさんだ強誘
電体キャパシタとを有するる半導体記憶素子であって、
前記電界効果型トランジスタのゲート電極が前記強誘電
体層をはさむ２つの導電体電極の一方と電気的に接続さ
れており、かつ前記ゲート電極および該ゲート電極と接
続された前記導電体電極に接続された電極端子が導出さ
れてなることを特徴としている。According to another aspect of the present invention, there is provided a semiconductor memory device in which a dielectric layer is formed on a surface of a first conductivity type semiconductor substrate between two second conductivity type semiconductor regions formed at intervals. A semiconductor memory having a body thin film, a field effect transistor having a gate electrode with a conductive film formed on the dielectric thin film, and a ferroelectric capacitor having a ferroelectric sandwiched between two conductor electrodes. An element,
A gate electrode of the field-effect transistor is electrically connected to one of two conductor electrodes sandwiching the ferroelectric layer, and is connected to the gate electrode and the conductor electrode connected to the gate electrode. It is characterized in that the formed electrode terminals are led out.
【００１３】[0013]
【作用】本発明によれば、強誘電体キャパシタをMOSFET
のゲート電極に接続すると共に、接続部から電極端子を
取り出す構成としているため、信号の書き込みにあたっ
ては、強誘電体キャパシタの両電極間に信号電圧を印加
すればよく、低い電圧で書き込みができる。また読み出
しにあたっては強誘電体キャパシタに蓄積された分極電
荷がMOSFETのゲート絶縁膜で形成されたキャパシタに転
送されMOSFETのドレイン、ソース間の導通、非導通状態
で検出でき、分極電荷を破壊しないで簡単に読み出すこ
とができる。According to the present invention, a ferroelectric capacitor is used as a MOSFET.
Since the electrode terminal is connected to the gate electrode of the ferroelectric capacitor and the electrode terminal is taken out from the connection portion, a signal voltage may be applied between both electrodes of the ferroelectric capacitor when writing a signal, and writing can be performed at a low voltage. When reading, the polarization charge stored in the ferroelectric capacitor is transferred to the capacitor formed by the gate insulating film of the MOSFET and can be detected in the conduction or non-conduction state between the drain and source of the MOSFET, without destroying the polarization charge. It can be read easily.
【００１４】さらに本発明によれば、強誘電体膜をMOSF
ETのゲート絶縁膜とは別個に形成するため、強誘電体膜
の下地電極の材質を自由に選択でき結晶性の良い強誘電
体膜を形成できる。Furthermore, according to the present invention, the ferroelectric film is a MOSF.
Since it is formed separately from the gate insulating film of ET, the material of the base electrode of the ferroelectric film can be freely selected and a ferroelectric film with good crystallinity can be formed.
【００１５】[0015]
【実施例】以下、添付図面に基づき本発明の半導体記憶
素子（以下、デバイスという）をさらに詳細に説明す
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device of the present invention (hereinafter referred to as a device) will be described in more detail below with reference to the accompanying drawings.
【００１６】本発明のデバイスの基本構成は、図１に示
されるように強誘電体キャパシタとMOSFETをそれぞれひ
とつずつ含むものである。ただ、従来の１Tr・１Capa／
１cell構造（図12〜13参照）のようにキャパシタとFET
のソースまたはドレインとを接続する構造ではなく、キ
ャパシタとゲート電極とを接続したものである。強誘電
体キャパシタによる蓄積電荷をゲート電極に伝えること
によりMOSFETの導通、非導通状態を切り替えられる。強
誘電体の残留分極による電荷を利用すれば、MOSFETの導
通、非導通状態を“１”、“０”とした不揮発性メモリ
の構成が可能である。The basic structure of the device of the present invention includes one ferroelectric capacitor and one MOSFET, as shown in FIG. However, conventional 1Tr / 1Capa /
Capacitor and FET like 1cell structure (see Figures 12-13)
The structure is not a structure in which the source or the drain is connected, but a capacitor and a gate electrode are connected. The conduction / non-conduction state of the MOSFET can be switched by transmitting the charge accumulated by the ferroelectric capacitor to the gate electrode. By utilizing the electric charge due to the remanent polarization of the ferroelectric substance, it is possible to construct a non-volatile memory in which the conduction and non-conduction states of the MOSFET are "1" and "0".
【００１７】この方式では記憶を読み出すのに、図１の
ソース15とドレイン16のあいだが導通か非導通かを読み
取ることにより行うので、読み取りにより強誘電体キャ
パシタ１の分極状態を破壊することはない。また、この
構造においてもMOSFETのゲート酸化膜の下部に発生する
電荷密度を必要とするため、MFS 構造と同様に要求され
る残留分極は比較的小さくてよい。こうして、前述した
１Tr・１Capa／１cellタイプに対する問題を解決するこ
とができる。In this method, the memory is read out by reading the conduction or non-conduction between the source 15 and the drain 16 in FIG. 1, so that the polarization state of the ferroelectric capacitor 1 is not destroyed by the reading. Absent. In addition, since this structure also requires a charge density generated below the gate oxide film of the MOSFET, the remanent polarization required as in the MFS structure may be relatively small. In this way, it is possible to solve the above-mentioned problem for the 1Tr / 1Capa / 1cell type.
【００１８】また本発明の構造では、半導体基板や半導
体基板上のバッファ層の上に強誘電体薄膜を直接成膜す
る必要がなく、下部電極の材質を選ぶことによって強誘
電体薄膜と下地との整合性をうることができる。たとえ
ば酸化物ペロブスカイト構造をもつPZT (PbZrTiO3 ）、
PLZT (PbLaZrTiO3 ）、 PbTiO3 などは、下地にPtを用
いると結晶性の良い膜がえられる。Further, in the structure of the present invention, it is not necessary to directly form the ferroelectric thin film on the semiconductor substrate or the buffer layer on the semiconductor substrate, and by selecting the material of the lower electrode, the ferroelectric thin film and the base can be formed. The consistency of can be obtained. For example, PZT (PbZrTiO 3 ) with oxide perovskite structure,
PLZT (PbLaZrTiO 3 ), PbTiO 3 etc. can be obtained as a film with good crystallinity if Pt is used as the base.
【００１９】また強誘電体キャパシタ１の一方の電極と
MOSFETのゲート電極との接続部にビットライン17を設け
ることにより、ワードライン14とビットライン17とのあ
いだの電圧を変化させることができ、これにより強誘電
体の分極反転を操作することができる。そのためMFIS構
造のように、絶縁膜を挿入した分印加電圧を大きくする
という必要がなくなり、低い電圧で記憶させることがで
きる。こうして、前述したMFS 構造に対する問題を解決
することができる。Further, one electrode of the ferroelectric capacitor 1
By providing the bit line 17 at the connection with the gate electrode of the MOSFET, the voltage between the word line 14 and the bit line 17 can be changed, and thereby the polarization reversal of the ferroelectric substance can be manipulated. .. Therefore, unlike the MFIS structure, it is not necessary to increase the applied voltage by inserting the insulating film, and it is possible to store at a low voltage. In this way, the above-mentioned problem with the MFS structure can be solved.
【００２０】実施例１ 図２〜７は本発明のデバイスの一実施例のプロセスフロ
ーをあらわす断面説明図である。なお、図７は図６を90
°回転させた方向での断面説明図である。図２〜７にお
いて、18は半導体基板、19はFET のドレイン、ソース領
域を形成するための不純物拡散領域、20は素子間分離の
ためのフィールド酸化膜、21は層間絶縁膜、22はゲート
電極、23はゲート酸化膜、24は導電体電極（導電膜）、
25は強誘電体、26は配線層、27はパシベーション膜であ
る。Embodiment 1 FIGS. 2 to 7 are sectional explanatory views showing a process flow of an embodiment of the device of the present invention. In addition, FIG.
It is a cross-sectional explanatory view in the direction rotated by °. 2 to 7, 18 is a semiconductor substrate, 19 is an impurity diffusion region for forming FET drain and source regions, 20 is a field oxide film for element isolation, 21 is an interlayer insulating film, and 22 is a gate electrode. , 23 is a gate oxide film, 24 is a conductor electrode (conductive film),
Reference numeral 25 is a ferroelectric substance, 26 is a wiring layer, and 27 is a passivation film.
【００２１】本実施例ではFET とキャパシタとが層間絶
縁膜21a により分離されている。図２に示される工程は
従来のMOSFET技術によるものである。In this embodiment, the FET and the capacitor are separated by the interlayer insulating film 21a. The process shown in FIG. 2 is by conventional MOSFET technology.
【００２２】すなわち、半導体基板表面に薄い酸化膜を
熱酸化法により形成し、部分酸化法により素子分離用の
フィールド酸化膜20を形成した。そののち、絶縁膜にポ
リシリコンを堆積してゲート電極22を形成すると共に、
ソース、ドレイン領域を形成する場所にイオン打込みを
し、熱処理をして不純物拡散層19を形成した。そのの
ち、CVD 法などにより層間絶縁膜21a を形成したもので
ある。That is, a thin oxide film was formed on the surface of a semiconductor substrate by a thermal oxidation method, and a field oxide film 20 for element isolation was formed by a partial oxidation method. After that, polysilicon is deposited on the insulating film to form the gate electrode 22, and
Ion implantation was performed on the locations where the source and drain regions are to be formed, and heat treatment was performed to form the impurity diffusion layer 19. After that, the interlayer insulating film 21a is formed by the CVD method or the like.
【００２３】つぎに、図３に示されるように層間絶縁膜
21a の上にキャパシタの下部電極となる導電膜24a を形
成、加工した。この導電膜の形成はたとえば、スパッタ
リング法で、100 〜600nm の膜厚のPt金属膜を形成し、
エッチングにより必要な部分のみを残し、他を腐蝕除去
する。この際、ゲート電極22と連結するように（図７参
照）導電膜を延ばして形成した。このPt金属膜を形成す
るのは、ついで導電膜24a の上に強誘電体25が形成され
るが、この強誘電体25に酸化物ペロブスカイト構造をも
つPZT 系（PZT 、PLZT、 PbTiO3 など）を用いるばあ
い、導電膜の材料としてはF.C.C.構造すなわち面心立方
格子構造をもつ金属、とくにPt（白金）を用いるのが好
ましいからである。その理由は、F.C.C.金属は下地にか
かわらず結晶配向性をもつ性質があり、その中でもPtは
PZT 系の強誘電体との格子定数のミスマッチが比較的小
さく、そのため強誘電体の結晶配向性が良くなるためで
ある。Next, as shown in FIG. 3, an interlayer insulating film is formed.
A conductive film 24a to be the lower electrode of the capacitor was formed and processed on 21a. The conductive film is formed, for example, by a sputtering method to form a Pt metal film with a thickness of 100 to 600 nm.
By etching, only the necessary parts are left and the others are removed by corrosion. At this time, the conductive film was extended so as to be connected to the gate electrode 22 (see FIG. 7). The Pt metal film is formed by forming the ferroelectric 25 on the conductive film 24a, and the PZT system (PZT, PLZT, PbTiO 3 etc.) having an oxide perovskite structure is formed on the ferroelectric 25. This is because it is preferable to use a metal having an FCC structure, that is, a face-centered cubic lattice structure, especially Pt (platinum) as the material of the conductive film when using. The reason is that FCC metal has the property of crystal orientation regardless of the substrate, and among them, Pt
This is because the lattice constant mismatch with the PZT-based ferroelectric is relatively small, which improves the crystal orientation of the ferroelectric.
【００２４】ついで図４に示すように強誘電体材料のた
とえば、PZT をスパッタリング法で0.1 〜0.3 μm 堆積
し、引きつづき上部電極を下部電極と同様に積層して不
要部分をエッチング除去して形成した。この強誘電体材
料の形成はスパッタリング法以外のCVD 法、ゾル−ゲル
法などでも形成できる。この強誘電体材料は酸化物ペロ
ブスカイト構造をもつPZT 、PLZTなどが強誘電性も強い
ので理想的である。しかし成膜の難しさからみると、Ge
TeやPbx Ge1-x Teのように簡単な結晶構造（NaCl型）で
結晶化温度の低い（250 ℃以下）、Ge元素を成分に有す
る強誘電体の方が、製造プロセス上優れている。Next, as shown in FIG. 4, a ferroelectric material such as PZT is deposited to a thickness of 0.1 to 0.3 μm by a sputtering method, and then an upper electrode is laminated in the same manner as the lower electrode and unnecessary portions are removed by etching. did. The ferroelectric material can be formed by a CVD method other than the sputtering method, a sol-gel method, or the like. This ferroelectric material is ideal because PZT and PLZT, which have an oxide perovskite structure, have strong ferroelectricity. However, from the difficulty of film formation, Ge
Ferroelectrics with a simple crystal structure (NaCl type), such as Te and Pb x Ge 1-x Te, that have a low crystallization temperature (250 ° C or less) and have a Ge element as a component are superior to the manufacturing process There is.
【００２５】なお、電極は２層以上の積層構造たとえ
ば、不純物がドープされたポリシリコンやアモルファス
シリコとPt層の組み合わせにすると接着性向上の効果が
ある。また、電極および強誘電体の加工に関してはウェ
ットエッチングでも良いが、微細化に適応しうる点より
イオンミリング、RIBE、RIE などのドライエッチングの
方が好ましい。It should be noted that the electrode has a laminated structure of two or more layers, for example, a combination of impurity-doped polysilicon or amorphous silicon and a Pt layer has an effect of improving adhesiveness. Although wet etching may be used for processing the electrodes and the ferroelectric, dry etching such as ion milling, RIBE, or RIE is preferable from the viewpoint of adaptability to miniaturization.
【００２６】つぎの図５〜６に示されるステップは従来
の半導体プロセス技術を用いたもので、強誘電体25およ
び上部電極の導電膜24b の上にCVD 法などでPSG を約0.
5μm 堆積し、層間絶縁膜21b を再度形成した。そのの
ち、電極コンタクトのため、層間絶縁膜21b を目抜き、
スパッタリング法によりAl膜を成膜し、エッチングでAl
の配線層26を形成した。その上にさらに、CVD 法などで
PSG を１〜２μm 堆積し、パッシベーション膜27を形成
して本発明の半導体記憶素子部分を形成した。The steps shown in FIGS. 5 to 6 are performed by using the conventional semiconductor process technology, and the PSG of about 0.5 is formed on the ferroelectric 25 and the conductive film 24b of the upper electrode by the CVD method or the like.
5 μm was deposited and the interlayer insulating film 21b was formed again. After that, for electrode contact, the interlayer insulating film 21b is punched out,
An Al film is formed by sputtering and Al is etched.
The wiring layer 26 was formed. On top of that, the CVD method etc.
PSG was deposited to a thickness of 1 to 2 μm and a passivation film 27 was formed to form a semiconductor memory element portion of the present invention.
【００２７】実施例２ 図８〜11は本発明のデバイスの他の実施例のプロセスフ
ローをあらわす断面説明図である。なお、図11は図10を
90°回転させた方向での断面説明図である。図８〜11に
おいて、18〜27は実施例１における同一参照符号と同等
のものをあらわしている。Embodiment 2 FIGS. 8 to 11 are sectional explanatory views showing a process flow of another embodiment of the device of the present invention. Note that FIG. 11 shows FIG.
It is a section explanatory view in the direction rotated 90 degrees. 8 to 11, 18 to 27 represent the same reference numerals as those in the first embodiment.
【００２８】本実施例ではFET のゲート電極と強誘電体
キャパシタの下部電極とが共用となっている。図８に示
されるステップでは、従来のMOSFET技術を用いて実施例
１と同様に半導体基板18上にフィールド酸化膜20、ゲー
ト酸化膜23を形成し、その上部にゲート電極兼強誘電体
キャパシタの下部電極となるPtの導電膜22を形成し、そ
の上部に強誘電体25、さらにその上部に上部電極となる
導電膜24を形成した。ここで強誘電体25として酸化物ペ
ロブスカイト構造をもつPZT 系を用いるばあいは、前述
した理由により導電膜の材料としてPtを選択するのが好
ましい。また導電膜22、24は２層以上の積層構造であっ
てもよい。たとえば、下地との整合性を考え下部電極の
Ptの下にドープされたポリシリコンやドープされたアモ
ルファスシリコンなどのシリコン系の導電体を形成する
と一層密着性がよい。In this embodiment, the gate electrode of the FET and the lower electrode of the ferroelectric capacitor are shared. In the step shown in FIG. 8, the field oxide film 20 and the gate oxide film 23 are formed on the semiconductor substrate 18 by using the conventional MOSFET technology as in the first embodiment, and the gate electrode / ferroelectric capacitor is formed on the field oxide film 20 and the gate oxide film 23. A Pt conductive film 22 to be a lower electrode was formed, a ferroelectric 25 was formed on the conductive film 22, and a conductive film 24 to be an upper electrode was further formed on the ferroelectric 25. When the PZT system having the oxide perovskite structure is used as the ferroelectric 25, it is preferable to select Pt as the material of the conductive film for the reason described above. Further, the conductive films 22 and 24 may have a laminated structure of two or more layers. For example, considering the compatibility with the base,
Adhesion is further improved by forming a silicon-based conductor such as doped polysilicon or doped amorphous silicon under Pt.
【００２９】ついで図９に示されるように電極および強
誘電体薄膜の不要部分を除去するため、エッチング加工
し、不純物拡散領域19を形成した。加工の方法としては
前述した理由によりドライエッチングを用いるのが好ま
しい。図10〜11は実施例１と同様に、従来のMOSFET技術
を用いてAlの配線層26およびパッシベーション膜27を形
成した工程をあらわしている。Then, as shown in FIG. 9, in order to remove unnecessary portions of the electrodes and the ferroelectric thin film, etching processing was performed to form impurity diffusion regions 19. As a processing method, it is preferable to use dry etching for the reasons described above. 10 to 11 show the process of forming the Al wiring layer 26 and the passivation film 27 by using the conventional MOSFET technique as in the first embodiment.
【００３０】[0030]
【発明の効果】以上説明したとおり、本発明のデバイス
によれば強誘電体キャパシタと電界効果型トランジスタ
のゲート電極とが接続されており、かつ前記キャパシタ
とゲート電極とのあいだに外部電極端子が接続されてい
るので、書き込み時は低い電圧で行え、読み出し時に
は、強誘電体の分極反転電荷によりMOSFETのゲートに反
転層を形成し、ドレイン、ソース間の導通、非導通状態
で検出でき、非破壊読み出しが可能である。また、結晶
性の良い強誘電体薄膜を有するデバイスをうることがで
きる。As described above, according to the device of the present invention, the ferroelectric capacitor is connected to the gate electrode of the field effect transistor, and the external electrode terminal is provided between the capacitor and the gate electrode. Since they are connected, a low voltage can be used for writing, and an inversion layer can be formed on the gate of the MOSFET by the polarization inversion charge of the ferroelectric substance for reading, and detection can be performed in the conduction or non-conduction state between the drain and source. Destructive reading is possible. Further, a device having a ferroelectric thin film having good crystallinity can be obtained.
【００３１】その結果、強誘電体のキャパシタに蓄えら
れた電荷量により情報を記憶する半導体記憶素子の特性
並びに信頼性を大幅に向上でき利用範囲が増える効果が
ある。As a result, the characteristics and reliability of the semiconductor memory element for storing information can be greatly improved by the amount of electric charge stored in the ferroelectric capacitor, and the range of use can be increased.
【図１】本発明のデバイスの一実施例の等価回路図であ
る。FIG. 1 is an equivalent circuit diagram of an embodiment of the device of the present invention.
【図２】本発明のデバイスの一実施例のプロセスフロー
をあらわす断面説明図である。FIG. 2 is a cross-sectional explanatory diagram showing a process flow of one embodiment of the device of the present invention.
【図３】本発明のデバイスの一実施例のプロセスフロー
をあらわす断面説明図である。FIG. 3 is a cross-sectional explanatory view showing a process flow of an example of the device of the present invention.
【図４】本発明のデバイスの一実施例のプロセスフロー
をあらわす断面説明図である。FIG. 4 is a cross-sectional explanatory diagram showing a process flow of one embodiment of the device of the present invention.
【図５】本発明のデバイスの一実施例のプロセスフロー
をあらわす断面説明図である。FIG. 5 is a cross-sectional explanatory view showing a process flow of an example of the device of the present invention.
【図６】本発明のデバイスの一実施例のプロセスフロー
をあらわす断面説明図である。FIG. 6 is a cross-sectional explanatory diagram showing the process flow of one embodiment of the device of the present invention.
【図７】図６を90°回転させた方向での断面説明図であ
る。FIG. 7 is a cross-sectional explanatory view in a direction obtained by rotating FIG. 6 by 90 °.
【図８】本発明のデバイスの他の実施例のプロセスフロ
ーをあらわす断面説明図である。FIG. 8 is a sectional explanatory view showing a process flow of another embodiment of the device of the present invention.
【図９】本発明のデバイスの他の実施例のプロセスフロ
ーをあらわす断面説明図である。FIG. 9 is a sectional explanatory view showing a process flow of another embodiment of the device of the present invention.
【図１０】本発明のデバイスの他の実施例のプロセスフ
ローをあらわす断面説明図である。FIG. 10 is a sectional explanatory view showing a process flow of another embodiment of the device of the present invention.
【図１１】図10を90°回転させた方向での断面説明図で
ある。FIG. 11 is a cross-sectional explanatory view in a direction obtained by rotating FIG. 10 by 90 °.
【図１２】従来の１Tr・１Capa／１cellタイプの強誘電
体メモリの等価回路図である。FIG. 12 is an equivalent circuit diagram of a conventional 1Tr / 1Capa / 1cell type ferroelectric memory.
【図１３】従来の１Tr・１Capa／１cellタイプの強誘電
体メモリの断面説明図である。FIG. 13 is a cross-sectional explanatory view of a conventional 1Tr / 1Capa / 1cell type ferroelectric memory.
【図１４】強誘電体のヒステリシスをあらわす図であ
る。FIG. 14 is a diagram showing hysteresis of a ferroelectric substance.
【図１５】従来のMFS 構造の強誘電体メモリの断面説明
図である。FIG. 15 is a cross-sectional explanatory diagram of a conventional MFS structure ferroelectric memory.
１ 強誘電体キャパシタ 14 ワードライン 15 ソース 16 ドレイン 17 ビットライン 18 半導体基板 19 不純物拡散領域 22 ゲート電極 24 導電体電極（導電膜） 25 強誘電体 1 Ferroelectric capacitor 14 Word line 15 Source 16 Drain 17 Bit line 18 Semiconductor substrate 19 Impurity diffusion region 22 Gate electrode 24 Conductor electrode (conductive film) 25 Ferroelectric substance
Claims (2)
いて形成された２つの第２導電型の半導体領域のあいだ
の前記基板表面に誘電体薄膜が設けられており、該誘電
体薄膜上部に導電膜が形成されゲート電極とした電界効
果型トランジスタと、強誘電体を２つの導電体電極では
さんだ強誘電体キャパシタとを有する半導体記憶素子で
あって、 前記電界効果型トランジスタのゲート電極が前記強誘電
体層をはさむ２つの導電体電極の一方と電気的に接続さ
れており、かつ前記ゲート電極および該ゲート電極と接
続された前記導電体電極に接続された電極端子が導出さ
れてなることを特徴とする半導体記憶素子。1. A dielectric thin film is provided on the surface of the substrate between two semiconductor regions of the second conductivity type which are formed on the surface of the semiconductor substrate of the first conductivity type and are spaced apart from each other. What is claimed is: 1. A semiconductor memory device comprising: a field-effect transistor having a conductive film formed thereon as a gate electrode; and a ferroelectric capacitor having a ferroelectric material sandwiched between two conductive electrodes. Is electrically connected to one of two conductor electrodes sandwiching the ferroelectric layer, and an electrode terminal connected to the gate electrode and the conductor electrode connected to the gate electrode is led out. A semiconductor memory device characterized by the following.
電体キャパシタとが少なくとも１層以上の絶縁層により
電気的に分離して形成されてなる請求項１記載の半導体
記憶素子。2. The semiconductor memory device according to claim 1, wherein the field effect transistor and the ferroelectric capacitor are formed by being electrically separated by at least one insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24771491A JP3160324B2 (en) | 1991-09-26 | 1991-09-26 | Semiconductor storage element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24771491A JP3160324B2 (en) | 1991-09-26 | 1991-09-26 | Semiconductor storage element |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35932199A Division JP3559486B2 (en) | 1999-12-17 | 1999-12-17 | Semiconductor storage element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0590532A true JPH0590532A (en) | 1993-04-09 |
| JP3160324B2 JP3160324B2 (en) | 2001-04-25 |
Family
ID=17167579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24771491A Expired - Fee Related JP3160324B2 (en) | 1991-09-26 | 1991-09-26 | Semiconductor storage element |
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| Country | Link |
|---|---|
| JP (1) | JP3160324B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5515311A (en) * | 1993-07-26 | 1996-05-07 | Olympus Optical Co., Ltd. | Method of driving ferroelectric memory |
| US5541870A (en) * | 1994-10-28 | 1996-07-30 | Symetrix Corporation | Ferroelectric memory and non-volatile memory cell for same |
| US5708284A (en) * | 1995-03-20 | 1998-01-13 | Sharp Kabushiki Kaisha | Non-volatile random access memory |
| EP1134803A1 (en) * | 2000-03-13 | 2001-09-19 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| KR100447790B1 (en) * | 2001-12-04 | 2004-09-08 | 한국과학기술연구원 | Error protection circuit in write signal of non destructive readout ferroelectric random access memory device and its application to the method |
| US7206217B2 (en) | 2002-04-10 | 2007-04-17 | Matsushita Electric Industrial Co., Ltd. | Non-volatile flip flop |
-
1991
- 1991-09-26 JP JP24771491A patent/JP3160324B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5515311A (en) * | 1993-07-26 | 1996-05-07 | Olympus Optical Co., Ltd. | Method of driving ferroelectric memory |
| US5541870A (en) * | 1994-10-28 | 1996-07-30 | Symetrix Corporation | Ferroelectric memory and non-volatile memory cell for same |
| US5708284A (en) * | 1995-03-20 | 1998-01-13 | Sharp Kabushiki Kaisha | Non-volatile random access memory |
| EP1134803A1 (en) * | 2000-03-13 | 2001-09-19 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| US6787830B2 (en) | 2000-03-13 | 2004-09-07 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| KR100447790B1 (en) * | 2001-12-04 | 2004-09-08 | 한국과학기술연구원 | Error protection circuit in write signal of non destructive readout ferroelectric random access memory device and its application to the method |
| US7206217B2 (en) | 2002-04-10 | 2007-04-17 | Matsushita Electric Industrial Co., Ltd. | Non-volatile flip flop |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3160324B2 (en) | 2001-04-25 |
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