JP3039425B2 - Capacitive element and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a capacitive element using a dielectric such as a ferroelectric or a high dielectric suitable for miniaturization and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, non-volatile memories using a ferroelectric as an insulating film for a storage capacitor and memories using a high dielectric constant film as an insulating film for a capacitor in order to compensate for the reduction in the absolute value of the storage capacity accompanying the miniaturization of DRAM. The development of is very active. In these cases, applying a ferroelectric or high dielectric to a silicon LSI process is a major issue. Since the basic structures of a nonvolatile memory using a ferroelectric and a DRAM using a high dielectric are similar, the prior art of the former will be introduced below.

A so-called ferroelectric memory combining a semiconductor and a ferroelectric, for example, a capacitor using lead zirconium titanate (Pb (Zr _x Ti _1-x ) O ₃ , hereinafter abbreviated as PZT) is a ferroelectric memory. "1" and "0" are stored using the remanent polarization of. Since this information is retained even when the power is turned off, it is known to operate as a nonvolatile memory.
FIG. 5 shows a circuit diagram of the unit cell as this basic configuration. In this case, the unit cell has a configuration in which one cell transistor (usually an n-channel MOSFET) Tr and a ferroelectric capacitor Cf are combined. Bit line (BL
), The word line (abbreviated as WL), and the plate line (abbreviated as PL) are controlled to turn on / off the Tr, and the polarity of the voltage applied to Cf is changed to change the residual polarization of Cf. Decide the positive or negative.

As described above, a unit cell of a ferroelectric memory is composed of a cell transistor Tr and a ferroelectric capacitor Cf.
In particular, the structure of the ferroelectric capacitor Cf is a major factor that determines the degree of integration. For example, 19
94 International Electron Device Meeting (International Electron)
Technical Digest in Device Meeting (Technical Digest) 8
It is introduced on page 43. FIG. 6 shows a sectional view of the structure of the capacitor in this case. In the figure, 1 is a silicon p-type layer, 2 is the same n ⁺ layer, 3 is a base interlayer insulating film (SiO ₂ ), 4 is a polysilicon plug, 5 is a barrier layer a (TiN), and 6 is a barrier layer b (TiN). ) And 7 are ferroelectric lower electrodes (Pt), 8 is a ferroelectric (PZT), 9 is a ferroelectric upper electrode, and 10 is a capacitor interlayer insulating film (SiO ₂ ). In this example, a ferroelectric capacitor composed of a lower electrode, a ferroelectric, and an upper electrode is formed on a polysilicon plug 4, and the source and the source of a cell transistor formed on an underlying silicon substrate are formed.
The n ⁺ layer 2 serving as a drain and the lower electrode 7 of the ferroelectric capacitor are electrically connected by a polysilicon plug 4. In this structure, since the cell transistor and the ferroelectric capacitor are formed by lamination, it is very advantageous for memory integration. This structure is the same for a DRAM using a high dielectric substance. In this case, instead of the ferroelectric substance (PZT),
As a high dielectric substance, for example, SrTiO ₃ , (Ba _1-x Sr
_x ) TiO ₃ is used, the other components are exactly the same.

[0005]

Problems with the structure of the capacitor shown in FIG. 6 will be described below.

In manufacturing this structure, first, a barrier layer b (Ti) 6 and a barrier layer a (T
iN) After forming the lower electrode 7 and PZT 8, a PZT 8 is formed. PZT is generally formed in an oxygen atmosphere at a temperature of about 600 ° C. The role of the barrier layers a and b is to prevent oxygen from diffusing in the lower electrode (Pt) and oxidizing the polysilicon plug 4 thereunder. That is,
When the polysilicon plug is oxidized, conduction between the lower electrode and the polysilicon plug cannot be established because the silicon oxide is an insulator. Therefore, this is prevented by interposing the barrier layers a and b. Barrier layer a (Ti
The laminated structure of N) / b (Ti) is effective at preventing the diffusion of oxygen into the polysilicon plug at a temperature of 600 ° C. or lower, and the laminated structure itself is not oxidized. Therefore, the TiN / Ti laminated structure is effective as a barrier film if a ferroelectric film or a high dielectric film is formed on polysilicon at a temperature of 600 ° C. or less, and the conduction between the lower electrode 7 and the n ⁺ layer 2 is improved. Can be taken.

In the case of PZT, it is possible to form a film at a temperature of 600 ° C. or less, but a ferroelectric material other than PZT, for example, SrBi
_{When 2} Ta ₂ O ₉ is used, the film is usually formed in an oxygen atmosphere at 800 ° C. In this case, the barrier layer a
The (TiN) 5 and the barrier layer b (Ti) 6 are completely oxidized, and these oxides are insulators, and at the same time, the oxidation proceeds to the polysilicon plug, so that the conduction between the lower electrode and the n ⁺ layer is completely obtained. I can't do things.

In general, even when a film is formed at a temperature of 600 ° C. or less, such as PZT having a low film formation temperature, oxidation of the TiN layer occurs although it is small. For example, when the capacitance size is reduced to about 2 μm and the scale of integration is increased, in particular, such oxidation often occurs partially instead of uniformly on the wafer surface, and the contact failure due to this is a bit yield failure. Comes out as. Therefore, the oxidation of the barrier layer and the polysilicon plug is performed by using a ferroelectric or a high dielectric
This becomes a serious problem in the manufacturing process of SI, especially semiconductor memory.

In order to solve this problem, it is necessary to change the barrier layer used here to another material having higher heat resistance, but at least a material which is not oxidized even at a temperature higher than 600 ° C. and does not allow oxygen to permeate. Has not been found to date.

An object of the present invention is to provide a structure capable of forming a capacitor made of a ferroelectric substance or a high dielectric substance on a contact plug made of a polysilicon plug or the like without causing a conduction failure with the contact plug, and a method of manufacturing the same. The idea is to provide a way.

[0011]

In order to solve the problem, a capacitor according to the present invention has a capacitor comprising an upper electrode, a dielectric layer, and a lower electrode on a contact plug via a capacitor lower interlayer film. In the capacitive element in which the contact plug and one electrode are electrically connected, the capacitive lower interlayer film is made of an insulating material.
Specifically, at least a part of the side surface of the lower electrode is electrically connected to the contact plug, so that the barrier layer conventionally provided under the lower electrode becomes unnecessary. Here, the contact portion may be formed via a polysilicon plug from the semiconductor base substrate, or may be formed on the plug via a contact pad. Therefore, a barrier film for preventing oxygen diffusion on the polysilicon plug is not required, and the n ⁺ layer can be in contact with the lower electrode. here,
Contact when making contact with the side of lower electrode etc.
The plug or contact pad is at least
Or larger than the lower electrode in either width
This facilitates connection. As a dielectric layer used in these structures, Pb (Zr
_{1-x Ti x) O 3} , SrBi 2 Ta 2 O 9, SrTiO
_3. Conventionally used ferroelectric materials such as (Ba _1-x Sr _x ) TiO ₃ .

[0012] Further, as a method of manufacturing these, a capacitor lower interlayer film, a lower electrode, and a dielectric layer are laminated on a contact portion formed in a contact plug or a contact pad, and then processed into a desired shape. A first step of partially exposing the portion, a metal material is formed on the entire surface after the first step, and the metal material remains at least on the side wall of the lower electrode by anisotropically etching the metal material. And a second step. In particular, it is preferable that the metal material is formed by CVD using an organic Al material because the formation of the metal portion on the side wall portion and the low-temperature film formation that does not adversely affect the characteristics of the ferroelectric material are possible. I can say. Specifically, a capacitive lower interlayer film is formed on a semiconductor base substrate. Next, after a lower electrode and a ferroelectric are formed, the ferroelectric, the lower electrode, and the lower interlayer film are collectively processed to expose the contact portion in the semiconductor base substrate. Thereafter, a metal wiring is formed by MOCVD, and then the whole surface is etched back by anisotropic etching. At this time, the metal wiring remains on at least a part of the side wall of the processed ferroelectric, lower electrode, and capacitor lower interlayer film, and conduction between the lower electrode and the contact portion can be established.

[0013]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view showing the structure of a ferroelectric capacitor according to the present invention.
Shown in In the figure, 1 is a silicon p-type layer, 2 is n ⁺
Layer, 3 is a base interlayer insulating film, 4 is a polysilicon plug, 8
Is a ferroelectric, 9 is a ferroelectric upper electrode, 10 is a capacitor interlayer insulating film, 11 is a contact pad, 12 is a capacitor lower interlayer insulating film, 13 is a metal wiring, 14 is a ferroelectric lower electrode a, 1
5 is a lower electrode b.

FIGS. 2A to 2F are sectional views showing the steps of the method for manufacturing a ferroelectric capacitor according to the present invention. On the structure in which the polysilicon plug 4 and the contact pad 11 are formed on the n ⁺ layer 2, a lower interlayer insulating film 12, a lower electrode b15, a lower electrode a14, and a ferroelectric material 8 are sequentially formed on the structure (FIG. 2).
(A)). Next, the ferroelectric 8, the lower electrode a14, the lower electrode b15, and the capacitive lower interlayer film 12 are collectively processed so that the contact pads 11 are exposed (FIG. 2B).
Metal wiring (such as Al) was formed on the entire surface (FIG. 2C)
Thereafter, the metal wiring is entirely etched back by a method such as reactive ion etching or the like so that the metal wiring remains only on the side wall of the capacitor as shown in the figure (FIG. 2D). Next, the upper electrode 9
Is formed (FIG. 2E), and an upper interlayer film 10 is formed thereon (FIG. 2F).

[0016]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1) In FIG. 1, 1 is a silicon p-type layer, 2 is an n ⁺ layer, 3 is a base interlayer insulating film (Si
O ₂ ), 4 is a polysilicon plug, 8 is a ferroelectric (PZ)
T), 9 is a ferroelectric upper electrode, 10 is a capacitor interlayer insulating film (SiO ₂ ), 11 is a contact pad (WSi ₂ ),
12 capacity lower insulating film (SiO _2), 13 is a metal wiring (Al), 14 is a ferroelectric lower electrode a (Pt), 15 but is lower electrode b (Ti), n ⁺ layer 2 and the lower Electrode 1
Electrical connection with 4 and 15 is metal wiring (Al) on the side wall of the capacitor
13, a contact pad (WSi ₂ ) 11, and a polysilicon plug 4. The method of manufacturing these wirings will be described later. However, since there is no problem such as oxidation in the manufacturing process, contact failure is less likely to occur. Further, since the ferroelectric capacitor is formed on the cell transistor via the polysilicon plug, it is advantageous for high integration of a semiconductor memory using the ferroelectric capacitor.

Next, a method of manufacturing a ferroelectric capacitor according to the present invention will be described. 2 (a) to 2 (f) are cross-sectional views showing a manufacturing process of one embodiment of the ferroelectric capacitor of the present invention. On the structure in which the polysilicon plug 4 and the contact pad 11 are formed on the n ⁺ layer 2, the lower interlayer insulating film 12, the lower electrode 15,
4. A ferroelectric material 8 is sequentially formed (FIG. 2A). At this time, the capacitive lower interlayer film (SiO 2) before forming the lower electrode 15 is formed.
₂ ) 12 is flattened by a method such as chemical mechanical polishing, the contact pad is 200 nm, and the thickness of the capacitive lower interlayer film 12 on the contact pad is about 500 nm. The lower electrode a14 is Pt (200 nm), the lower electrode b15 is Ti (50 nm), and the thickness of PZT is 200 nm. Pt
The reason for putting Ti underneath is to improve the adhesion between Pt and the lower interlayer film. The flattening is performed because the film quality of the ferroelectric material 8 deteriorates on a substrate having irregularities.

Next, the ferroelectric 8, the lower electrodes 14, 15,
The capacitor lower interlayer film 12 is processed at a time so that the contact pads 11 are exposed (FIG. 2B). This can be performed by a method such as reactive ion etching using a photoresist as a mask and using a gas such as CF ₄ or ion milling using Ar. In particular, in the case of reactive ion etching, a contact pad (WSi ₂ )
It is easy to detect the end point of the etching by emission analysis when 12 is exposed.

Next, a metal wiring (Al) is formed on the entire surface (FIG. 2C). Al at this time is, for example, MOCVD using dimethyl aluminum hydride (DMAH).
At a temperature of about 200 ° C. Since a film forming method using a gas phase chemical reaction such as MOCVD has good step coverage, Al is sufficiently formed also on the side wall of the capacitance step.

Next, the metal wiring (Al) is entirely etched back by a method such as reactive ion etching using Cl ₂ (FIG. 2D). At this time, since reactive ion etching is anisotropic etching, it is possible to leave Al only on the side wall of the capacitor as shown in the figure. The lower electrodes 14 and 15 and the contact pads 11 are electrically connected by the metal wiring on the side wall.

Next, an upper electrode (Pt: about 200 nm) 9
Is formed (FIG. 2E). This is performed by ion milling using a photoresist as a mask after forming Pt on the entire surface (not shown). First metal wiring (Al)
When PZT is formed on the entire surface, PZT and Al react with each other to adversely affect the ferroelectric characteristics of PZT. In this case, the reaction layer is also mostly removed by ion milling.

Finally, an upper interlayer film (Si)
O ₂ ) 10 is formed (FIG. 2F). This includes, for example, C using O ₃ (ozone) and TEOS (tetraethoxysilane) without adversely affecting the ferroelectric properties.
SiO ₂ by VD is used.

According to the above manufacturing method, a ferroelectric capacitor having the structure of the present invention can be manufactured. However, when a ferroelectric capacitor is formed, the lower electrode and the n ⁺ layer (or polysilicon plug) are still connected. Electrical connection has not been made, and connection is made with the metal wiring on the side wall after processing the ferroelectric capacitor, so that contact failure due to oxidation of the electrode material does not occur as in the related art.

For example, in this structure, the Ti layer of the capacitor lower electrode b is oxidized at the time of PZT film formation, as in the conventional example, but the electrical connection with the polysilicon plug 4 is made by Al on the side wall. This is never a problem. After the side wall wiring of the metal material is formed, there is formation of the upper electrode of the ferroelectric capacitor and formation of the interlayer film on the capacitor. However, since these are all performed at a temperature of 400 ° C. or less, the adverse effect on the contact due to this is performed. Does not occur.

In this example, Al is used for the metal wiring. However, if there is a film forming method using other materials, for example, W, Cu, polysilicon, etc., which does not deteriorate the ferroelectric characteristics, it is also possible to use this. Of course you can. Although a polysilicon plug is used, another material such as W can be used in the same manner. LSI formed on the underlying silicon layer
In the case where the distance between the ferroelectric capacitor and the underlying silicon layer can be reduced because the number of circuit wirings is small, the plug or contact pad is not particularly required, and it is possible to obtain a contact directly with the substrate by Al wiring.

In this embodiment, an oxide film under the capacitance is interposed between the lower electrode of the ferroelectric and the contact pad. However, as long as the lower portion of the lower electrode is flattened, the oxide film between the electrodes is particularly reduced. No need.

Further, it is needless to say that the wiring on the side wall need not necessarily extend over the entire circumference of the capacitor, and it is sufficient that a part of the wiring remains conductive.

(Embodiment 2) FIG. 3 is a sectional view showing the structure of another embodiment of the present invention. In this case, the taper angle of the capacitance portion is increased only on the left side. In the process, the metal wiring tends to remain only on the right side. Therefore, the structure is such that the metal wiring is formed only on the right side in the drawing. According to this structure, since the metal wiring is partially left on only a part of the side wall, a short circuit between the upper electrode and the metal wiring hardly occurs and the yield is improved.

(Embodiment 3) FIG. 4 is a structural sectional view of another embodiment. In this case, the ferroelectric 8, the lower electrode a14,
The lower electrode b15 extends to the left and is larger than the upper electrode 9;
The structure has remained. According to this structure, since the metal wiring is partially left on only a part of the side wall, a short circuit between the upper electrode and the metal wiring hardly occurs and the yield is improved.

[0031]

As described in the above embodiments, according to the capacitor of the present invention and the method of manufacturing the same, a ferroelectric and a high dielectric capacitor suitable for high integration can be obtained by forming the dielectric film at 600 ° C. Even if the film is formed at such a high temperature, it can be obtained without causing a contact failure.

[Brief description of the drawings]

FIG. 1 is a sectional view of one embodiment of a capacitor structure according to the present invention.

FIGS. 2A to 2F are process cross-sectional views (a to f) of one embodiment of a method for manufacturing a capacitor according to the present invention;

FIG. 3 is a cross-sectional view of another embodiment of the capacitor structure of the present invention.

FIG. 4 is a sectional view of another embodiment of the capacitor structure of the present invention.

FIG. 5 is a circuit diagram of an example of a unit cell of a semiconductor memory using a ferroelectric.

FIG. 6 is a sectional view of an example of the structure of a conventional ferroelectric capacitor.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon p-type layer 2 silicon n ⁺ layer 3 base interlayer insulating film (SiO ₂ ) 4 polysilicon plug 5 barrier layer a (TiN) 6 barrier layer b (Ti) 7 ferroelectric lower electrode (Pt) 8 ferroelectric (Pb (Zr _0.53 Ti _0.47 ) O ₃ ) 9 Upper ferroelectric electrode (Pt) 10 Upper interlayer insulating film (SiO ₂ ) 11 Contact pad (WSi ₂ ) 12 Lower interlayer insulating film (SiO ₂ ) 13 Metal wiring (Al) 14 Ferroelectric lower electrode a (Pt) 15 Ferroelectric lower electrode b (Ti)

Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 27/04 H01L 27/10 651 27/108

Claims (7)

(57) [Claims] A capacitor comprising an upper electrode, a dielectric layer, and a lower electrode on a contact plug via a capacitor lower interlayer film;
In the capacitive element in which the contact plug and one electrode are electrically connected, the capacitive lower interlayer film is made of an insulating material, and the contact plug is at least long.
Samoshiku the capacitor element, wherein a larger lower electrode This <br/> in any width. 2. A contact pad and a contact pad on a contact plug.
Upper electrode, dielectric layer, lower electrode
Having a capacity consisting of poles and
In the capacitive element electrically connected to the electrode,
The capacitor lower interlayer film is made of an insulating material;
Pads smell at least either in length or width
A capacitance element larger than the lower electrode. 3. The contact plug or the contact plug at least partially on a side surface of the lower electrode.
2. The electrical connection of claim 1, wherein
Alternatively , the capacitive element according to claim 2 . Wherein said dielectric layer is _{Pb (Zr 1-x Ti x} ) O
₃ , SrBi ₂ Ta ₂ O ₉ , SrTiO ₃ , (Ba _1-x
4. The capacitor according to claim 1 , wherein the capacitor is made of any material selected from Sr _x ) TiO ₃ . 5. The capacitive element according to claim 1, wherein an integrated circuit is formed on the underlying semiconductor substrate which is made conductive by said contact plug. 6. A capacitor lower interlayer film, a lower electrode, and a dielectric layer are laminated on a contact portion formed in a contact plug or a contact pad and then processed into a desired shape to partially expose the contact portion. A first step of forming a metal material over the entire surface after the first step, and a second step of leaving the metal material on at least the side wall of the lower electrode by anisotropically etching the metal material. A method for manufacturing a capacitive element, comprising: 7. A CV using an organic Al material as the metal material.
7. The method according to claim 6 , wherein the capacitor is formed of D.