JPH0982914A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a means which prevents the deterioration of film quality of a dielectric layer being in contact with a barrier layer, and prevents a plug part in the lower part from being oxidized through the barrier layer and from turning to a high resistance part. SOLUTION: A source region 23 and a drain region 24 are formed in an element forming region defined by an LOCOS oxide film 22 on a silicon substrate 21. Between the source region 23 and the drain region 24, a gate insulating film 25 is formed, on which word lines 26, 27 are formed. A protective film 28 is formed on the word lines 26, 27. The protective film 28 on the source region 23 is eliminated, and a barrier layer 29 is formed. The protective film 28 on the drain region 24 is eliminated, and a bit line 30 is formed. A first interlayer insulating film 31 is formed on the barrier layer and the bit line. A contact hole 32 is formed in the interlayer insulating film 31 on the barrier layer 29. A plug 33 and a lower electrode 34 are formed in the contact hole 32. On the lower electrode 34, a ferroelectric layer 35 is formed, on which a drive line 36 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a capacitor using a high dielectric material or a ferroelectric material and a manufacturing method thereof. In recent years, the integration of semiconductor memories such as DRAMs has been increasing more and more, and the area of capacitors used in the semiconductor memories is approaching its limit.

[0002]

2. Description of the Related Art In a conventional semiconductor device using a silicon oxide film or a nitride film as a capacitor dielectric, the thickness of the silicon oxide film or the nitride film is reduced in order to increase its capacitance. However, even if the silicon oxide film or nitride film is made to be extremely thin while maintaining good film quality, it becomes difficult to secure the capacitance required for semiconductor memory such as DRAM. ing.

Therefore, in order to overcome this, it is necessary to introduce a substance having a high dielectric constant as the dielectric of the capacitor. Strontium titanate (SrTiO ₃ , STO), strontium barium titanate ((Ba, Sr) TiO ₃ ,
High dielectrics or ferroelectrics having a large dielectric constant such as BST) are expected, and research aiming to apply these materials to semiconductor devices is actively under way.

FIG. 4 shows a conventional DRAM using a high dielectric material.
FIG. In this figure, 41 is a silicon substrate, 42 is a LOCOS oxide film, 43 is a source region, and 4 is a source region.
4 is a drain region, 45 is a gate insulating film, 46 and 47 are word lines, 48 and 50 are protective films, 49 is a bit line, 51
Is a first interlayer insulating film, 52 is a contact hole, 53 is a plug, 54 is a barrier layer, 55 is a lower electrode, 56 is a dielectric layer, 57 is an upper electrode, 58 is a second interlayer insulating film, and 59.
Is the upper wiring.

The manufacturing process of a conventional DRAM using a high dielectric will be described with reference to this drawing. First Step A LOCOS oxide film 42 is formed on the upper surface of a silicon substrate 41 to define an element formation region, an n-type impurity is injected into the element formation region to form a source region 43 and a drain region 44, and a gate is formed thereon. An insulating film 45 is formed, word lines 46 and 47 which are also gate electrodes are formed thereon, a protective film 48 is formed thereon to form a switching transistor, and a bit line 49 is formed on the drain region 44. Then, the protective film 50 is formed thereon.

Second Step A first interlayer insulating film 51 is formed thereon, the surface is flattened by a method such as reflow or chemical mechanical polishing (CMP), and the source region 43 is formed on the first interlayer insulating film 51. To form a contact hole 52. The contact hole 52 is filled with a plug material such as polysilicon or tungsten to form a plug 53, and then the surface is flattened by etch back CMP or the like.

Third Step A lower electrode 55 is formed by forming a barrier layer 54 on the barrier layer 54, forming a conductor layer on the barrier layer 54, and patterning the conductor layer.

Fourth Step A dielectric layer 56 is formed thereon and patterned into a desired shape. The dielectric layer 56 may be a high dielectric material or a ferroelectric material. Forming a conductor layer on it,
The upper electrode 57 is formed by patterning into a desired shape and size.

Fifth Step A second interlayer insulating film 58 is formed thereon, and a conductor layer is formed thereon and patterned to form an upper wiring 59.

[0010]

In the conventional semiconductor device having the structure described with reference to FIG. 4, the end of the barrier layer 54 is easily oxidized in the step of forming the dielectric layer 56 and is converted into an insulating oxide film. Or the film quality of the dielectric layer 56 in contact with the barrier layer 54 is deteriorated. further,
The lower plug portion is also easily oxidized through the barrier layer 54, and the plug has a high resistance or becomes an insulator in the worst state. An object of the present invention is to provide a means for preventing deterioration of the film quality of the dielectric layer in contact with the barrier layer and oxidation of the lower plug portion through the barrier layer to increase the resistance.

[0011]

As the degree of integration of DRAM increases, the projected area of the plane of the lower electrode decreases, so that the buffer layer is oxidized by an oxidizing atmosphere in the step of forming the dielectric layer and has a high resistance. Alternatively, there is a risk that it will become an insulating layer. As in the semiconductor device and the method for manufacturing a semiconductor device according to the present invention, the barrier layer does not come into direct contact with the oxidizing atmosphere in the step of forming the dielectric layer by adopting the configuration or the steps described in the claims, and thus the barrier layer Is less likely to be oxidized and a low resistance plug can be formed.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device and a method of manufacturing the semiconductor device of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 and 2 show a first embodiment.
FIG. 6 is an explanatory view of the manufacturing process of the semiconductor device according to
(A)-(G) has shown each process. In this figure, 1 is a silicon substrate, 2 is a LOCOS oxide film, 3 is a source region, 4 is a drain region, 5 is a gate insulating film, 6,
7 is a word line, 8 is a protective film, 9 is a barrier layer, 10 is a bit line, 11 is a first interlayer insulating film, 12 is a contact hole, 13 is a conductive material, 14 is a plug, 15 is a lower electrode,
Reference numeral 16 is a dielectric layer, 17 is an upper electrode, 18 is a second interlayer insulating film, and 19 is an upper wiring.

First step (see FIG. 1A) A LOCOS oxide film 2 is formed on the upper surface of a silicon substrate 1 to define an element formation region, and an n-type impurity is selectively implanted into this element formation region. A source region 3 and a drain region 4 are formed, a gate insulating film 5 is formed thereon by thermal oxidation, word lines 6 and 7 which are also gate electrodes are formed thereon, and a protective film made of SiO ₂ is formed thereon. 8 is formed to form a switching transistor.

Source region 3 of switching transistor
After removing the protective film 8 on the substrate, a barrier layer 9 made of Ti is formed to prevent the silicon substrate 1 and a lower electrode 15 to be formed later from diffusing and reacting with each other.
After removing the protective film 8 on the substrate, the bit line 10 is formed.

As the barrier layer 9, in addition to the above Ti, Ti
N, Pt, Ru, Ir and alloys containing them, R
A conductive oxide such as u or Ir can be used. Then, a first interlayer insulating film 11 made of SiO ₂ and having a thickness equal to or larger than the target thickness of the first interlayer insulating film and the height of the lower electrode 15 of the capacitor is formed thereon by CVD.
And the like.

Second step (see FIG. 1B) The first interlayer insulating film 11 is selectively removed to remove the barrier layer 9
A contact hole 12 is formed.

Third step (see FIG. 1C) A conductive material 1 such as Pt is formed on the upper surface including the contact hole 12.
3 is formed by a film forming method such as CVD, and the contact hole 12 is filled with a conductive material 13. As the conductive material 13, Ru, Ir, an alloy containing these metals, a conductive oxide film of Ru, Ir, or the like can be used in addition to Pt.

Fourth Step (see FIG. 1D) The conductive material 13 and the first interlayer insulating film 11 are polished by chemical mechanical polishing or the like to form the plug 14 and the lower electrode 1.
5 is formed and the surface of the first interlayer insulating film 11 is flattened. Therefore, the remaining first interlayer insulating film 11
Is obtained by adding the depth of the plug 14 and the height of the lower electrode 15.

Fifth Step (see FIG. 2E) The first interlayer insulating film 11 is etched to the depth of the plug 14. At this point, the plug 14 and the lower electrode 15 are integrally formed.

Step 6 (see FIG. 2F) A dielectric layer 16 having a large dielectric constant such as strontium titanate (SrTiO ₃ , STO) is formed thereon by a conventionally known film forming method. Then, a conductive material is formed thereon and patterned to form the upper electrode 17.

Seventh step (see FIG. 2G) A second interlayer insulating film 18 made of SiO ₂ is formed thereon, a conductor layer made of an aluminum alloy or the like is formed thereon, and this is patterned. Then, the upper wiring 19 is formed.

It has been found that the DRAM manufactured by the above steps has the following effects. In the conventional structure, the shape of the lower electrode is (cross section x height) =
When (0.3 μm × 0.3 μm) × 0.4 μm, the barrier layer is exposed to an oxidizing atmosphere during the dielectric film formation and is oxidized to be a high resistance or an insulator. Alternatively, the plug portion of tungsten is also oxidized, and the resistance of the plug is as high as several tens of kΩ to an insulator, but in the structure and manufacturing method of the present invention, the barrier layer is oxidized during the formation of the dielectric film. Since the plug is not exposed to a conductive atmosphere and the plug is integrated with the lower electrode, it can be reduced to about several tens Ω.

Further, when the high dielectric layer is an STO film having a film thickness of 75 nm and the upper electrode is TiN or Pt, the high dielectric layer is applied to the barrier layer portion in the conventional structure, so that the leakage current of the capacitor> 1 × 10 ⁶ / Acm ² ) but due to the structure of the present invention, the leakage current is 1 ×.
It can be reduced to 10 ⁷ / Acm ² .

(Second Embodiment) FIG. 3 is a diagram for explaining the structure of a semiconductor device according to the second embodiment. In this figure, 21 is a silicon substrate, 22 is a LOCOS oxide film, 2
3 is a source region, 24 is a drain region, 25 is a gate insulating film, 26 and 27 are word lines, 28 is a protective film, 29 is a barrier layer, 30 is a bit line, 31 is a first interlayer insulating film, 3
2 is a contact hole, 33 is a plug, 34 is a lower electrode, 35 is a ferroelectric layer, 36 is a drive line, and 37 is a second electrode.
Is an interlayer insulating film, and 38 is an upper wiring.

This embodiment relates to a nonvolatile RAM using a ferroelectric substance as a dielectric substance. The configuration of the semiconductor device of this embodiment will be described together with its manufacturing method.

First Step A LOCOS oxide film 22 is formed on the upper surface of a silicon substrate 21 to define an element formation region, and an n-type impurity is selectively implanted into this element formation region to form a source region 23 and a drain region 24. Then, a gate insulating film 25 is formed thereon, word lines 26 and 27 which are also gate electrodes are formed thereon, and a protective film 28 made of SiO ₂ is formed thereon to form a switching transistor.

Second Step After the protective film 28 on the source region 23 is partially removed, a barrier layer made of Ti for preventing the silicon substrate 21 and a lower electrode 34 to be formed later from diffusing and reacting with each other. After forming 29 and partially removing the protective film 28 on the drain region 24, the bit line 30 is formed. Then, a first interlayer insulating film 31 made of SiO _{2 having} a thickness equal to or larger than the target thickness of the first interlayer insulating film and the height of the lower electrode 34 of the capacitor is formed thereon. .

Third Step The first interlayer insulating film 31 is selectively removed to remove the barrier layer 2
9 is formed, a conductive material such as Pt is formed on the upper surface including the contact hole 32, and the contact hole 32 is filled with the conductive material.

Fourth Step The conductive material and the first interlayer insulating film 31 are flatly polished by chemical mechanical polishing or the like to form the plug 33 and the lower electrode 34, and the first interlayer insulating film 31 is formed to the depth of the plug 33. Etching.

Fifth Step Further, strontium titanate (SrTiO 3) is added._Three, S
A ferroelectric layer 35 such as TO) is formed, and a drive is formed thereon.
Form line 36. And on top of that Si₂O _ThreeEmpty
Forming a second interlayer insulating film 37 on which the upper wiring 3 is formed.
8 is formed to complete the nonvolatile RAM.

Also in the nonvolatile RAM of this embodiment, as in the DRAM of the first embodiment, in the manufacturing process, oxidation of the plug connected to the lower electrode can be prevented, and its resistance value is several tens Ω. Can be reduced to a degree,
The leakage current of the capacitor could be reduced.

In the above embodiment of the present invention, D
Although the configurations of the RAM and the non-volatile RAM and the manufacturing method thereof have been described, the present invention is not limited to the DRAM and the non-volatile RAM, and in general, a high dielectric layer, a ferroelectric layer and the like that are easily oxidized by an oxidizing atmosphere. It goes without saying that it can be applied to a semiconductor device using a coating.

[0034]

As described above, according to the present invention,
By forming a barrier layer at the bottom of the plug,
It is possible to prevent the barrier layer and plug from increasing in resistance and becoming an insulator due to oxidation. Also, since the dielectric layer is not in contact with the barrier layer, it prevents the thickness of the dielectric layer and the ferroelectric layer from decreasing. can do.

[Brief description of drawings]

FIG. 1 is an explanatory view (1) of a manufacturing process of a semiconductor device according to a first embodiment, in which (A) to (D) show each process.

FIG. 2 is a manufacturing process explanatory view (2) of the semiconductor device according to the first embodiment, in which (E) to (G) show each process.

FIG. 3 is a configuration explanatory diagram of a semiconductor device according to a second embodiment.

FIG. 4 is a diagram showing the structure of a conventional DRAM using a high dielectric.

[Explanation of symbols]

 1 Silicon Substrate 2 LOCOS Oxide Film 3 Source Region 4 Drain Region 5 Gate Insulation Film 6,7 Word Line 8 Protective Film 9 Barrier Layer 10 Bit Line 11 First Interlayer Insulation Film 12 Contact Hole 13 Conductive Material 14 Plug 15 Lower Electrode 16 Dielectric layer 17 Upper electrode 18 Second interlayer insulating film 19 Upper wiring 21 Silicon substrate 22 LOCOS oxide film 23 Source region 24 Drain region 25 Gate insulating film 26, 27 Word line 28 Protective film 29 Barrier layer 30 Bit line 31 First Interlayer insulating film 32 Contact hole 33 Plug 34 Lower electrode 35 Ferroelectric layer 36 Drive line 37 Second interlayer insulating film 38 Upper wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/792

Claims (5)

[Claims] 1. A lower electrode and a barrier layer are provided under a dielectric layer, and the barrier layer is formed under a plug which is a lower layer of an interlayer insulating film connected to the lower electrode. Semiconductor device. 2. The DRAM is characterized in that the dielectric layer is a high-dielectric layer, and a capacitor having a capacitor composed of the high-dielectric layer and electrodes sandwiching the high-dielectric layer as a storage capacitor is provided. The semiconductor device described in. 3. The non-volatile RAM, wherein the dielectric layer is a ferroelectric layer, and a storage capacitor is a capacitor including an electrode sandwiching the ferroelectric layer and the ferroelectric layer. 1. The semiconductor device described in 1. 4. A switching transistor is formed on a semiconductor substrate, a barrier layer is formed in a region where a plug is to be formed on the switching transistor, and an interlayer insulating film is formed on the barrier layer to a height higher than that of a lower electrode of a capacitor. To form
A contact hole reaching the barrier layer for forming the lower electrode of the capacitor and the plug is formed in the interlayer insulating film, and a plug forming conductor layer is formed on the upper surface including the contact hole, and the interlayer insulating film is formed. The conductive layer for forming a plug is removed to the height of the lower electrode to planarize it, the interlayer insulating film is etched to expose the lower electrode of the capacitor, and a high dielectric layer is formed on the lower electrode. A method of manufacturing a semiconductor device, comprising the step of forming an upper electrode on the high dielectric layer to form a DRAM. 5. A switching transistor is formed on a semiconductor substrate, a barrier layer is formed in a region where a plug is to be formed on the switching transistor, and an interlayer insulating film is formed on the barrier layer at a height higher than that of a lower electrode of a capacitor. To form
A contact hole reaching the barrier layer for forming the lower electrode of the capacitor and the plug is formed in the interlayer insulating film, and a plug forming conductor layer is formed on an upper surface including the contact hole. The plug forming conductor layer is removed to the height of the lower electrode to be planarized, the interlayer insulating film is etched to expose the lower electrode of the capacitor, and a ferroelectric layer is formed on the lower electrode. A method of manufacturing a semiconductor device, comprising: forming an upper electrode on the ferroelectric layer to form a nonvolatile RAM.