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US20040259307A1 - Semiconductor memory device having plug contacted to a capacitor electrode and method for fabricating a capacitor of the semiconductor memory devcie - Google Patents

Semiconductor memory device having plug contacted to a capacitor electrode and method for fabricating a capacitor of the semiconductor memory devcie Download PDF

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US20040259307A1
US20040259307A1 US10217401 US21740103A US2004259307A1 US 20040259307 A1 US20040259307 A1 US 20040259307A1 US 10217401 US10217401 US 10217401 US 21740103 A US21740103 A US 21740103A US 2004259307 A1 US2004259307 A1 US 2004259307A1
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layer
formed
semiconductor
electrode
diffusion
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US10217401
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Kwon Hong
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SK Hynix Inc
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SK Hynix Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/75Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28568Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising transition metals
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • H01L27/10852Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor
    • H01L27/10855Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor with at least one step of making a connection between transistor and capacitor, e.g. plug
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/55Capacitors with a dielectric comprising a perovskite structure material

Abstract

The present invention provides a semiconductor memory device and a method capable of preventing the contact between a dielectric layer of a capacitor and a diffusion barrier. The plug to be contacted to an electrode of a capacitor, comprises a diffusion barrier layer and a conducting layer. The conducing layer is formed with a material capable of flowing current nevertheless the conducting layer is oxidized. Accordingly, it is possible to prevent the dielectric layer being contacted with the diffusion barrier, there by the leakage current may be reduced, and the capacitance of the capacitor may be increased.

Description

    FIELD OF THE INVENTION
  • [0001]
    The present invention relates to a method for fabricating a semiconductor memory device; and more particularly, to a method for fabricating a capacitor of semiconductor memory device.
  • DESCRIPTION OF THE PRIOR ART
  • [0002]
    A DRAM (Dynamic Random Access Memory) cell is a semiconductor memory device typically comprising one transistor and one capacitor, in which one bit of data is stored in a cell by using an electric charge. A capacitor comprises of a lower electrode, a dielectric layer, and an upper electrode. One electrode of the capacitor is connected to the source/drain junction of the transistor. Another electrode of the capacitor is connected to a reference voltage line.
  • [0003]
    Advances in computer applications have increased the demand for higher capacity memory chips. Decreasing the size of the memory cells allows more memory cells to be packed into an integrated circuit.
  • [0004]
    The capacitance of a capacitor is proportional to the surface area of the electrodes and a dielectric constant of a dielectric layer. As the area of the memory cell has decreased, the capacitance of the capacitors tends to decrease also, lowering the performance of the memory cells.
  • [0005]
    In order to increase the density of memory cells, stacked capacitors have been proposed. Stacked capacitors are formed by partially stacking the storage electrode over the transistor and over the bit/word line, thereby effectively reducing the area used for each memory cell.
  • [0006]
    A plug is used to connect the lower electrode of the capacitor with the source/drain junction of the transistor.
  • [0007]
    A method for fabricating a capacitor of a semiconductor memory device according to the conventional method is described referring to FIG. 1A to FIG. 1C.
  • [0008]
    As shown in FIG. 1A, an insulating layer 15 is formed over a semiconductor substrate 10, an isolation layer 11, such as field oxide layer, and a transistor comprising a gate insulating layer 12, a gate electrode 13 and the source/drain junctions 14. Thereafter, a plug 16 is formed in the interlayer insulating layer. The plug 16 is composed of a ploysilicon layer 16A, an ohmic contact layer 16B and a diffusion barrier layer 16C formed in a contact hole, exposing one of the source/drain junctions 14.
  • [0009]
    As shown in FIG. 1B, a lower electrode 17 is formed on the diffusion barrier layer 16C by depositing and patterning a first conductive layer. The diffusion barrier layer 16C may be exposed during the formation of the lower electrode 17 because of a mask misalignment. The mask misalignment is frequently occurred in a manufacturing process of a highly integrated device.
  • [0010]
    As shown in FIG. 1C, a dielectric layer 18 is formed on the lower electrode 17 and an upper electrode 19 is formed on the dielectric layer 18. The dielectric layer 18 is formed with a material exhibiting a very high dielectric constant, such as Barium strontium titanate (BaSrTiO3, hereafter abbreviated BST), to increase the capacitance in a highly integrated device.
  • [0011]
    According to the preceding conventional method, the exposed part of the diffusion barrier layer 16C of the plug 16 is contacted to the dielectric layer 18.
  • [0012]
    There are several problems generated by the contact between the diffusion layer 16C and the dielectric layer 18. One problem is that the diffusion barrier layer 16C is oxidized during the process for forming the dielectric layer 18, because the dielectric layer 18, such as the BST layer, is formed under oxygen gas atmosphere and at high temperature. The oxidized part of the diffusion barrier layer 16C, exhibiting low dielectric constant, plays a role of a dielectric layer of a capacitor, thereby the capacitance of the capacitor is reduced. The other problem is that the work function difference, between the diffusion barrier 16C and the dielectric layer 18, is low, thereby the leakage current is increased because of the low Schottky barrier height.
  • SUMMARY OF THE INVENTION
  • [0013]
    It is, therefore, an object of the present invention to provide a semiconductor memory device and a fabrication method capable of preventing the contact between a dielectric layer of a capacitor and a diffusion barrier of a plug.
  • [0014]
    It is, therefore, another object of the present invention to provide a semiconductor memory device and a fabrication method capable of preventing the lowering the capacitance of a capacitor and the increasing the leakage current between the lower electrode of a capacitor and a diffusion barrier of a plug.
  • [0015]
    In accordance with an aspect of the present invention, there is provided a semiconductor memory device, comprising: a semiconductor substrate, wherein a gate electrode is formed on the semiconductor substrate, and wherein source/drain junctions are formed in the semiconductor substrate; an interlayer insulating layer formed over the semiconductor substrate; a plug formed in the interlayer insulating layer, wherein the plug comprises a diffusion barrier layer and a conducting layer, and wherein the conducing layer is formed with a material capable of flowing current nevertheless the conducting layer is oxidized; a lower electrode of capacitor contacted to the conducing layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer.
  • [0016]
    In accordance with another aspect of the present invention, there is provided a method for fabricating semiconductor memory device, comprising the steps of: providing a semiconductor substrate, wherein a gate electrode is formed on the semiconductor substrate, and wherein source/drain junctions are formed in the semiconductor substrate; forming an interlayer insulating layer over the semiconductor substrate; etching the interlayer insulating layer to form a contact hole; forming a diffusion barrier layer and a conducting layer in the contact hole to form a plug, wherein the conducing layer is formed with a material capable of flowing current nevertheless the conducting layer is oxidized; forming a lower electrode contacted to the conducting layer; forming a dielectric layer on the lower electrode; and forming an upper electrode on the dielectric layer.
  • [0017]
    In accordance with still further another aspect of the present invention, there is a method for fabricating semiconductor memory device, comprising the steps of: providing a semiconductor substrate, wherein a gate electrode is formed on the semiconductor substrate, and wherein source/drain junctions are formed in the semiconductor substrate; forming an interlayer insulating layer over the semiconductor substrate; etching the interlayer insulating layer to form a contact hole; forming a plug, wherein a diffusion barrier and a conducting layer in the contact hole to form the plug, and wherein the conducing layer is formed with a material capable of flowing current nevertheless, the conducting layer is oxidized; forming a seed layer on the conducting layer; forming a glue layer on the seed layer; forming a sacrificial layer on glue layer; etching the sacrificial layer and the glue layer to form a opening defining a region of a lower electrode; forming a lower electrode on the seed layer in the opening; removing the sacrificial layer and the seed layer; forming a dielectric layer on the lower electrode; and forming a upper electrode on the dielectric layer.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0018]
    The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:
  • [0019]
    [0019]FIG. 1A to FIG. 1C are cross sectional views showing a method for fabricating a semiconductor memory device according to the conventional method.
  • [0020]
    [0020]FIG. 2A to FIG. 2I are cross sectional views showing a method for fabricating a capacitor of a semiconductor device according to an embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0021]
    Hereinafter, a semiconductor memory device fabrication method according to embodiments of the present invention will be described in detail referring to the accompanying drawings.
  • [0022]
    As shown in FIG. 2A, an interlayer insulating layer, composed of a first insulating layer 21 and a second insulting layer 22, is formed over a semiconductor substrate 20, on which a determined lower structure (not shown), comprising an isolation layer, such as a field oxide layer, and a transistor including a gate insulating layer, a gate electrode and the source/drain junctions. The second insulating layer 22 is formed with a material of which etching selectivity is higher than the first insulating layer 21. In a preferred embodiment of the present invention, the first insulating layer 21 is formed by depositing a silicon oxide layer to a thickness of 3000-8000 Å, and the second insulating layer 22 is formed by depositing a silicon nitride layer to a thickness of 300 to 1000 Å.
  • [0023]
    As shown in FIG. 2B, the second insulating layer 22 and the first insulating layer 21 are etched to form a contact hole 100 exposing one of the source/drain junction (not shown) formed in the semiconductor substrate 20. And then, a polysilicon layer 23A, for forming a plug is deposited to a thickness of 500-3000 Å on the second insulating layer 22 and the on semiconductor substrate 20 in the contact hole. Thereafter, an etching process is performed to expose the surface of the second insulting layer 22 and to remove a part of the polysilicon layer 23A in the contact hole. Thereby, the height difference 200 between the surface of the second insulating layer 22 and the surface of the polysilicon layer 23A becomes 500 to 1500 Å.
  • [0024]
    As sown in FIG. 2C, an ohmic contact layer 23B and a diffusion barrier layer 23C are formed, one by one, on the polysilicon layer 23A. Subsequently, a chemical mechanical polishing (hereafter, abbreviated CMP) process is performed until the surface of the second insulating layer 22 is exposed. In a preferred embodiment of the present invention, the ohmic contact layer 23B is formed with TiSix, and the diffusion barrier layer 23C is formed with TiN, TiSiN, TiAlN, TaSiN, TaAlN, IrO2 or RuO2. For forming the TiSix, a Ti layer is deposited, an annealing process is performed for reaction between Ti atom in the titanium layer and Si atom in the polysilicon layer 23A, and a wet etching process is performed to remove the Ti layer remaining on the second insulating layer 22 and the TiSix layer.
  • [0025]
    As shown in FIG. 2D, a part of the diffusion barrier layer 23C is etched using an etchant, such as a mixed gas comprising Cl2 and BCl3, to which the diffusion barrier layer 23C has higher etching selectivity than the second insulting layer 22.
  • [0026]
    As shown in FIG. 2E, a conducting layer 23D is deposited on the second insulating layer 22 and the diffusion barrier layer 23C, and a blanket etching process or a CMP process is performed until the second insulating layer 22 is exposed. Thereby, the plug 23 composed of polysilicon layer 23A, the ohmic contact layer 23B, the diffusion barrier 23C and the conducting layer 23D a, is completely formed. The conducting layer 23D is formed with a material which can flow current even if it is oxidized. In the preferred embodiment of the present invention, Ru, Pt or Ir is deposited by using chemical vapor deposition technique, for forming the conducting layer 23D. On the other hand, the blanket etching process or the CMP process may be skipped, in order to use the conducting layer 34D as a seed layer for forming a lower electrode of a capacitor.
  • [0027]
    Also, the process for forming the polysilicon layer 23A may be omitted, in such case, the plug 23 is composed of the ohmic contact layer 23B layer, the diffusion barrier layer 23C and the conducting layer 24D. Moreover, the process for forming the ohmic contact layer 23B can be omitted, in such a case, the plug 23 is composed of the polusilicon layer 23A, diffusion barrier layer 23C and the conducting layer 24D. Accordingly, it is possible that the plug 23 is composed of the diffusion barrier layer 23C and the conducting layer 23D.
  • [0028]
    As shown in FIG. 2F, a seed layer 24 is formed on the conducting layer 23D and the second insulating layer 22, thereafter a glue layer 25 and a sacrificial layer 26 are stacked, one by one, on the seed layer 24. In the preferred embodiment of the present invention, the seed layer 24 is formed with Pt or Ru 50-100 Å thick, the glue layer 25 is formed with. TiN, TiAlN, TaN, TaSiN, Al2O3 or TiO2 50-500 Å thick, and the sacrificial layer 26 is formed with silicon oxide 5000-15000 Å thick. In case that the conducting layer 23D is formed
  • [0029]
    On the other hand, the processes for forming the seed layer 24 and the glue layer 25 can be omitted depending the various methods for forming a lower electrode.
  • [0030]
    As shown in FIG. 2G, the sacrificial layer 26 and the glue layer 25 is selectively etched to form opening 300 exposing the seed layer 24, and a lower electrode 27 is formed on the seed layer 24 in the opening 300. In the preferred embodiment of the present invention, a Pt layer as the lower electrode 27, is deposited to a thickness of 4000-12000 Å by the electroplating. A current density of 0.1-20 mA/cm2 is imposed on electrodes for electroplating, with DC or DC pulse.
  • [0031]
    As shown FIG. 2H, the sacrificial layer 26, the glue layer 25 and the seed layer 24 are removed to separate neighboring the lower electrodes 27. The sacrificial layer 26 and the glue layer 25 are removed by a wet etching, and the seed layer 24 is removed by a dry etching. Also, the glue layer 25 can be removed by a dry etching.
  • [0032]
    According to the preceding process of the present invention, the diffusion barrier layer 23C of the plug 23 is not exposed, even if the mask misalignment is occurred in the process for forming the opening 300. That is, the conducting layer 23D, covering the diffusion layer 23C, is exposed in case of occurring the mask misalignment.
  • [0033]
    As shown in FIG. 2I, a dielectric layer 28 is deposited on the lower electrode 27 and the second insulating layer 22. Thereafter, an upper electrode 29 is formed on the dielectric layer 28. In the preferred embodiment of the present invention, a BST layer is deposited to a thickness of 150-500 Å at a temperature of 350-600° C. for forming the dielectric layer 28, and an annealing for crystallizing the dielectric layer 28 is performed in an N2 gas atmosphere at a temperature of 500-700° C. for 30-180 seconds, thereby dielectric characteristic of the dielectric layer 28 may be improved. The upper electrode 29 is formed with a material, which can flow current even if it is oxidized, such as Pt, Ru, Ir.
  • [0034]
    There are several advantages to form the conducing layer on the diffusion barrier. A first advantage is that it is possible to prevent the dielectric layer being contacted with the diffusion barrier. A second advantage is that it is possible to reduce the leakage current. A third advantage is that it is possible to prevent the diffusion barrier from being exposed even if the mask misalign is occurred, thereby the annealing for crystallizing the dielectric layer can be performed at a high temperature. A fourth advantage is that it is possible to obtain high capacitance of the capacitor in the highly integrated semiconductor device.
  • [0035]
    Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims (18)

    What is claimed is:
  1. 1. A semiconductor memory device, comprising:
    a semiconductor substrate, wherein a gate electrode is formed on the semiconductor substrate, and wherein source/drain junctions are formed in the semiconductor substrate;
    an interlayer insulating layer formed over the semiconductor substrate;
    a plug formed in the interlayer insulating layer, wherein the plug comprises a diffusion barrier layer and a conducting layer, and wherein the conducing layer is formed with a material capable of flowing current nevertheless the conducting layer is oxidized;
    a lower electrode of capacitor contacted to the conducing layer;
    a dielectric layer formed on the lower electrode; and
    an upper electrode formed on the dielectric layer.
  2. 2. The semiconductor device as recited in claim 1, the conducting layer is selected from a group consisting of Ru layer, Ir layer, Pt layer and Ir layer.
  3. 3. The semiconductor device as recited in claim 1, the diffusion barrier layer is selected from a group consisting of TiN layer, TiSiN layer, TiAlN layer, TaSiN layer, TaAlN layer, IrO2 layer and RuO2 layer.
  4. 4. The semiconductor device as recited in claim 1, further comprising a polysilicon layer between the diffusion barrier layer and the semiconductor substrate.
  5. 5. The semiconductor device as recited in claim 1, further comprising an ohmic contact layer between the diffusion barrier layer and the semiconductor substrate.
  6. 6. The semiconductor device as recited in claim 5, further comprising a polysilicon layer between the ohmic contact layer and the semiconductor substrate.
  7. 7. A method for fabricating semiconductor memory device, comprising the steps of:
    providing a semiconductor substrate, wherein a gate electrode is formed on the semiconductor substrate, and wherein source/drain junctions are formed in the semiconductor substrate;
    forming an interlayer insulating layer over the semiconductor substrate;
    etching the interlayer insulating layer to form a contact hole;
    forming a diffusion barrier layer and a conducting layer in the contact hole to form a plug, wherein the conducing layer is formed with a material capable of flowing current nevertheless the conducting layer is oxidized;
    forming a lower electrode contacted to the conducting layer;
    forming a dielectric layer on the lower electrode; and
    forming an upper electrode on the dielectric layer.
  8. 8. The method as recited in claim 7, wherein the conducting layer is formed with Ir, Pt or Ru.
  9. 9. The method as recited in claim 8, the lower electrode is formed by an electroplating by using the conducting layer as a see layer.
  10. 10. The method as recited in claim 7, wherein the diffusion barrier layer is formed with TiN, TiSiN, TiAlN, TaSiN, TaAlN, IrO2 or RuO2.
  11. 11. The method as recited in claim 7, wherein the dielectric layer is formed with BaSrTiO3 layer, and wherein the upper electrode is formed with Pt layer, Ru layer or Ir layer.
  12. 12. A method for fabricating semiconductor memory device, comprising the steps of:
    providing a semiconductor substrate, wherein a gate electrode is formed on the semiconductor substrate, and wherein source/drain junctions are formed in the semiconductor substrate;
    forming an interlayer insulating layer over the semiconductor substrate;
    etching the interlayer insulating layer to form a contact hole;
    forming a plug, wherein a diffusion barrier and a conducting layer in the contact hole to form the plug, and wherein the conducing layer is formed with a material capable of flowing current nevertheless the conducting layer is oxidized;
    forming a seed layer on the conducting layer;
    forming a glue layer on the seed layer;
    forming a sacrificial layer on glue layer;
    etching the sacrificial layer and the glue layer to form a opening defining a region of a lower electrode;
    forming a lower electrode on the seed layer in the opening;
    removing the sacrificial layer and the seed layer;
    forming a dielectric layer on the lower electrode; and
    forming a upper electrode on the dielectric layer.
  13. 13. The method as recited in claim 12, the step of forming the plug including:
    forming the diffusion barrier layer in the contact hole;
    etching the diffusion barrier to remove a part of the diffusion barrier layer in the contact hole; and
    forming the conducting layer on the diffusion barrier layer.
  14. 14. The method as recited in claim 12, wherein the lower electrode is formed by an electroplating.
  15. 15. The method as recited in claim 13, wherein the conducting layer is formed with Ir, Pt or Ir, and wherein the diffusion barrier layer is formed with TiN, TiSiN, TiAlN, TaSiN, TaAlN, IrO2 or RuO2.
  16. 16. The method as recited in claim 15, wherein a silicon oxide layer and a nitride layer are staked to form the interlayer insulating layer.
  17. 17. The method as recited in claim 16, wherein the diffusion barrier layer is etched with a mixed gas comprising Cl2 and BCl3.
  18. 18. The method as recited in claim 16, the dielectric layer is formed with a BaSrTiO3 layer, and wherein the upper electrode is formed with Pt layer, Ru layer or Ir layer.
US10217401 2000-06-19 2003-10-09 Semiconductor memory device having plug contacted to a capacitor electrode and method for fabricating a capacitor of the semiconductor memory devcie Abandoned US20040259307A1 (en)

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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6451666B2 (en) * 1999-12-27 2002-09-17 Hyundai Electronics Industries Co., Ltd Method for forming a lower electrode by using an electroplating method
KR100676534B1 (en) * 2000-06-28 2007-01-30 주식회사 하이닉스반도체 Method of manufacturing a capacitor in a semiconductor device
KR100390952B1 (en) * 2000-06-28 2003-07-10 주식회사 하이닉스반도체 Method of manufacturing a capacitor
KR100646947B1 (en) * 2000-06-29 2006-11-17 주식회사 하이닉스반도체 Method of manufacturing a capacitor in a semiconductor device
US6818935B2 (en) * 2001-09-12 2004-11-16 Hynix Semiconductor Inc. Semiconductor device and method for fabricating the same
KR100448852B1 (en) * 2001-12-26 2004-09-18 주식회사 하이닉스반도체 Method for manufacturing a capacitor of semiconductor device
KR100443361B1 (en) * 2002-04-26 2004-08-09 주식회사 하이닉스반도체 Method for fabricating capacitor using electro chemical deposition
KR100875647B1 (en) 2002-05-17 2008-12-24 주식회사 하이닉스반도체 A capacitor of a semiconductor device forming method
JP2003347427A (en) 2002-05-23 2003-12-05 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
KR100500940B1 (en) * 2002-06-21 2005-07-14 주식회사 하이닉스반도체 Method for fabricating capacitor in semiconductor device
KR100480601B1 (en) * 2002-06-21 2005-04-06 삼성전자주식회사 Semiconductor memory device and manufacturing method thereof
KR100800136B1 (en) * 2002-06-28 2008-02-01 주식회사 하이닉스반도체 Method for fabricating semiconductor device
KR100870315B1 (en) * 2002-07-18 2008-11-25 매그나칩 반도체 유한회사 Method for manufacturing semiconductor device
KR100859949B1 (en) 2002-07-19 2008-09-23 매그나칩 반도체 유한회사 Method for manufacturing analog semiconductor device
KR100782790B1 (en) 2002-07-30 2007-12-05 동부일렉트로닉스 주식회사 Semiconductor device and fabrication method of thereof
US8480006B2 (en) * 2006-09-08 2013-07-09 Ventech, Llc Vehicle supplemental heating system

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5392189A (en) * 1993-04-02 1995-02-21 Micron Semiconductor, Inc. Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for forming same
US5825609A (en) * 1996-04-23 1998-10-20 International Business Machines Corporation Compound electrode stack capacitor
US5877062A (en) * 1996-11-13 1999-03-02 Samsung Electronics Co., Ltd. Methods of forming integrated circuit capacitors having protected diffusion barrier metal layers therein
US5892254A (en) * 1997-02-27 1999-04-06 Samsung Electronics Co., Ltd. Integrated circuit capacitors including barrier layers having grain boundary filling material
US5994153A (en) * 1996-11-05 1999-11-30 Sony Corporation Fabrication process of a capacitor structure of semiconductor memory cell
US6162744A (en) * 1998-02-28 2000-12-19 Micron Technology, Inc. Method of forming capacitors having high-K oxygen containing capacitor dielectric layers, method of processing high-K oxygen containing dielectric layers, method of forming a DRAM cell having having high-K oxygen containing capacitor dielectric layers
US6165834A (en) * 1998-05-07 2000-12-26 Micron Technology, Inc. Method of forming capacitors, method of processing dielectric layers, method of forming a DRAM cell
US6194752B1 (en) * 1997-06-16 2001-02-27 Sanyo Electric Co., Ltd. Dielectric device, dielectric memory and method of fabricating the same
US6235579B1 (en) * 1999-10-18 2001-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing stacked capacitor
US6235603B1 (en) * 1999-07-12 2001-05-22 Motorola Inc. Method for forming a semiconductor device using an etch stop layer
US6255187B1 (en) * 1999-04-21 2001-07-03 Samsung Electronics Co., Ltd. Method of fabricating self-aligning stacked capacitor using electroplating method
US20010010956A1 (en) * 1999-12-28 2001-08-02 Hong Suk-Kyoung Method for manufacturing semiconductor memory device incorporating therein copacitor
US6291250B1 (en) * 1999-06-03 2001-09-18 Oki Electric Industry, Co., Ltd. Method for manufacturing semiconductor memory device
US6326294B1 (en) * 2000-04-27 2001-12-04 Kwangju Institute Of Science And Technology Method of fabricating an ohmic metal electrode for use in nitride compound semiconductor devices
US6335241B1 (en) * 1998-08-07 2002-01-01 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US6348420B1 (en) * 1999-12-23 2002-02-19 Asm America, Inc. Situ dielectric stacks
US6355492B1 (en) * 1997-01-22 2002-03-12 Sony Corporation Process for the manufacturing of oxide electrodes for ferroelectric capacitor

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09102591A (en) * 1995-07-28 1997-04-15 Toshiba Corp Semiconductor device and manufacture thereof
KR100215867B1 (en) * 1996-04-12 1999-08-16 구본준 Capacitor of semiconductor device and its fabrication method
KR100219506B1 (en) * 1996-12-04 1999-09-01 윤종용 A capacitor manufacturing method of semiconductor device
KR100230402B1 (en) * 1996-12-31 1999-11-15 윤종용 Capacitor of semiconductor device and manufacturing method thereof
JPH1174487A (en) * 1997-06-30 1999-03-16 Fujitsu Ltd Semiconductor device and manufacture thereof
KR100474989B1 (en) * 1997-07-15 2005-02-24 삼성전자주식회사 Manufacturing method of capacitor with barrier layer for semiconductor device
JP3549715B2 (en) * 1997-10-15 2004-08-04 シンメトリクス コーポレーション The method of manufacturing Bi layered ferroelectric thin film
JPH11265984A (en) * 1998-03-17 1999-09-28 Sony Corp Manufacture of semiconductor device
KR100300046B1 (en) * 1998-05-26 2001-06-13 김영환 Fabricating method of semiconductor device
CN1516275A (en) * 1998-07-03 2004-07-28 松下电器产业株式会社 Semiconductor device and its mfg. method
KR20000026967A (en) * 1998-10-24 2000-05-15 김영환 Capacitor of semiconductor device and method for forming the same
JP3559234B2 (en) * 2000-01-13 2004-08-25 華邦電子股▲ふん▼有限公司 Contact plug and a manufacturing method thereof for pillar type storage node
US6326315B1 (en) * 2000-03-09 2001-12-04 Symetrix Corporation Low temperature rapid ramping anneal method for fabricating layered superlattice materials and making electronic devices including same
JP2001274349A (en) * 2000-03-24 2001-10-05 Mitsubishi Electric Corp Semiconductor device and its manufacturing method

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5392189A (en) * 1993-04-02 1995-02-21 Micron Semiconductor, Inc. Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for forming same
US5825609A (en) * 1996-04-23 1998-10-20 International Business Machines Corporation Compound electrode stack capacitor
US5994153A (en) * 1996-11-05 1999-11-30 Sony Corporation Fabrication process of a capacitor structure of semiconductor memory cell
US5877062A (en) * 1996-11-13 1999-03-02 Samsung Electronics Co., Ltd. Methods of forming integrated circuit capacitors having protected diffusion barrier metal layers therein
US6355492B1 (en) * 1997-01-22 2002-03-12 Sony Corporation Process for the manufacturing of oxide electrodes for ferroelectric capacitor
US5892254A (en) * 1997-02-27 1999-04-06 Samsung Electronics Co., Ltd. Integrated circuit capacitors including barrier layers having grain boundary filling material
US6194752B1 (en) * 1997-06-16 2001-02-27 Sanyo Electric Co., Ltd. Dielectric device, dielectric memory and method of fabricating the same
US6162744A (en) * 1998-02-28 2000-12-19 Micron Technology, Inc. Method of forming capacitors having high-K oxygen containing capacitor dielectric layers, method of processing high-K oxygen containing dielectric layers, method of forming a DRAM cell having having high-K oxygen containing capacitor dielectric layers
US6165834A (en) * 1998-05-07 2000-12-26 Micron Technology, Inc. Method of forming capacitors, method of processing dielectric layers, method of forming a DRAM cell
US6335241B1 (en) * 1998-08-07 2002-01-01 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US6255187B1 (en) * 1999-04-21 2001-07-03 Samsung Electronics Co., Ltd. Method of fabricating self-aligning stacked capacitor using electroplating method
US6291250B1 (en) * 1999-06-03 2001-09-18 Oki Electric Industry, Co., Ltd. Method for manufacturing semiconductor memory device
US6235603B1 (en) * 1999-07-12 2001-05-22 Motorola Inc. Method for forming a semiconductor device using an etch stop layer
US6235579B1 (en) * 1999-10-18 2001-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing stacked capacitor
US6348420B1 (en) * 1999-12-23 2002-02-19 Asm America, Inc. Situ dielectric stacks
US20010010956A1 (en) * 1999-12-28 2001-08-02 Hong Suk-Kyoung Method for manufacturing semiconductor memory device incorporating therein copacitor
US6326294B1 (en) * 2000-04-27 2001-12-04 Kwangju Institute Of Science And Technology Method of fabricating an ohmic metal electrode for use in nitride compound semiconductor devices

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