JPH07169854A - Semiconductor device and manufacture of it - Google Patents

Abstract

PURPOSE:To prevent the counter diffusion of elements by providing a barrier layer made of an oxide film of Ti on a layer insulating film, a ferroelectric thin film burying lower electrode material in the layer and covering the lower electrode material, and an upper electrode, and preventing the layer insulating film from touching the ferroelectric thin film. CONSTITUTION:A thin TiO2 film 9 being a barrier layer is provided on a layer insulating film 3. Then a well-shaped lower electrode burying hole is formed in the thin TiO2 film 9, and a lower electrode 4 is made. The lower electrode is ground until flattened surfaces of the barrier layer 9 and the lower electrode 4 appear by grinding by the use of mechanical or chemical reaction. On these surfaces a thin PZT film is made. The TiO2 layer 9 functions as a counter diffusion barrier between the PZT layer 5 and the layer insulating film 3 at the time of the manufacture of the thin PZT film. Consequently, it becomes possible to prevent the counter diffusion between the thin PZT film and SiO2, and to form a capacity insulating film on a flat surface without etching the lower electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device incorporated in a semiconductor integrated circuit device and a manufacturing method thereof.

[0002]

2. Description of the Related Art By using a ferroelectric thin film as a capacitive insulating film in a semiconductor memory cell, a nonvolatile memory capable of high-speed writing and reading or a ferroelectric thin film having a large relative dielectric constant is capacitively insulated. A highly integrated dynamic random access memory (DRAM) used as a film can be manufactured. When manufacturing such a memory cell, an oxide ferroelectric thin film mainly containing Pb or Bi as a component is used as a capacitive insulating film. As a conventional technology, "16 kilobit ferroelectric nonvolatile memory having a bit parallel structure": Warmack, Toish, Digest of 1989 Eye Triple E International Solid State Circuit Conference, pages 242-243,
1989 ("A 16kb Ferroselectr
ic Nonvolatile Memory wit
ha Bit Parallel Architec
“Ture” ,: R. Womack and D. To
isch, Digestof 1989 IEEE
International Solid-State
Circuits Conference, pp.
242-243, Feb. 1989) has been used. That is, as shown in FIG. 1, after the lower electrode 4 formed on the conductive barrier layer for preventing mutual diffusion with the interlayer insulating film 3 or polycrystalline silicon is finely processed, the ferroelectric thin film 5 is heated to 600 ° C. It is formed at the film forming temperature before and after. After that, the ferroelectric thin film is finely processed to form the upper electrode 6, the element isolation film 7, and the Al wiring 8.

[0003]

However, the conventional memory cell manufacturing technique has the following drawbacks. That is, SiO ₂ is generally used as the interlayer insulating film, but when a ferroelectric thin film containing Pb as a component is formed on a finely processed electrode pattern at a film forming temperature of about 600 ° C., the electrode is covered. Pb and Si interdiffuse between the uninsulated portion of the interlayer insulating film and the ferroelectric thin film. Due to this mutual diffusion, the characteristics of semiconductor elements such as transistors located under the interlayer insulating film deteriorate, and the characteristics of the ferroelectric thin film on the electrode deteriorate through the ferroelectric thin film directly above the interlayer insulating film. there were.

Further, Pt, which is generally used as a lower electrode material for a ferroelectric substance, has poor reactivity, and Pt once etched is redeposited around the side wall of the resist or the like by reactive ion etching. This is one of the factors that reduce the yield of devices because the electrodes cannot be finely processed into the intended shape. In addition, in the structure in which the ferroelectric substance is sandwiched between the lower electrode and the upper electrode, when the lower electrode and the ferroelectric substance are continuously deposited, mutual diffusion of the elements as described above does not occur, but the final shape In the etching process for obtaining the above, there is a problem that Pt is redeposited on the side wall of the ferroelectric substance and the lower electrode and the upper electrode are short-circuited. Further, since the step coverage is poor depending on the method of manufacturing the ferroelectric thin film, the stepped portion caused by the processing of the lower electrode causes the element failure.

[0005]

According to the present invention, a barrier layer made of an oxide of Ti is layered on an interlayer insulating film, a lower electrode material is embedded in the layer, and the lower electrode material is covered. The present invention relates to a semiconductor device structure comprising a ferroelectric thin film and an upper electrode, and a manufacturing method thereof.

According to the shape of the semiconductor device of the present invention,
Since the oxide layer of Ti eliminates the portion where the interlayer insulating film containing SiO ₂ as a component and the ferroelectric thin film are in contact, the problem of mutual diffusion of elements is solved. In other words, since this barrier layer does not interdiffuse with Si, which is the main component of the interlayer insulating film, and Pb contained in the capacitor insulating film even at the ferroelectric thin film manufacturing temperature, as a result, Pb penetrates into the interlayer insulating film, and It has a function of suppressing the penetration of Si into the ferroelectric thin film.
Therefore, it is possible to prevent deterioration of the ferroelectric thin film and elements such as transistors. As a barrier layer, T
In order to use the oxide of i, the oxide of Ti may be deposited from the beginning, but metal Ti is deposited to form a ferroelectric substance.
It is also possible to perform oxidation at the same time in the processing stage to obtain Ti oxide.

Furthermore, since the buried lower electrode does not form a step with the barrier layer, a highly reliable element can be manufactured regardless of the method of manufacturing the ferroelectric thin film. Further, since the step of etching the lower electrode material is not included, it is possible to select a lower electrode material which is necessary for good ferroelectric film production and which is difficult to perform fine processing.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.

Example 1 In this example, 300 nm TiO ₂ was formed as a barrier layer on an interlayer insulating film by a reactive sputtering method to form a groove having a depth of 200 nm, and 400 nm Pt was DC sputtered as a lower electrode. An example in which a PZT thin film having a thickness of 200 nm is formed as a ferroelectric film by the sol-gel method is shown below. The barrier layer can also be formed by forming metal Ti in a layered form, burying the lower electrode, and then oxidizing Ti at the same time as forming the ferroelectric thin film in an oxygen atmosphere. As the ferroelectric film, in addition to PZT, PbTi
Perovskite type oxide ferroelectrics such as O ₃ and (Pb, La) (Zr, Ti) O ₃ can be used. Also, the sol-gel method is one of the film forming methods in which it is considered difficult to form a thin film having a uniform film thickness on a substrate having a step due to the nature of the film forming method, but it is uniform and good on a flat substrate. It is a film forming method that can obtain a ferroelectric film having characteristics of a thin film having a thickness of 100 nm or less.

FIG. 2 shows a barrier layer TiO ₂ on the interlayer insulating film 3.
This is a structure provided with a thin film 9. After forming a well-shaped lower electrode burying hole in the TiO ₂ thin film 9, the lower electrode 4 is manufactured. The lower electrode is ground by mechanical or chemical polishing until the barrier layer 9 and the flattened surface of the lower electrode 4 are exposed. The PZT thin film 5 is formed on this surface. When the PZT thin film is formed, the TiO ₂ layer 9 is the PZT layer 5
And an inter-layer insulating film 3 function as a mutual diffusion barrier. FIG. 3 shows the composition distribution in the depth direction measured by Auger electron spectroscopy when a PZT thin film is formed after forming a 50 nm TiO ₂ barrier layer on the interlayer insulating film SiO ₂ .
At the PZT / TiO ₂ interface, Pb penetrating from the PZT layer to the barrier layer remains at about 10 nm from the interface, and SiO ₂
There is no Pb penetrating inside. Furthermore, TiO2 / Si
Diffusion of Si is also suppressed at the O ₂ interface, and Si is below the detection limit in the PZT layer. From this result, TiO ₂
It is confirmed that the thin film serves as a diffusion barrier layer during PZT film formation. By the way, the TiO ₂ layer 9 has a parachlore pyrochlore structure which is a metastable phase of PZT. However, since the pyrochlore phase portion is removed by etching together with the TiO ₂ barrier layer after PZT film formation, there is no problem in practical use. Alternatively, the pyrochlore phase portion and the titanium oxide portion can be used as the element isolation film.

(Embodiment 2) In the embodiment shown in FIG. 4, it is necessary to form a contact hole in the interlayer insulating film 3 and connect the lower electrode 4 and the drain of the transistor 2 with the polycrystalline silicon 10 and the Si barrier metal 11. Is shown. After forming the interlayer insulating film 3, a first contact hole is formed and polycrystalline silicon is embedded. Subsequently, the metal Ti layer 9 is produced. In the case of this structure, metal Ti must be used as the barrier layer in order to prevent the polycrystalline silicon from being oxidized. A second contact hole having an area necessary for the area of the capacitor is formed on the buried first contact hole. The second contact hole is sequentially filled with the Si barrier metal 11 and the lower electrode 4 and polished to be flat, and then the PZT thin film 5 is formed thereon.
In this case, the film thickness t1 of the titanium oxide barrier layer 9 and the film thickness t2 of the Si barrier metal 11 that are oxidized when the ferroelectric film is formed.
Must be in the relationship of t1> t2. By manufacturing the memory cell having the above structure, the mutual diffusion of the PZT thin film and SiO ₂ can be prevented as in the case of FIG. ₂ , and the capacitor can be formed on the flat surface without etching the lower electrode. An insulating film can be formed.

Although the above description has been made only for the case where a memory cell capacitor is assumed, the present invention can obtain the same effect in many cases in which a ferroelectric thin film containing Pb is widely applied to semiconductor integrated circuits. .

[Brief description of drawings]

FIG. 1 is a memory cell structure according to the prior art.

FIG. 2 is a memory cell structure according to the present invention.

FIG. 3 is a composition distribution diagram in the depth direction when a PZT thin film is formed on TiO ₂ (50 nm) / SiO ₂ .

FIG. 4 is a memory cell structure according to the present invention in the presence of contacts made of polycrystalline silicon.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Si substrate 2 Transistor 3 Interlayer insulation film 4 Lower electrode 5 PZT thin film 6 Upper electrode 7 Element isolation film 8 Al wiring 9 Titanium oxide barrier layer 10 Polycrystalline silicon 11 Si barrier metal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/822

Claims (2)

[Claims] 1. An interlayer insulating film having a layered oxide of Ti, a lower electrode material embedded in the layer, and a ferroelectric thin film and an upper electrode covering the lower electrode. Characteristic semiconductor device. 2. A layer of Ti or an oxide of Ti is formed on the interlayer insulating film, and a well-shaped groove having an opening area required as an electrode area is formed in the layer, and the well-shaped groove is formed on the well. After forming a lower electrode layer thicker than the depth, a lower electrode structure embedded in a flat surface is formed by polishing the lower electrode layer, and then a ferroelectric film is formed and then the ferroelectric film is formed of Ti. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the upper electrode is formed by processing together with the oxide layer.