JP4459335B2 - Ferroelectric transistor type nonvolatile memory element and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile memory element, and more particularly to a ferroelectric transistor type nonvolatile memory element of a nonvolatile memory using a ferroelectric substance.
[0002]
[Prior art]
Recently, a FeRAM (Ferroe 1 ectric Random Access Memory) using a ferroelectric, which is being developed, has a configuration in which a DRAM capacitor is replaced with a ferroelectric capacitor (Japanese Patent Laid-Open No. 2-113496). The operation is to determine whether the stored information is “1” or “0” by detecting the difference in charge amount between when the polarization of the ferroelectric capacitor is inverted and when it is not inverted. For this reason, it is inevitable that the information held when the information is read is destroyed, so-called destructive reading.
[0003]
Further, in this method, since the charge in the polarization inversion is extracted and detected as a current, the area of the capacitor is reduced and the current value is also reduced, which makes detection difficult. This is a fundamental problem that occurs because the cell structure of FeRAM does not follow the scaling law.
[0004]
In order to compare the amount of charge discharged from the ferroelectric capacitor, it is usually necessary to arrange a pair of reference cells in each cell. Therefore, two transistors 2 are used to form one memory cell. A capacitor is required. Therefore, there is a problem that the memory cell area is twice or more larger than that of a DRAM having the same processing accuracy.
[0005]
On the other hand, a ferroelectric transistor in which a ferroelectric is arranged at a gate portion of a field effect transistor (FET) can constitute a memory cell with a single transistor. In this device, the polarization of the ferroelectric induces the channel charge of the transistor to turn on and off between the source and drain, and even if the cell area is proportionally reduced, the rate of change in drain current does not change. . This means that the memory cell of the ferroelectric transistor follows the scaling rule (Journal of the Institute of Electronics, Information and Communication Engineers 77-9 p976, 1994), and there is no theoretical limit for miniaturization.
[0006]
The above is not only advantageous for reducing the cell area, but also the on / off of the FET is maintained by the polarization of the ferroelectric, so that information is not destroyed by the read operation, so-called nondestructive reading is performed. Is also possible.
[0007]
Further, the ferroelectric transistor in which the ferroelectric is arranged in the gate portion is roughly classified into two types. One of them is a ferroelectric transistor having an MFIS (Metal-Ferroelectric-Insulator-Semiconductor) structure, and the ferroelectric induces electric charges on the surface of the semiconductor substrate through the gate insulating film due to its polarization. One is a ferroelectric transistor having an MFMIS (Metal-Ferroelectric-Metal-Insulator-Semiconductor) structure, in which a metal electrode layer is sandwiched between a ferroelectric layer having an MFIS structure and an insulating layer.
[0008]
FIG. 2 shows the structure of these ferroelectric transistors in an equivalent circuit. From FIG. 2, when a voltage is applied between the upper electrode 25 and the semiconductor substrate 20, the ferroelectric 24 is polarized. From the viewpoint of memory retention characteristics, it is necessary to apply a voltage until the polarization of the ferroelectric material is sufficiently saturated. _F (Capacity of ferroelectric layer) is C ₁ It is important to design so as to be smaller than (capacity of the gate insulating layer). One way to make this design possible is to make the area of the ferroelectric capacitor smaller than the area of the gate insulating layer. For this purpose, an equipotential surface exists under the ferroelectric capacitor. And is realized by the MFMIS structure.
[0009]
In a conventional example of a ferroelectric transistor having an MFMIS structure (T. Nakamura et. Al. Dig. Tech. Pap. Of 1995 IEEE Int. Solid-State Circuits Conf. P. 68 (1995)), FIG. As shown in FIG. 4, a gate insulating oxide film 21, a polycrystalline film 22, a conductive film 23, a ferroelectric film 24, and an electrode 25 such as platinum are sequentially stacked on a semiconductor substrate 20 to form a source (not shown). A ferroelectric memory cell has been proposed in which a drain is formed by a self-alignment method or the like, and a gate electrode or the like is provided above the source and drain. As shown in FIG. 12A, a gate structure comprising a silicon thermal oxide film 21 and a polycrystalline silicon 22 gate electrode is used as a gate insulating film. If the ferroelectric capacitor and the gate portion are processed together, the leakage current at the side wall is large and it is not practical.
[0010]
For this reason, the gate portions of the silicon thermal oxide film 21 and the polycrystalline silicon 22 are produced by a normal self-alignment method, and a ferroelectric capacitor is connected to the transistor via a contact hole formed in the interlayer insulating film. The structure must be taken (FIG. 12B). As shown in FIG. 12B, the ferroelectric memory cell includes a gate insulating oxide film 21, a polycrystalline silicon film 22, a conductive film 23 connected through a contact hole, a ferroelectric film 24, and a semiconductor substrate 20. An electrode 25 of platinum or the like is sequentially formed to form a source and a drain (not shown) by a self-alignment method or the like, and a gate electrode is provided above the source and the drain.
[0011]
In this structure, since an alignment margin is required for the polycrystalline silicon electrode 22 and the contact hole of the transistor, the width of the polycrystalline silicon electrode (corresponding to the gate length) cannot be shortened to the minimum processing dimension. Further, when the alignment margin becomes extremely small, a problem such as that shown in FIG. 12C occurs, and the yield rapidly decreases. Thus, in the ferroelectric transistor having the MFMIS structure, the gate length cannot be set to the minimum processing dimension of the LSI manufacturing process.
[0012]
In addition, the ferroelectric transistor has a problem that the memory retention time becomes extremely short because the phenomenon of canceling the residual polarization of the ferroelectric occurs when the ferroelectric current leakage and charge injection occur. . Particularly, when charge injection occurs from the semiconductor substrate side, the channel of the FET disappears and information is lost in a short time. The gate insulating film formed on the semiconductor substrate is extremely thin, and charge injection and leakage current are likely to occur on the end surface processed by dry etching or the like.
[0013]
[Problems to be solved by the invention]
As described above, in the ferroelectric transistor having the MFMIS structure, the area of the ferroelectric capacitor needs to be smaller than the area of the gate insulating film. Further, there is a problem that the gate length cannot be reduced to the minimum processing size of the LSI manufacturing process. Further, the ferroelectric transistor has a problem that the memory holding time is shortened by the leakage current of the ferroelectric material and the charge injection into the ferroelectric material. It is considered that this leakage current and charge injection are likely to occur on the damaged gate insulating film and the end face of the ferroelectric.
[0014]
The present invention has been made to solve such an unsolved problem of the conventional technology, and enables the area of the ferroelectric capacitor to be smaller than the area of the gate insulating film, and the gate length to be set to LSI. Ferroelectric transistor-type non-volatile memory with excellent memory retention, which can be reduced to the minimum processing size of the manufacturing process, and prevents leakage current and charge injection at the damaged gate insulating film and ferroelectric end face. An element is provided.
[0015]
[Means and Actions for Solving the Problems]
A ferroelectric transistor type nonvolatile memory element according to the present invention includes an insulating thin film, a first conductive thin film, a ferroelectric thin film, and a second conductive thin film as a gate portion of a field effect transistor formed on a semiconductor substrate. Silicon oxide film covering source and drain regions in a ferroelectric transistor type nonvolatile memory element having a sequentially stacked structure Inner edge of And the insulating thin film Outer edge And the length of the first conductor thin film in the channel length direction is longer than that of the insulating thin film, and the end face of the first conductor thin film is disposed so as not to contact the end face of the insulating thin film. As the silicon oxide film, a thermal oxide film having a thickness larger than that of the insulating thin film is used. The silicon oxide film is formed by thermally oxidizing the semiconductor substrate using the insulating thin film as a mask. The inner edge of the oxide film is formed so as to be defined by the outer edge of the insulating thin film, and the first conductor thin film is formed along the upper surface of the silicon oxide film and the upper surface of the insulating thin film. It is characterized by that.
[0016]
In addition, as a gate part of a field effect transistor formed on a semiconductor substrate, a ferroelectric transistor type nonvolatile memory having a structure in which an insulating thin film, a first conductive thin film, a ferroelectric thin film, and a second conductive thin film are sequentially stacked. In a method for manufacturing an insulating memory element, a single crystal substrate mainly composed of silicon is used as a semiconductor substrate, the insulating thin film is formed and processed, a source region and a drain region are formed using the insulating thin film as a mask, and the insulating A silicon oxide film covering the source and drain regions by thermally oxidizing the surface of the semiconductor substrate using a conductive thin film as a mask Forming a first conductive thin film on the insulating thin film, applying and firing a metal organic ferroelectric thin film on the first conductive thin film, A second forming step of forming a second conductor thin film, and an outer edge of the first conductor thin film formed in the second forming step is located on the silicon oxide film It is characterized by that.
[0017]
Based on FIG. 1 which shows the outline | summary of this invention, the effect | action is demonstrated. A field effect transistor formed on a semiconductor substrate 1 generally has a gate portion having a laminated structure of a gate insulating film 5 and a conductor electrode 6, and a voltage is applied to the conductor electrode 6 so that the source and drain 2 The current flowing between them is controlled to turn on and off.
[0018]
In the gate portion of the present invention, the insulating thin film 5 that prevents oxygen diffusion is used as the gate insulating film, and the first conductive thin film 6, the ferroelectric thin film 7, and the second conductive thin film 8 are sequentially stacked thereon. A ferroelectric capacitor (capacitance) having a structure is arranged, and the field effect transistor can be fixed in an on / off state even when no voltage is applied to the gate portion due to the residual polarization generated by the ferroelectric. Therefore, it can function as a non-volatile memory.
[0019]
Here, the writing, erasing and reading operations of the ferroelectric transistor type nonvolatile memory element of the present invention will be described with reference to FIG.
[0020]
In FIG. 1, an n-channel FET using a 5V drive p-type substrate will be described as an example. First, in the write operation, 5 V is applied to the second conductor thin film 8 side and 0 V is applied to the substrate 1 side to generate downward polarization in the ferroelectric thin film 7. By this operation, even when the second conductor thin film 8 side is set to 0 V, the source 2 and the drain 2 can be turned on. This state is defined as “1”. Next, the erase operation will be described. A voltage of 0 V is applied to the second conductive thin film 8 side and 5 V is applied to the substrate 1 side to cause downward polarization in the ferroelectric thin film 7. By this operation, when the second conductor thin film side is 0 V, the source 2 and the drain 2 can be turned off so that they are not conductive. This state is defined as “0”. Next, the reading operation will be described. The second conductor thin film 8 side is set to 0 V, the substrate 1 side is set to 0 V, the source 2 is set to 0 V, and a 2 V pulse is applied to the drain 2. Whether the memory cell is “1” or “0” is determined based on whether or not the drain voltage immediately decreases. If the drain voltage immediately decreases, this means that the memory cell is in an ON state, and “1” is stored. That would have been done. On the other hand, when the drain voltage does not drop immediately, “0” is stored. Thus, it operates as a nonvolatile memory element corresponding to the polarization direction of the ferroelectric. The voltage setting described above is an example, and the substrate 1 side may be set to a constant potential, and the second conductor thin film 8 side corresponding to the gate may be distributed to plus / minus potential.
[0021]
In the ferroelectric transistor type memory device according to the present invention, the silicon oxide film 4 covering the source and drain portions thicker than the insulating thin film for preventing the diffusion of oxygen is disposed to prevent the above-mentioned diffusion of oxygen. After the end surface of the insulating thin film 5 and the silicon oxide film 4 are joined, and the length of the first conductor thin film 6 in the source and drain directions is longer than that of the insulating thin film 5 that prevents oxygen diffusion, It arrange | positions so that the end surface of the 1st conductor thin film 6 may not contact the end surface of the insulating thin film 5. FIG. By taking such a laminated structure, the gate insulating film 5 and the source / drain self-alignment are separated from each other after the etching process of the gate insulating film (insulating thin film 5) and the etching process of the first conductor thin film 6 are separated. Therefore, the leakage current and the charge injection amount at the end face of the gate portion (end faces of the first conductive thin film 6 and the ferroelectric thin film 7) can be greatly suppressed.
[0022]
Further, by using the silicon oxide film 4 thicker than the insulating thin film 5 that covers the source and drain portions and prevents the diffusion of oxygen, the parasitic capacitance of the gate electrode 6 can be reduced, and the high speed can be achieved. Enable operation.
[0023]
In the case of the present invention, after the insulating thin film is formed and processed, impurities are implanted to form the source and drain portions using the insulating thin film as a mask, and the portion not covered with the insulating thin film is thick. A silicon oxide film 4 is formed. The first conductor thin film 6 is formed on the insulating thin film 5 so that the end surface thereof covers the thick silicon oxide film 4. As a result, a ferroelectric transistor can be fabricated effectively by a self-alignment process with respect to the gate electrode while ensuring a margin for alignment with the insulating thin film (gate insulating film) 5.
[0024]
The insulating thin film 5 in the present invention can be used not only as a mask for forming the silicon oxide film 4 covering the source and drain portions, but also increases the thickness of the gate insulating film when the ferroelectric is heated and crystallized. Can be avoided. Insulating thin film 5 that prevents oxygen diffusion Is ,Preferably SiON film Is .
[0025]
As the first conductor thin film 6 and the second conductor thin film 8 in the present invention, platinum, iridium, iridium oxide, a mixture thereof, or a laminated structure thereof is preferably used. Further, as the ferroelectric thin film 7, ABO _Three Mold, A ₂ B ₂ O ₇ A ferroelectric having a type structure or a ferroelectric having a layered perovskite type structure can be used.
[0026]
Here, A and B represent metal elements. Further, by using the ferroelectric thin film 7 having a relative dielectric constant of 50 or less, a nonvolatile memory element having excellent memory retention characteristics can be obtained. In particular, Sr ₂ Ta ₂ O ₇ Or Sr ₂ (NbTa) ₂ O ₇ Or SrBi ₂ Ta ₂ O ₉ As described above, it is more preferable to use a ferroelectric material having a lower relative dielectric constant.
[0027]
More preferably, the effective area of the ferroelectric capacitor is made smaller than the area of the channel region of the field effect transistor. The reason is that the structure of the gate portion is equivalent to a capacitor in which a ferroelectric thin film 7 and an insulating thin film 5 mainly composed of silicon nitride are connected in series as shown in FIG. When a voltage is applied to each thin film, the voltage is applied in inverse proportion to the capacity. Therefore, the relative dielectric constant of the ferroelectric substance is small, and the smaller the capacity, the higher the applied voltage and the saturation of the polarization, which is advantageous for memory retention. Because it becomes.
[0028]
Further, in the present invention, the silicon oxide film 4 thicker than the insulating thin film 5 that prevents the diffusion of oxygen covering the source and drain portions is disposed, and the insulating thin film 5 that prevents the diffusion of oxygen described above is disposed. Since the arrangement is made so that the end face is joined, the alignment margin between the gate insulating film (insulating thin film 5) and the first conductor thin film 6 can be increased, so that the gate length can be reduced to the minimum processing dimension of lithography. Can be shortened.
[0029]
Further, according to the present invention, after processing the insulating thin film 5 that prevents the diffusion of oxygen, the silicon substrate 4 is thermally oxidized using the insulating thin film 5 as a mask to cover the source and drain portions. Therefore, the device can be manufactured by a very simple method.
[0030]
Here, we will compare with reports that have been studied. In a report made by Fujimori et al. In 1998 (Jpn. Appl. Phys. Vol.37 (1998) p.5207), Po1y-Si / SiO ₂ / Pt / STN / IrO on top of gate electrode with Si / Si laminated structure ₂ / Pt structure (STN is Sr ₂ (TaNb) ₂ O ₇ It has a structure that connects ferroelectric capacitors. In this case, Po1y-Si / SiO ₂ After the structure is formed and processed, the source portion and the drain portion are formed by ion implantation, an interlayer insulating film is formed, and contact holes for bonding to the ferroelectric capacitor are formed. Therefore, it is necessary to allow for an alignment margin for lithography, and POly-Si / SiO of the gate electrode portion. ₂ The structure cannot be reduced to the minimum processing size, and there is a problem that the device area becomes large. On the other hand, in the present invention, this problem can be overcome as described above.
[0031]
The invention disclosed in Japanese Patent Laid-Open No. 5-135570 (inventor, Takashi Nakamura) is configured such that the gate electrode end face of the field effect transistor coincides with the ferroelectric capacitor electrode and the end face of the ferroelectric substance. However, in such a structure, a large amount of leakage current and charge injection occur through the end face of the damaged part, and the memory retention time becomes extremely short. On the other hand, the present invention can solve such problems by reducing leakage current and preventing charge injection.
[0032]
In the invention of Japanese Patent Laid-Open No. 5-121759 (inventor, Katsumi Kajishima), Po1y-Si / SiO ₂ A gate electrode having a structure is embedded in an interlayer insulating film having a low dielectric constant, and an effect similar to that of the present invention can be obtained. However, in order to realize this structure, a sacrificial gate is used, and a source and a drain part are formed. After that, a low dielectric constant interlayer insulating film is formed, planarized using CMP (Chemical Mechanical Polishing), the sacrificial gate is removed, and a new Poly-Si / SiO ₂ An extremely complicated manufacturing process is required in which a laminated structure is formed and planarization and embedding is performed again by CMP. In the present invention, the same effect can be obtained by a shorter manufacturing process as described above.
[0033]
Further, in the invention of Japanese Patent Application Laid-Open No. 11-145411 (inventor, Takashi Nakamura), SiO in the gate portion ₂ On the gate area, the SiO ₂ It is characterized by forming a ferroelectric capacitor area smaller than the area of, but since it is difficult to form the source part and the drain part by the self-alignment process, it is necessary to take a large alignment margin, There is a problem that the entire element becomes large. The publication does not require the use of a material that prevents oxygen diffusion in the gate insulating film, avoiding the problem of increasing the thickness of the gate insulating film during the ferroelectric heating and crystallization process. Can not. In the present invention, the thickness of the gate insulating film can be reduced, and such a problem can be solved.
[0034]
According to the present invention, a ferroelectric transistor with a small area can be manufactured because a margin for alignment can be secured even when the distance between the source and drain, which has been difficult with the conventional method, becomes the minimum processing dimension of the LSI manufacturing process. In addition, it is possible to separate the processing of the gate insulating film and the processing of the ferroelectric thin film, and to separate the end face of the ferroelectric or electrode that has been damaged by etching from the end face of the gate insulating film. A great effect can be obtained in reducing the leakage current in the dielectric thin film and the charge injection into the ferroelectric thin film, and the memory retention time can be greatly extended.
[0035]
Further, after using the silicon substrate, forming the insulating thin film 5 mainly composed of silicon nitride, and forming the silicon oxide film 4 covering the source and drain portions after processing by the thermal oxidation method of the silicon substrate, In addition to the simplification, a dense silicon oxide film 4 can be obtained.
[0036]
As described above, according to the present invention, problems that are difficult to achieve with conventional ferroelectric transistors can be realized by an easy structure and manufacturing method.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0038]
[Embodiment 1]
First, a ferroelectric transistor (sample A) as a nonvolatile memory element as shown in FIG. 3 and a ferroelectric transistor (sample B) as shown in FIG. 4 were produced as a comparative example. Both ferroelectric transistors use a p-type silicon (100) single crystal substrate 10, a field oxide film 12 is formed by thermal oxidation, and an activation region in which a transistor is to be formed is opened by photolithography and etching. .
[0039]
3 and 4, the field effect transistor formed on the semiconductor substrate 10 has a gate portion having a laminated structure of a gate insulating film 14 and a first conductor electrode 15, and the first conductor electrode 15 Is for reducing the capacitance of the ferroelectric thin film to increase the applied voltage to CF to CI shown in FIG. In the gate portions 14 and 15, an insulating thin film that prevents diffusion of oxygen is used as the gate insulating film 14, and a first conductive thin film 15, a ferroelectric thin film 16, and a second conductive thin film 17 are sequentially stacked thereon. The electrode 18 is formed by providing a hole in the interlayer insulating film 19. 3 and 4 conceptually, after forming the gate insulating film 14 of the gate portion, the source / drain regions 11 are formed by ion implantation using the gate insulating film 14 as a mask. Further, after forming the source / drain regions 11, a thermal oxide film 13 is formed by annealing. A field effect transistor that exhibits a non-volatile memory function is formed by the residual polarization generated by the ferroelectric thin film 16 on the gate portion.
[0040]
The operation of the ferroelectric transistor nonvolatile memory element in FIG. 3 is the same as that in FIG. 1, but will be described again. Each operation of writing, erasing and reading of the ferroelectric transistor type nonvolatile memory element of the present invention will be described with reference to FIG.
[0041]
In FIG. 3, as an example of voltage application, a case of an n-channel FET using a 5V drive p-type substrate will be described. First, in the write operation, 5 V is applied to the second conductor thin film 17 side and 0 V is applied to the substrate 10 side to generate downward polarization in the ferroelectric thin film 16. By this operation, even if the second conductor thin film 17 side is set to 0 V, the source 11 and the drain 11 can be turned on. This state is defined as “1”. Next, the erase operation will be described. 0V is applied to the second conductor thin film 17 side and 5V is applied to the substrate 10 side to cause downward polarization in the ferroelectric thin film 16. By this operation, when the second conductor thin film 17 side is at 0 V, the source 11 and the drain 11 can be turned off so as not to conduct. This state is defined as “0”.
[0042]
Next, the reading operation will be described. The second conductor thin film 17 side is set to 0 V, the substrate 10 side is also set to 0 V, the source 11 is set to 0 V, and a pulse of 2 V is applied to the drain 11. Whether the memory cell is “1” or “0” is determined based on whether or not the drain voltage immediately decreases. If the drain voltage immediately decreases, this means that the memory cell is in an ON state, and “1” is stored. That would have been done. On the other hand, when the drain voltage does not drop immediately, “0” is stored. Thus, it operates as a nonvolatile memory element corresponding to the polarization direction of the ferroelectric. Note that the above voltage setting is an example, and the substrate 10 side may be constant, and the second conductor thin film 17 side corresponding to the gate may be distributed to plus / minus potential. Further, if the memory elements are arranged in a matrix and bit lines and word lines are connected to gate electrodes, drain electrodes, etc., a highly integrated nonvolatile semiconductor memory can be completed.
[0043]
(Method for producing sample A)
In the case of sample A shown in FIG. 3, first, a SiON thin film 14 is formed as a gate insulating film. Nitrogen ions are previously implanted into the active region at an energy of about 20 keV, and then annealed at 800 ° C. in an oxygen atmosphere. As a result, an insulating film having a thickness of 5 nm can be formed. Next, after applying a resist, the end face portion of the gate insulating film 14 is processed by photolithography and dry etching. Next, phosphorus ions are ion-implanted into the sample to form source and drain regions 11. Further, after the resist is removed, the thermal oxide film 13 of silicon can be formed so as to cover the source and drain regions 11 by annealing at about 800 ° C. in an oxygen atmosphere. At this time, the thickness of the thermal oxide film 13 was about 20 nm. Since the SiON film prevents the permeation of oxygen, an oxide film is hardly formed in the gate region. By annealing in an oxygen atmosphere at 800 ° C., activation annealing of the source and drain regions can also be performed. As a result, the structure shown in FIG. 5 is obtained.
[0044]
Next, a laminated film 15 of titanium and platinum is formed as a first conductor thin film on the gate insulating film 14 by a sputtering method. The total thickness of platinum and titanium is about 200 nm. Next, as a ferroelectric thin film, Sr (NbTa) ₂ O ₇ The film 16 is formed by a method of applying and baking a metal organic material. The film thickness is about 300 nm. Next, iridium was formed by sputtering as the second conductor thin film. The film thickness is about 150 nm. This was sequentially processed by photolithography and dry etching in the order of the second conductor thin film, the ferroelectric thin film, and the first conductor thin film. Further, a silicon oxide film is formed as an interlayer insulating film 19 by plasma CVD, contact holes are formed on the second conductor thin film, and the source and drain layers, and an aluminum electrode 18 is formed and processed to complete. FIG. 7 shows a top view of the completed ferroelectric transistor. In FIG. 7, a ferroelectric transistor (sample A) includes a gate insulating film 14, a wide conductive laminated film 15 of a first conductive thin film, a ferroelectric 16, and a gate electrode of a second conductive thin film. The gate portion is formed from 17, and the source / drain layer 11, the thermal oxide film 13, and the source / drain electrode 20 are formed. Reducing the ferroelectric capacitance so that the effective area of the capacitance of the ferroelectric 16 formed between the conductor laminated film 15 and the gate electrode 17 is about 1/5 of the area of the gate insulating film 14, The length in the width direction of the gate insulating film 14 of the ferroelectric film was also set.
[0045]
(Method for producing sample B)
Next, in the case of the sample B of the comparative example, as shown in FIG. 4, the SiON thin film 14 is first prepared as a gate insulating film. Nitrogen ions are previously implanted into the active region at an energy of about 20 keV, and then annealed at 800 ° C. in an oxygen atmosphere. Thereby, the insulating film 14 having a thickness of 5 nm can be formed. Next, a thin film 15 in which titanium and platinum are sequentially laminated is formed as a first conductor thin film. Next, as a ferroelectric thin film, Sr (NbTa) ₂ O ₇ The film 16 is formed by a method of applying and baking a metal organic material. The film thickness is about 300 nm. Next, iridium was formed as the second conductor thin film 17 by sputtering. The film thickness is about 150 nm. Further, after the resist is applied, the gate laminated structure is collectively processed by photolithography and dry etching.
[0046]
Next, phosphorus ions are ion-implanted into the sample to form source and drain regions 11. Further, the source and drain regions 11 are activated by annealing at about 800 ° C. in a nitrogen atmosphere. As a result, the structure shown in FIG. 6 is obtained. In FIG. 6, a gate insulating film 14, a metal laminated thin film 15, a ferroelectric thin film 16, and a second conductor thin film 17 are formed on a semiconductor substrate 10.
[0047]
Next, a silicon oxide film is formed as an interlayer insulating film 19 by plasma CVD, a contact hole is formed, and an aluminum electrode 18 is formed and processed to complete.
[0048]
For Samples A and B, a voltage was applied between the second conductor electrode 17 and the silicon single crystal substrate 10 to measure voltage-current characteristics. Thereby, the leakage current of the gate portion can be measured. The result is shown in FIG. Sample A has a leakage current of 10 even when 3V is applied. ^-9 Ampere / cm ² Sample B is 10 ^-6 Ampere / cm ² It is obvious that sample A has a smaller leakage current. This is because the sample B collectively processes the gate insulating film SiON film 14 and the first conductor thin film, and the end faces coincide with each other. It is considered a thing. On the other hand, in the case of sample A, the damaged end faces do not match, so the leak path is blocked and the leak characteristics are considered to be good.
[0049]
(Evaluation of sample A and sample B)
Next, memory retention characteristics are evaluated. For samples A and B, information is written by applying a voltage between the second conductor electrode 17 and the silicon single crystal substrate 10 to generate ferroelectric polarization. Thereafter, the source portion was grounded, a voltage of 1 V was applied to the drain portion, and after applying the write voltage, the current value flowing through the drain after being held for a certain period of time was observed. The result is shown in FIG. In the figure, the measurement results of samples A and B when the applied voltage Vg is changed from 5 V to 0 V and from -5 V to 0 V are shown. Time 10 for both samples A and B ⁶ Measured with elapsed time of sec. As is apparent from this result, it can be seen that the sample A has a longer memory retention time than the sample B. This is considered to be due to the fact that the amount of charge flowing into the ferroelectric material can be largely suppressed.
[0050]
[Embodiment 2]
A ferroelectric transistor type nonvolatile memory element according to Embodiment 2 of the present invention will be described.
[0051]
A ferroelectric transistor as shown in FIG. 10 was prototyped. In FIG. 10, first, a p-type silicon (100) single crystal substrate 10 was used, a field oxide film 12 was formed by thermal oxidation, and an activation region where a transistor was to be formed was opened by photolithography and etching.
[0052]
Next, after forming and processing the SiON thin film 14 as the gate insulating film and the polycrystalline silicon film 26 as the gate electrode, ion implantation is performed using the gate electrode portion as a mask, and the source and drain regions 11 are produced. Next, after removing the resist, the source and drain regions 11 were activated by annealing at about 800 ° C. in a nitrogen atmosphere. Further, a silicon oxide film 13 was formed as an interlayer insulating film. As a result, a structure as shown in FIG. 11 is obtained.
[0053]
Next, a contact hole was opened in the upper part of the gate electrode portion in the silicon oxide film 13, and a titanium and platinum film was formed as the first conductor film 15 by a sputtering method. Further, as the ferroelectric thin film 16 (Sr (NbTa) ₂ O ₇ Film) is formed by a method of applying and baking a metal organic material. The film thickness is about 300 nm. Next, iridium oxide was formed as the second conductor thin film 17 by sputtering. The film thickness is about 150 nm. The second conductor thin film 17, the ferroelectric thin film 16, and the first conductor film 26 were sequentially processed by photolithography and dry etching. Further, a silicon oxide film is formed as an interlayer insulating film 19 by plasma CVD, and then contact holes are formed, and aluminum electrodes 18 are formed and processed on the source / drain layer 11 and the second conductor thin film 17. Completion. In the case of this sample, good characteristics can be obtained as in the case of Sample A of Embodiment 1. However, when making a contact hole, it is necessary to allow for an alignment margin with the gate electrode portion. As a result, the gate length became as long as 0.75 μm. As a result, it has been clarified that in the structure of this embodiment, the element area is considerably larger than the element structure of the present invention.
[0054]
In the above embodiment, one element of the ferroelectric transistor type nonvolatile memory element has been described. However, a large number of elements formed in this way are formed in a matrix, and in principle, at a density equal to or higher than that of a DRAM. The storage device can be integrated. Further, this ferroelectric transistor type nonvolatile memory device can be provided in an LSI for IC cards, mobile phones, etc., and provided as a highly reliable and stable memory element without a drive mechanism.
[0055]
In addition, by configuring each memory cell using a gate electrode as a bit line, a source as a plate line, and a drain as a word line, it is possible to control the on / off of the memory function with a small drive voltage, and a highly reliable nonvolatile memory element Can be operated reliably.
[0056]
【The invention's effect】
According to the present invention ,strength Leakage current and charge injection flowing through the damaged layer on the dielectric end face can be drastically reduced, and as a result, memory retention time as a memory device can be extended.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of an element structure in the present invention.
FIG. 2 is a diagram showing an equivalent circuit of a ferroelectric transistor according to the present invention.
FIG. 3 is a diagram showing a structure of a sample A in Embodiment 1 according to the present invention.
FIG. 4 is a diagram showing a structure of a sample B in Embodiment 1 according to the present invention.
5 is a view showing a structure after an oxide film is formed so as to cover a source / drain region 11 in a manufacturing process of a sample A according to Embodiment 1 of the present invention. FIG.
6 is a view showing a structure after activation of a source / drain region 11 in a manufacturing process of a sample B according to Embodiment 1 of the present invention. FIG.
7 is a top view of sample A in Embodiment 1 according to the present invention. FIG.
FIG. 8 is a diagram showing measurement results of current-voltage characteristics of a sample in Embodiment 1 according to the present invention.
FIG. 9 is a diagram showing measurement results of memory retention characteristics of a prototype sample according to Embodiment 1 of the present invention.
FIG. 10 is a diagram showing a structure of a sample in Embodiment 2 according to the present invention.
FIG. 11 is a diagram showing a structure after an interlayer insulating film is formed in the manufacturing process of a sample in Embodiment 2 according to the present invention.
FIG. 12 is a diagram showing a ferroelectric transistor having a MFMIS structure according to the prior art.
[Explanation of symbols]
1 Semiconductor substrate
2 Source and drain regions
3 Field oxide film
4 Silicon oxide film covering source and drain
5 Insulating thin film that prevents oxygen diffusion
6 First conductor thin film
7 Ferroelectric thin film
8 Second conductor thin film
9 Aluminum wiring
10 p-type silicon single crystal substrate
11 Source and drain regions
12 Field oxide film
13 Thermal oxide film covering source and drain
14 SiON thin film (insulating thin film)
15 Platinum / titanium thin film (first conductor thin film)
16 Sr (NbTa) ₂ O ₇ Thin film (ferroelectric thin film)
17 Iridium thin film (second conductor thin film)
18 Aluminum wiring
19 Plasma CVD silicon oxide film
20 Silicon polycrystalline substrate
21 Thermally oxidized silicon oxide film
22 Polycrystalline silicon electrode
23 Iridium and iridium oxide laminated electrodes
24 Ferroelectric thin film
25 Iridium and iridium oxide laminated electrodes
26 Single crystal silicon

Claims (10)

A ferroelectric transistor type nonvolatile memory having a structure in which an insulating thin film, a first conductive thin film, a ferroelectric thin film, and a second conductive thin film are sequentially stacked as a gate portion of a field effect transistor formed on a semiconductor substrate. In the element
The inner edge of the silicon oxide film covering the source region and the drain region is joined to the outer edge of the insulating thin film, and the length in the channel length direction of the first conductive thin film is longer than that of the insulating thin film, Arranged so that the end face of the body thin film does not contact the end face of the insulating thin film ,
As the silicon oxide film, a thermal oxide film that is thicker than the insulating thin film is used,
The silicon oxide film is formed such that an inner edge of the silicon oxide film is defined by an outer edge of the insulating thin film by thermally oxidizing the semiconductor substrate using the insulating thin film as a mask.
The ferroelectric transistor type nonvolatile memory element, wherein the first conductive thin film is formed along the upper surface of the silicon oxide film and the upper surface of the insulating thin film .   2. The ferroelectric transistor type nonvolatile memory element according to claim 1, wherein a single crystal silicon substrate is used as the semiconductor substrate. The insulating thin film, a ferroelectric transistor type nonvolatile memory element according to claim 1 or 2, characterized in that the SiON film. The ferroelectric capacitor comprising the first conductive thin film, the ferroelectric thin film, and the second conductive thin film has a structure in which an effective area is smaller than an area of a channel region of the field effect transistor. 4. The ferroelectric transistor type nonvolatile memory element according to any one of items 1 to 3 . As the ferroelectric material, a ferroelectric material having an ABO ₃ type structure (A and B are metal elements, the same shall apply hereinafter), a ferroelectric material having an A ₂ B ₂ O ₇ type structure, or a strong material having a layered perovskite structure. ferroelectric transistor type nonvolatile memory element according to claim 1, any one of 4, characterized by using a dielectric material. As the ferroelectric material, a material mainly composed of Sr ₂ Nb ₂ O ₇ , Sr ₂ Ta ₂ O ₇ , Sr ₂ (NbTa) ₂ O ₇ , or SrBi ₂ Ta ₂ O ₉ is used. The ferroelectric transistor type nonvolatile memory element according to any one of claims 1 to 4 . Wherein the strong as the dielectric material, a ferroelectric transistor type nonvolatile memory element according to any one of claims 1 to 6, the dielectric constant is characterized by the use of 50 or less of the material. Platinum as the conductive thin film, iridium, any one of claims 1 to 7, characterized in that the use of thin film or structure obtained by stacking two or more of these mainly iridium oxide, one of the conductive polycrystalline silicon 2. The ferroelectric transistor type nonvolatile memory element according to item 1. A ferroelectric transistor type nonvolatile memory having a structure in which an insulating thin film, a first conductive thin film, a ferroelectric thin film, and a second conductive thin film are sequentially stacked as a gate portion of a field effect transistor formed on a semiconductor substrate. In the manufacturing method of the element,
Using a single crystal substrate mainly made of silicon as a semiconductor substrate, forming and processing the insulating thin film, forming a source region and a drain region using the insulating thin film as a mask, and using the insulating thin film as a mask, the semiconductor substrate A first forming step of forming a silicon oxide film covering the source region and the drain region by thermally oxidizing the surface ;
After the first forming step, a first conductor thin film is formed on the insulating thin film, a metal organic ferroelectric thin film is applied and baked on the first conductor thin film, and then a second conductor thin film is formed. A second forming step of forming
Have
The manufacturing method of a ferroelectric transistor type nonvolatile memory element, wherein an outer edge of the first conductive thin film formed in the second forming step is located on the silicon oxide film . After the second forming step, an interlayer insulating film is formed, and a hole is formed in the interlayer insulating film corresponding to the second conductor thin film, the source region, and the drain region, and an electrode is formed in the hole. The method of manufacturing a ferroelectric transistor type nonvolatile memory element according to claim 9 , further comprising a step of :

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