JPS5925262A - Mis type semiconductor device - Google Patents

Abstract

PURPOSE:To improve the integration degree by a method wherein a capacitor forming electrode and a drain wiring conductive film are extended in parallel each other, and a gate wiring conductive film and the capacitor forming electrode are extended to the direction of mutual intersection. CONSTITUTION:An information accumulation capacitor is formed of a semiconductor region continuous to the source region 6 of a MIS transistor and the cpapcitor forming electrode formed via an insulation film 7. Then, the capacitor forming electrode 8 and the drain wiring conductive film 10 are formed by extending them in parallel each other on the semiconductor region. Further, the gate wiring conductive film 11 is formed by extending it to the direction of intersection with the capacitor forming electrode 8.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an MIS type semiconductor device, and is directed to a MIS type semiconductor device for a main-CIMIS-transistor memory configuration.

The simplest type of dynamic memory cell is a one-transistor memory cell. By the way, in such a type of memory hill, 841S (ti'r W1 port 11 connected in series with it through a transistor)
The problem is that the potential of the information read from the information storage capacitor is written, and the read data line becomes floating.

This means that it is necessary to increase the capacity for information storage to some extent.

When configuring a memory in an aluminum gate type MIS-LSI, one of the source and drain diffusion regions is formed wide, and an electrode is formed through an insulating film on one of the regions. ηW1゛Publication US P3
:387286 and use the capacitance +i1 between the semiconductor region and the electrode as the capacitor for information storage. However, originally an aluminum gate type MIS semiconductor shield was used between the gate and the source/drain. 1. There is a problem that ' becomes large.

By the way, when making a one-transistor memory using a silicon gate type MIS semiconductor device using a self-alignment method, the insulating film constituting the dielectric is formed at the same time as the gate insulating film, so the insulating film is thick and one memory cell There is a limit to the area occupied per hit. Furthermore, due to diffusion, the window openings W do not constitute each prefecture, resulting in waste.

The present invention was made to solve such problems,
The purpose is to reduce the area occupied by the IMQs memory and improve the degree of integration.

According to one embodiment of the present invention, a silicon gate electrode formed through an insulating film in a part of a region where an active region of a semiconductor is to be formed is used as a mask and (7-(source) by doping the semiconductor surface with impurities. After forming the drain region, the semiconductor surface is subjected to a thin oxidation treatment over the entire surface, and the surface of the silicon gate electrode is protected with an oxide film formed by this treatment, and then, a thin oxidation treatment is applied to the entire surface of the semiconductor. By forming an electrode through at least the oxide film, a capacitor having at least this oxide film as a dielectric is formed.

According to another embodiment of the present invention, an insulating film is interposed in a part of the area where the active area of the semiconductor is to be formed! After removing the mask from the silicon oxide electrode formed in step 7 and doping the body surface with impurities, source and drain regions were formed, and then the semiconductor surface was subjected to thinning () tanning treatment. ,
The oxide film formed by this treatment protects the surface of the silicon electrode 1, and then the jir! of either the source or drain. A multi-lrI layer film consisting of the oxide film and another dielectric material film is formed on the surface of the film, and electrodes are formed on the multilayer film. The multilayer film described in I is used as a dielectric.

The present invention will be explained below with reference to Examples 2).

FIG. 1 is a cross-sectional view showing, in order of steps, a method of manufacturing an MIS type semiconductor device according to an embodiment of the present invention.

(a) The surface of the semiconductor substrate 10 is selectively oxidized to form a 5iQ2 film 2 for field passivation, and then the entire surface of the semiconductor substrate 10 is subjected to p4. j54i'(, (l
Forming the SiQ2 film 3 for forming the 1-C Gaechie marginal film a).

fbl Next, a silicon gate electrode (former 4) is formed on the semiconductor substrate 1. , t can be formed by t-coninoting.

Using this gate electrode 4 as a mask, the film 3 is etched to form a gate insulating film 3a, and an unnecessary substance diffusion process is performed in this state.
, Dre fn 5. A semiconductor region of the source 6 is formed. .

(c) Next, the surface of the semiconductor body is subjected to thermal oxidation treatment to form a thin insulating film (thickness: 750 Å, for example) 7.

This thermal oxidation treatment converts silicon debris that may be present between the gate electrode 4, drain 5, and source 6 into an insulator, or oxidizes the corners and ends of the surface of the silicon micropole due to electric field concentration. Tar, the surface condition of the pole is smoothed and the electric field concentration can be directly controlled.

However, in the present invention, the thermal oxidation treatment
This not only protects the poles, but also forms an information storage container using the insulating film 7 formed by this process as a dielectric, as will be described later.

(Mountain) A polycrystalline silicon layer is grown in a vapor phase on a semiconductor substrate. Then, it is etched so that it remains in the source region 6'2, and the KIl!!
This is one electrode 3 facing the source region 6.

From -5-1, in forming this electrode 8, 1,
This creates an information storage capacity on the source side of the N4I SFE i'' element.

(e) Next, tTe was placed on the semiconductor substrate for multilayer wiring.
The edge film 9 is grown in a vapor phase, and then a desired portion of the insulation II>19 is etched to form a contact hole.

if) After that, a B wiring film 10 is formed. Fu, 161
Qa is a contact portion of the Aβ wiring film 10 with the drain region 5.

Figure 2 shows the state of the semiconductor element γX1 (f) at each step: td.
-■ is a plan view showing the state of step ta in the second embodiment, (b) is the state of step (bl), (cl is the state of step (1), (di is process (f)
Each figure in Figure J-J-0 corresponds to a sectional view taken along line A-A in each figure in Figure 2.

FIG. 3 [, 11, Fbl is a layout diagram showing a part of the memory array (for four memory cells) in various embodiments, and is used to clearly understand the mutual wiring relationship. FIG. 5(C) is a wiring diagram corresponding to them.

The embodiment shown in FIG.
In contrast, in the embodiment shown in FIG. 3(l), each gate is connected to A through a contact hole 4a.
It is connected to the β wiring 11 (Z).

In any case, in the present invention, the dielectric material constituting the information storage valley 1-B element is formed at the same time as the insulating film for protecting the silicon gate surface, so the silicon chip 1-M I S -I C can be formed without increasing the number of steps. A J-needle transistor memory cell information-eight stacking gate element can be formed in the following manner.

Also, all of the surface area of one source (or drain) region is
If the electrodes are used as the electrodes constituting the storage capacitor, a larger capacity can be obtained with the same area than the conventional one-transistor memory cell using silicon chips.

In addition, the capacity for information storage is 1M, and the element capacity is 11M, 5 pieces, 51
02 film and other insulating films, such as Si, which has a high dielectric constant.
,N.

(N4 has a dielectric constant several times larger than that of SiQ). Even if the film piece of the double layer itself is made slightly thicker than the conventional case of only 5iQ2, the capacitance of the device can be increased.

The present invention is an IIA (IMIS) Langisque memory cell type IIA.
It can be widely applied to the manufacturing method of MIS type semiconductor devices for M. In addition, in order to lower the space between the polysilicon 4 and the polysilicon 8, an insulating film (CVI) is formed using a deposition technique such as CVD after the deposition of the IJ S i 4, and etching of the IJ S i 4 is performed. Sometimes CV
After etching the D film, use the same mask to etch Po IJ S i 4
It is also possible to perform etching.

[Brief explanation of the drawing]

Figures 1 (al to f) are cross-sectional views of an embodiment of the present invention, not shown in the order of steps. (aj is the first
(1)) is the plan view of Fig. 1 (1)), (cl is the plan view of Fig. 1 (d), (d) is the plan view of Fig. 1 (r)
) is a plan view of No. 31XI (al, (b) is a plan view showing a part of the memory array (4 memory cells) in various embodiments, respectively. 3 shows the electrode area constituting the valley M-element, and the dotted area shown by parallel diagonal lines on the upper right shows the contact hole fit for interconnection between the upper and F elements.
) is a wiring diagram showing a part of the memory array common to each. ]...Semiconductor No. 1 (-plate, 2...5iQ2 film, 3.
- SiQ for gate insulating film formation, film, 3a... gate insulating film, 4... gate electrode, 5... drain, 6...
・Source, 7...Thin insulating film (dielectric material and silicon gate surface protection film for the information storage device), 8... Opposed to the source region, forming one electrode of the information storage device 9... Insulating film for mutual insulation between two lower wirings, 10... Aβ film for drain wiring, 11... A8 film for gate wiring. Figure 1 Figure 1 Figure 2 Figure 2 rα) 2nd Figure 2 Figure 3

Claims (1)

[Claims] An 8.11 S l transistor whose drain region is bonded to a conductive film for drain wiring and whose gate type rod is bonded to the conductive film for gate wiring and is formed in a semiconductor active region, and the above-mentioned MIS) A MIS semiconductor device having an information storage capacitor coupled to a source region 1 of a transistor (MIS), wherein the information storage capacitor has a semiconductor region connected to the source region of the transistor The capacitance forming rod and the drain wiring conductive film extend parallel to each other on the semiconductor active region, and the capacitor forming rod and the drain wiring conductive film extend parallel to each other on the semiconductor active region. -1. Wiring Precautions 7] T, the film has the above-mentioned capacity - intersects with the forming electrode and the above-mentioned conductive film for drain wiring - extends in the direction of the line - [M I S type conductor with Puero and C1. Device.