JPS6018146B2 - Manufacturing method of MIS type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MIS type semiconductor device, and is mainly directed to a MIS type semiconductor device for an IMIS transistor memory configuration.

The simplest type of dynamic memory cell is a one-transistor memory cell.

By the way, in this type of memory cell, MIS
Information is stored in an information storage capacitor connected in series through a transistor, but the problem is that the potential of the information read from the information storage capacitor is written and divided into the floating capacitance of the read data line. In order to be
There is a need to increase the capacity for information storage to some extent. When configuring a memory in an aluminum gate type MIS-LSI, one of the source and drain diffusion regions is formed wide, and an electrode is formed through an insulating film on one of the regions. It is possible to fabricate an element having the structure described in , and use the capacitance between the semiconductor region and the electrode as an information storage capacitor.

However, in the original aluminum gate type MIS semiconductor device, there is a problem in that the parasitic capacitance between the gate, source, and drain becomes large. By the way, in a silicon gate type skin S semiconductor device using a self-alignment method, 1
When manufacturing a transistor memory, the insulating film constituting the dielectric is formed at the same time as the gate insulating film, so the insulating film is thick and there is a limit to the reduction in area occupied by one memory cell.

Further, due to diffusion, the window opening W does not constitute a capacity, resulting in waste. The present invention has been made to solve these problems, and its purpose is to reduce the area occupied by IMOS memory cells and improve the degree of integration.

The basic structure of the present invention to achieve the above object is to dope impurities into the semiconductor surface using a silicon gate electrode formed through an insulating film in a part of the region where the active region of the semiconductor is to be formed as a mask. After forming the source and drain regions, the entire semiconductor surface is thinly oxidized,
The surface of the silicon gate electrode is protected by the oxide layer formed by the treatment, and an electrode is then formed on either the source or drain region through at least the oxide film, thereby removing at least this oxide film. It is characterized by forming a capacitor with a dielectric material. Another configuration of the present invention is that the source and drain regions are formed by doping the semiconductor surface with impurities using a silicon gate electrode formed through an insulating film in a part of the region where the active region of the semiconductor is to be formed. After that, the semiconductor surface is subjected to a thin oxidation treatment, and the surface of the silicon electrode is protected by the oxide film formed by the treatment, and then the oxide film and another dielectric material film are formed on either the source or drain region. The invention is characterized in that a multilayer film consisting of the following is formed, and an electrode is formed on the multilayer film, thereby making the multilayer film a dielectric.

The present invention will be explained below with reference to Examples.

FIG. 1 is a cross-sectional view showing the manufacturing method of a MIS type semiconductor device according to an embodiment of the present invention in the order of steps.

'a' The surface of the semiconductor substrate 1 is selectively oxidized to form a field passivation Si02 film 2, and then the entire surface of the semiconductor substrate 1 is heated and oxidized to form a gate insulating film forming Si02 film 3. 'b' Next, a silicon gate electrode 4 is formed on the semiconductor substrate 1. This can be formed by forming a polycrystalline silicon layer over the entire surface of the substrate 1 by vapor phase growth, and then photoetching the polycrystalline silicon layer. Then, using this gate electrode 4 as a mask, the Si0
2 film 3 is etched to form a gate insulating film 3a, and an impurity diffusion process is performed in this state to form a drain 5 and a source 6.
forming a semiconductor region.

'c} Next, the semiconductor surface is subjected to thermal oxidation treatment to form a thin insulating film (film thickness, for example, 750 Å) 7.

This thermal oxidation treatment converts silicon debris that may be present between the gate electrode 4, drain 5, and source 6 into an insulator, or oxidizes the corners and edges of the silicon electrode surface where electric fields tend to concentrate. It is possible to make the surface of the electrode smooth and prevent electric field concentration. but,
The present invention not only protects the gate electrode by this thermal oxidation treatment, but also forms an information storage capacitor using the insulating film 7 formed by this treatment as a dielectric, as will be described later.

'd' Vapor phase growth of a polycrystalline silicon layer on the semiconductor substrate.

Then, it is photoetched so that it remains on the source region 6 and forms one electrode 8 facing the source region 6 with the insulating film 7 interposed therebetween. That is, by forming this electrode 8, an information storage capacity is created on the source side of the skin SFET element.

[c' Next, an insulating film 9 is placed on the semiconductor substrate for multilayer wiring.
is grown in a vapor phase, and then a desired portion of this insulating film 9 is photo-etched to form a contact hole. m After that, an A-line wiring film 10 is formed.

Note that 10a is a contact portion with the drain region 5 of the A wiring film 10. FIG. 2 is a plan view showing the state of the semiconductor element part in each step, where 'a} represents the state of step [a} in the above embodiment, and 'a} represents the state of step [b},
c} represents the state of the process 'd', and {d' represents the state of the process.

Each figure in FIG. 1 corresponds to a sectional view taken along the line AA in each figure in FIG. Figures 3a and 3b are layout diagrams showing a part of the memory array (for four memory cells) in various embodiments, and are intended to clearly understand the mutual wiring relationship. are the corresponding wiring diagrams.

In the embodiment shown in FIG. 3a, each drain region is connected to the A wiring 10 via a contact hole portion 10a, whereas in the embodiment shown in FIG. The gate is connected to the A wiring 11 via the contact hole 4a.

In any case, in the present invention, the dielectric material constituting the information storage capacitor element is formed simultaneously with the silicon gate surface protection insulating film, so there is no need to increase the number of steps, and information for one-transistor memory cell using the silicon gate surface S-IC is required. A storage capacitor element can be formed. In addition, the entire area of the source (or drain) region can be used as an electrode constituting the information storage capacitor, resulting in a larger capacity even with the same area than in the case of a one-transistor memory cell using a conventional silicon gate S-IC. is obtained.

Note that the dielectric of the capacitive element for information storage is composed of a double layer of an Si02 film and another insulating film, particularly a Si3N4 (nitride) film with a high dielectric constant, to strengthen the protection of the silicon gate while reducing the yield of the dielectric. The overall function factor can be made larger than conventional ones (Si3N4 has a dielectric constant several times larger than Si02, so even if the double layer itself is slightly thicker than the conventional case of only Si02, the capacitance of the capacitive element can be increased). can.

The present invention can be widely applied to a method for manufacturing a MIS type semiconductor device for an IMIS transistor memory cell type RAM.

In addition, in order to reduce the capacitance between polysilicon 4 and polysilicon 8, CVD using a deposition technique such as CVD is used.
The insulating film is formed after poly-Si4 is deposited.
It is also possible to perform selective etching of the CVD film during the etching step 4 and then perform etching of poly-Si4 under the same mask.

[Brief explanation of drawings]

FIGS. 1a to 1f are cross-sectional views showing an embodiment of the present invention in the order of steps. Figures 2 a to d are plan views of each step in the above embodiment; specifically, a is a plan view of Figure 1 a, b is a plan view of Figure 1 b, and c is a plan view of Figure 1 d. Plan view d is a plan view of FIG. 1 f. Figures 3a and 3b are plan views showing a part of the memory array (for four memory cells) in various embodiments, respectively.
Particularly, the portion corresponding to the parallel diagonal line on the lower right side indicates an electrode region constituting the capacitor element, and the portion corresponding to the parallel diagonal line on the upper right side indicates a contact hole portion for interconnection between the upper and lower sides. FIG. 3c is a wiring diagram showing a part of the memory array common to each.
DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Sj02 waist, 3... Si02 film for gate insulating film formation, 3a... Gate insulating film, 4... Gate electrode, 5... Drain, 6... Source, 7...
・Thin insulating film (dielectric and silicon gate surface protection film of the information storage capacitor, 8... Wiring film that faces the source region and constitutes one electrode of the information storage capacitor, 9...
・Insulating film for mutual insulation between upper and lower wiring, 10...A film for drain wiring, 11...A film for gate wiring. Girder L figure Girder Otsu figure 3 figure

Claims (1)

[Scope of Claims] 1. After forming source and drain regions by doping the semiconductor surface with impurities using a silicon gate electrode formed through an insulating film in a part of the region where the active region of the semiconductor is to be formed as a mask. , the entire surface of the semiconductor is subjected to a thin oxidation treatment to form an oxide film that protects the surface of the silicon gate electrode and extends over the source and drain regions; A method for manufacturing an MIS type semiconductor device, characterized in that a capacitor electrode is formed thereon through at least the oxide film, and a capacitor using at least the oxide film as a dielectric is formed. 2. A method for manufacturing an MIS type semiconductor device according to claim 1, characterized in that polycrystalline silicon is used as an electrode formed on either the source or drain region via at least an oxide film. 3 After forming source and drain regions by doping the semiconductor surface with impurities using a silicon gate electrode formed via an insulating film as a mask in a part of the region where the active region of the semiconductor is to be formed, the semiconductor surface is thinly oxidized. process,
The oxide film formed by this treatment protects the surface of the silicon electrode, and then a multilayer film consisting of the oxide film and another dielectric material film is formed on either the source or drain region. and forming an electrode on the multilayer film to form a capacitor using the multilayer film as a dielectric. 4. MIS according to claim 3, characterized in that a nitride film is used as the other dielectric material film.
Method for manufacturing type semiconductor devices.