JPS60200565A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the integration of a memory cell by forming a groove type capacitor in a groove formed with an insulating film on the inner surface, and forming the entire groove as a groove type isolation for separating between elements, thereby preventing a leakage current between adjacent capacitors to prevent a signal charge from erasing. CONSTITUTION:Capacitors 11 formed in groove shape are in an insulated state from a semiconductor substrate 12 via an insulating film 14 formed on the inner surface of a groove, and the film 14 is also formed between adjacent capacitors 11 and 11. Thus, a punch-through between the capacitors 11 and 11 can be effectively prevented, and no signal charge is erased. Accordingly, an interval between the capacitors 11 and 11 can be reduced to decrease the occupying area of the capacitors. On the other hand, grooves 13 operate as groove type isolation via the film 14 of the inner surface and also operate as an insulator separation between MOSFETs 10. Accordingly, as the occupying area of the capacitors is reduced, the entire memory cell M-CEL can be highly integrated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device suitable for a semiconductor memory device in which a trench type capacitor is configured as an information storage section.

[Background technology]

2. Description of the Related Art In recent years, with the demand for increased storage capacity of semiconductor memory devices, miniaturization of memory elements (memory cells) has been promoted, and higher integration of elements has been achieved. For example, storage devices that include a capacitor as an information storage unit and an MO8 field effect transistor (MOSFET) are no exception, and attempts have been made to miniaturize capacitors, which occupy a particularly large area. ing. Special Public Service 1977-127
The semiconductor memory device described in No. 39 is in response to such requirements, and the capacitor is formed in a groove shape to reduce the area occupied by the capacitor.

That is, in this device, as shown in FIG. 1, a groove (pore) 2 is formed from the main surface of a semiconductor substrate 1 toward the inside of the substrate, and an insulating film 3 is laminated and formed on the surface of this groove 20. A capacitor 5 is constituted by the capacitive electrode 4. In this example, the MO8FET6 adjacent to the capacitor 5 is used to create a one-element D-RAM (dynamink RA)'v, I).
The capacitor 5 is used as an information storage section. Therefore, according to this storage device, if the capacity is the same as that of a conventional planar capacitor, its occupied area can be reduced to at least 1,150 pixels compared to the conventional planar capacitor, and as a result, the degree of integration can be increased by more than 50 times.

However, when the present inventor conducted various studies on the D-RAM, it was found that adjacent memory cells %j −
If an attempt is made to further increase the degree of integration by reducing the distance between the CE Ls, the depletion layers of the capacitors 5, 5 will be brought closer together, and a so-called punch-through phenomenon will occur between the two capacitors, causing a leakage current X. It has been found that a problem arises in that the signal charge (information) accumulated in the capacitor 5.5 is lost.

In order to prevent this, it is necessary to increase the distance between the two capacitors 5, 5, which limits the improvement in the degree of integration and makes the trench-shaped structure less meaningful. [Object of the Invention] The present invention The purpose of this is to prevent leakage current between adjacent capacitors and prevent loss of signal charge, thereby reducing the spacing between memory cells with trench capacitors, thereby achieving an increase in the density of memory cells. It is an object of the present invention to provide a semiconductor device suitable for a storage device that can be used as a storage device.

The above and other objects and novel features of the present invention include:
This will become clear from Description 2 of Example A and the attached drawings.

[G of invention! , essential]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a trench capacitor is constructed by forming a pair of conductive films with an insulating film sandwiched in a trench that is insulated from the semiconductor substrate. Dissipation of charge can be prevented, and by configuring this groove as an isolation region between elements, it is possible to arrange each capacitor in close proximity.
This achieves an improvement in the degree of device integration.

〔Example〕

2 and 3 show an embodiment in which the present invention is applied to a one-element type D-RAM. FIG. 2 is a plan layout diagram, FIG. 3 (5), and CB+ are AA and BB in FIG. FIG. In these figures, 10 is a MOSFES, 11 is a capacitor, and the planar area shown by the chain line C in the figures each includes one MO8FFJTIO and the capacitor 11, and constitutes one unit of memory cell M-CEL.

That is, a planar U-shaped groove 13 is formed on the main surface of the semiconductor substrate 12.
The grooves 13 are arranged alternately and facing each other, and each groove 13 is kept insulated from each other by an insulating film (silicon oxide film) 14 formed on its inner surface or boundary surface. In this groove 13, a polysilicon film 15 as a first conductive film is provided.
A silicon oxide film 16 is formed as an insulating film (dielectric film) on the top surface of the silicon oxide film 16, and polysilicon 17 as a second conductive film (conductor) is filled in the groove 13 on top of the silicon oxide film 16. This constitutes a so-called groove-type capacitor 11.

On the other hand, a gate insulating film 19 made of a silicon oxide film is formed on a rectangular region 18 surrounded by an insulating film 14 provided on the inner surface of the groove 13, and a word line extending in the vertical direction in the figure is formed on the gate insulating film 19. 20 is provided as a gate electrode. Then, source-drain regions 21 doped with impurities are formed on the main surface of the region 18, and these source-drain regions 21 and the gate electrode (word line 20) form two MO8FETIOs in each region 18. is formed.

Then, the first conductive film 15 and the source/drain region 2
1 through a contact 22, and the second conductive film 17 is made conductive in each capacitor 11 to connect to GN.
Connect to D. Further, on an interlayer insulating film 23 such as PSG, which is provided over the entire surface of the MO8FETIO and the capacitor 11, a data layer [24] made of an AA film is provided which extends in the lateral direction shown in the drawing, and is connected to the source/drain region via a contact 25. 2] is connected to the other side.

Next, a method of manufacturing the memory cell M-CEL having the above structure, particularly the capacitor 11, will be explained with reference to FIGS.

Note that these figures correspond to the cross section of FIG. 3 (5).

First, as shown in FIG. 4, a mask patterned with a silicon oxide film 26 is formed on the main surface of the semiconductor substrate 12 with which a capacitor is to be formed, and this is dry-etched to form a trench 13. of a required depth. 13 are formed in close proximity. In the figure, 27 is a silicon nitride film. Then, by performing thermal oxidation in this state, an insulating film 14 made of a silicon oxide film is formed on each inner surface of the trenches 13 and 13 and on the partition wall portions 13a of both trenches, as shown in the figure.

Next, in the same figure (after removing the silicon oxide 11K 26 as a mask and the silicon nitride film 27 as shown in O), an oxide film 2B is formed on the surface of the substrate 2, and a first conductive film 15 is formed on the entire surface by CVD. Forming a polysilicon film 1,
Furthermore, a silicon oxide film as an insulating film 16 is formed thereon. Further, by depositing polysilicon as a second conductive film 17 on the entire surface by CVD and filling the grooves 13.13, and then etching back this, a capacitor 11.11 can be constructed. Prior to the formation of the first conductive film 15, an oxide film 28 at the contact 22 portion, which will be described later, is
A contact hole 22a is formed in the hole 22a.

Then, if a mask 29 is formed as shown in ) in the same figure, and then dry etching is performed to remove the film to a uniform thickness, directly adjacent capacitors 11 and 11 can be formed as shown in ) in the same figure.
The membranes 15, 15 can be separated from each other. Then, polysilicon that will become a part of the second conductive film 17 is deposited and patterned. This area of failure 18.18
The first conductive films 15, 1.5, a part of which will be extended as contacts 22.22 and 7, are formed in a self-aligned manner using the second conductive film pattern as a mask, as shown in FIG.
A capacitor 11.11 is completed as shown in FIG.

Subsequently, by performing surface oxidation, the oxide film on the capacitor and the gate oxide film 19 can be formed simultaneously.

Thereafter, a gate electrode, or word line 2o, can be formed by polysilicon deposition and selective etching.

Hereinafter, by forming MO8FETIO and data line 24 by a conventional method, D-R in FIGS.
AM can be completed.

According to the above configuration, the trench-shaped capacitor 11 is completely insulated from the semiconductor substrate 12 by the insulating film 14 provided on the inner surface of the trench, and moreover, the capacitor 11 is completely insulated from the semiconductor substrate 12 by the insulating film 14 provided on the inner surface of the trench. Since the insulation [14] exists, punch-through between the capacitors 11[deg.] 1 can be reliably prevented, and signal charges will not be lost. Therefore, it is possible to reduce the distance between the capacitors 11, 11, and the area occupied by the capacitors can be reduced. On the other hand, the groove 13 constituting the upper capacitor 1 can function as so-called groove type isolation by the insulating film 4 on the inner surface, and also acts as insulation between the MO8FETs 0. 'This makes it possible to prevent mutual interference between the MO8FETIOs, and in combination with the aforementioned reduction in the area occupied by the capacitor, it is possible to achieve high integration of the memory cell M-CEL as a whole.

〔effect〕

(11 The capacitor is formed in a groove shape. An insulating film is formed on the inner surface of the groove to insulate the capacitor from the semiconductor substrate. Therefore, if the capacitors are placed close to each other, there will be no Mohanchi through phenomenon. The degree of integration of capacitors can be improved by preventing the loss of charge.

(2) Since an insulating film is formed on the inner surface of the groove constituting the capacitor, the groove itself can be configured as a groove-type isolation, and as well as reducing the spacing between the element isolation regions, the element
It is possible to reduce the mutual spacing between KMO8FBTs and prevent mutual interference.

(3) In (1) above, it is possible to reduce the distance between the capacitor and MOSFET in f21, and the D-RAM
The degree of integration can be improved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, D-RAM
The planar layout of the MOSFETs and capacitors constituting the device is not limited to that shown in the drawings, but may have other configurations, and the arrangement of the data lines and word lines can be changed accordingly. Furthermore, other materials may be used for the first and second conductive films and insulating films that constitute the capacitor.

[Application field]

The above explanation will mainly focus on the one-element type D-RA, which is the field of application that was the background of the invention made by the present inventor.
Although we have explained the case where it is applied to M memory cells, other D
- Not only memory cells such as RAM and static RAM, but also any circuit element using MOSFET or capacitor can be similarly applied.

[Brief explanation of drawings]

Fig. 1 is a sectional view of a conventional structure, Fig. 2 is a plan layout of an embodiment of the present invention, Fig. 3 (Bl is an enlarged sectional view of edges AA and BB in Fig. 2, respectively), Fig. 4 A ~") is a partial process cross section M of the manufacturing method. 10... MOSFET, 11... Capacitor, 12
... Semiconductor substrate, 13... Groove, 14... Insulating film,
15... First conductive film, 16... Insulating film, 17...
Second conductive film, 19... Gate oxide film, 20... Word line (gate electrode), 22... Contact, 24...
- Data line, 25... Contact, 26... Silicon oxide film, 27... Silicon nitride film, 29... Mask, M-CEL... Memory cell. Figure 1 Figure 2 Zθ 2σ / Reno (, ], -5, l, ++ /n) L, 1
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LL -II -i "J-" 1, L, -Li 11 Dust C: + I22 '"1] 1 1 L'47 (II + 7.1, 1,, ... , -・2-7
）ゝゝゝ +）Do〆″′. A: Yu7” ・: Ward-1 1.- = − Figure 3 (A) 1 (13)

Claims (1)

[Claims] 1. In a semiconductor device in which a groove-type capacitor is formed on a semiconductor substrate, the capacitor is formed in a groove having an insulating film formed on the inner surface thereof while maintaining an insulated state from the semiconductor substrate. A semiconductor device characterized in that the entire groove is configured as a groove-type isolation for separating elements. 2. Claim 1, wherein the capacitor is constituted by a first conductive film formed on an insulating film on the inner surface of the groove, an insulating film formed thereon, and a second conductive film formed thereon. The semiconductor device described. 3. MOSFET on the semiconductor substrate next to the capacitor
3. The semiconductor device according to claim 1, wherein the MOSFET and the capacitor constitute a one-element type memory cell. 4. The semiconductor device according to claim 3, wherein a trench capacitor is provided between the MO8FETs for isolation.