JPS60113461A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the capacitance per unit area by a method wherein a groove is formed in an element isolation insulator buried in a semiconductor substrate, and the capacitor is constructed by utilizing the side surface and bottom surface thereof. CONSTITUTION:The first groove 2 is formed in the element isolation region of the Si substrate 1. The groove is filled by adhering an oxide film 3 over the entire surface, and resin 21 is applied thereon, the surface of which is then flattened. Next, the film 3 is left only in the groove 2 by etching, and the surface of the substrate is flattened. Then, the second grooves 5 are formed in the film 3, and the first electrode 6, a dielectric 7, and the second electrode 8 are successively buried in. In such a manner, the capacitor is formed by utilizing the side surface and the bottom surface of the grooves. Because the capacitor employs the structure of electrode 6-dielectric 7-electrode 8 instead of MOS structure, the consideration of interface levels and the like is not necessary, and Si nitride, etc. a high dielectric can be employed. Therefore, the capacitance per unit area of the capacitor can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a one-transistor, one-capacitor type MOS dynamic memory element that can be highly integrated.

(Prior art) Conventionally, a 1-transistor I+1-capacitor type dynamic memory has been widely used as a dynamic memory because it can be highly integrated, but it has the following problems in achieving even higher integration. Ta.

■ Due to higher integration, the cell area and capacitor area also decrease, so in order to obtain a sufficient noise margin, it is necessary to make the capacitor oxide film thinner so as not to reduce the capacitance, but making it thinner will reduce the manufacturing yield. descend.

■ Since the capacitor is formed of a MOS capacitor/IP capacitor consisting of a conductor electrode, a dielectric material, and a semiconductor substrate, there is a so-called FT error in which the contents of the memory cell change due to the charge generated by the α rays incident on the substrate. A phenomenon called ``2'' occurs, and there are problems with the reliability of the device.

(Object of the Invention) This invention was made in view of the above points, and its object is to increase the capacitor capacity t per unit area and to
It is an object of the present invention to provide a method for manufacturing a semiconductor device that allows a dynamic memory element with a large dose to be obtained.

(Summary of the Invention) The main point of this invention is to dig a groove in an insulator for isolation between elements embedded in a semiconductor substrate, and use the side and bottom surfaces of the groove to form a conductor electrode, a dielectric material, and a conductor electrode. The objective is to manufacture capacitors that

(Example) An example of the present invention will be described below with reference to the drawings.
Before that, the structure of a dynamic memory device manufactured according to an embodiment of the present invention will be explained with reference to FIGS. 1 and 2. FIG. 1 is a plan view of the dynamic memory element, and FIG. 2 is a sectional view taken along the line ■--■ in FIG. In these figures, reference numeral 1 denotes a P-type silicon substrate as a semiconductor substrate, on the surface side of which a first trench 2 is excavated and an oxide film 3 as an insulator for isolation between resistors is embedded. Further, a P-type channel stop layer 4 for preventing inversion is formed on the substrate portion under this oxide film 3. A second groove 5 is formed in the oxide film 3. Inside this second groove 5, after a first electrode 6 made of polysilicon is entirely formed on the bottom and side surfaces of the groove 5, a dielectric layer made of a silicon nitride film is formed on the first electrode 6. A capacitor is embedded by forming a second electrode 8 made of polysilicon on the dielectric 7 and then forming a second electrode 8 made of polysilicon.

Said first electrode 6 of this capacitor extends onto the substrate surface adjacent to the oxide film 3. Then, the first electrode 6 is connected to the N diffusion layer 9 formed in the adjacent substrate portion. In addition to the N+ diffusion layer 9, the P-type silicon substrate 1 is provided with a predetermined distance apart from the diffusion layer 9 in the opposite direction to the oxide film 3! A diffusion layer 10 is formed. Also a pair of these!
A gate oxide film 11 and a gate electrode 12 are laminated on the substrate surface between the diffusion layers 9 and 10.

That is, the gate oxide film 11 is formed on the silicon substrate 1.
and the gate electrode 12, and the N+ diffusion layer 9.10
A transfer gate transistor (MOS) transistor serving as a source and drain is formed at '. Further, on the silicon substrate 1, an oxide film 13 and an address line 14 are laminated to be located on the second electrode 8 of the capacitor in the capacitor portion. This address line 14 is formed of polysilicon together with the gate electrode 12 of the transfer gate transistor. Then, the address line 14 is connected to the gate voltage @112.

An insulating film 15 is formed on the entire surface of the silicon substrate 1 so as to cover the address lines 14, gate electrodes 12, and the like. Then, a bit line 16 made of aluminum is formed on this insulating film 15, and a trap protection film 17 is formed. Note that the bit line 16 is connected to one diffusion layer 10 via a contact hole 18 formed in the insulating film 15. Further, the second electrode 8 of the canopy 9 is connected to ground potential.

FIG. 3 shows an electrical circuit for one dynamic memory element as described above, where CI is a capacitor and T
1 is a transfer gate transistor.

Next, a method for manufacturing the above-mentioned dynamic memory element (an embodiment of the present invention) will be described with reference to FIG.

First, for example, P with an impurity concentration of 1×10 to 1×10 crn
A resist pattern is formed on a mold silicon substrate 1 having openings at locations that are to become inter-element isolation regions of the substrate. Next, using the resist as a mask, for example CBr
By etching the silicon substrate 1 using a reactive ion etching device using F5 gas, a first groove 2 with a depth of 2 μm is formed in the element isolation region of the silicon substrate 1.
form. Furthermore, using the resist as a mask, boron (
B) Dose t5X1012 or 5 X 10"'t
A P-type channel top layer 4 is formed in the substrate portion at the bottom of the first groove 2 by ion implantation at ons/m2.

(See FIG. 4A) Next, after the resist is completely removed, an oxide film (SiOa) 3 is deposited on the entire surface by sputtering to fill the first groove 2. A polyimide resin 21 is applied thereon to a thickness of 2 to 10 μm. At this time, the surface becomes almost flat due to the viscosity of the resin. (See FIG. 4(B)) Thereafter, the resin 21 and the oxide film 3 are etched using a reactive ion etching device using Freon gas mixed with oxygen, thereby converting the oxide film 3 into an insulator for isolation between elements. As shown in FIG. 4(C), the surface of the substrate is flattened by leaving only the first groove 2 in the first groove 2.

Next, in order to embed a capacitor in the remaining oxide film 3 and form a second trench, a resist pattern having an opening in the trench formation area is formed on the substrate 1 and the oxide film 3. Then, by etching the resist pattern using a reactive ion etching device using fluorocarbon gas, a 1.5 μm deep second pattern is formed on the oxide film 3.
Dig all grooves 5. (See Figure 4 (D)) After that, the exposed silicon substrate 1 is thermally oxidized.
An oxide film 22 of 100 to 500 Å is formed on the surface.

This oxide film 22 masks the diffusion of impurities from the first layer polysilicon to the substrate 1, which will be formed in a later step. (4th
(See FIG. 4(E)) Next, a part of the oxide film 22, that is, the portion of the oxide film 22 adjacent to the oxide film 3 serving as an insulator for isolation between elements is removed (see FIG. 4(F)). Next, a first layer of polysilicon containing a high concentration of impurities such as phosphorus (P) and arsenic (As) is deposited on the entire surface by low pressure CVD (chemical vapor deposition), and the polysilicon is -e turning is performed by photolithography, and the oxide film 22 used as a mask is removed. This allows the first
The first frost of the canopy made of layer polysilicon; pole 6
are formed extending over the side and bottom surfaces of the second groove 5 and also onto the surface of the substrate adjacent to the oxide film 3. Also, of course,
Oxide film 22 is removed. (Figure 4 (G)) After that,
Low-pressure CVD to form a silicon nitride film that will become the dielectric of the capacitor
The film is deposited to a thickness of 200 to 300 Å according to the method. In order to reduce the leakage current of the nitride film, 850 to 9
An oxide film with a thickness of 20 to 40 Å is formed on the surface of the nitride film in a wet oxygen atmosphere at 50°C. Next, a second layer of polysilicon containing a high concentration of phosphorus (CP) or arsenic (A8), for example, is deposited over the entire surface by low pressure CVD, and the film thickness is set so that the second #5 is completely buried. This results in a flat surface. Thereafter, the second layer polysilicon is turned by photolithography, and the silicon nitride film is further etched as a mask for all of the remaining polysilicon. As a result, a dielectric 7 of the capacitor made of a silicon nitride film is formed on the first electrode 6 of the capacitor, and a second electrode of the capacitor made of second excitation polysilicon is further formed on this dielectric 7. 8
is formed. (See Figure 4 (H)) Then, at 950°C
By performing oxidation in an oxygen atmosphere, an oxide film is formed on the entire surface. This oxide film has a thickness of 300 to 500× on the single crystal silicon substrate 1. Subsequently, molybdenum silicide is deposited on the entire surface by sputtering to a thickness of 3000 Å. Then, by turning the molybdenum silicide using photolithography technology, a gate electrode 1 of a transfer gate transistor (MOS) made of the molybdenum silicide is formed.
2 and address line 14 are formed at predetermined positions, respectively. Furthermore, by patterning the oxide film using the gate electrode 12 and the address line 14 as a mask, the gate oxide film 11 of the transfer gate transistor made of the oxide film and the insulating oxide film 1 under the address line 14 are formed.
form 3. Note that the address line 14 is turned t9 so as to be connected to the gate electrode 12.

(See FIG. 4 (I)) Thereafter, arsenic (As)' is ion-implanted into the substrate 1 in a self-aligned manner using the gate electrode 12 as a mask. of? A diffusion layer 9.10'e is formed. Here, one 1" diffusion layer 9 located on the side of the oxide film 3 serving as an insulator for isolation between elements is connected to the first electrode 6 of the capacitor. (See FIG. 4(I)) Next Then, for example, PSG (phosphorus silica glass) is deposited by the CVD method to form an insulating film 15 on the entire surface, and this insulating film 1
5 has a contact hole 18 on the 1-diffusion layer 10.
is formed using photolithography technology. Thereafter, by completely turning aluminum containing 1 to 2% silicon, the bit line 16 connected to the 1-diffusion layer 10 through the contact hole 18 is connected to the insulating film using the aluminum. 15. (See FIG. 4(J)) Finally, a protective film is formed on the entire surface. Through the above steps, the dynamic memory device shown in FIGS. 1 and 2 is completed.

Although the above is an N-channel process using a P-type silicon substrate 1, it is also possible to form the memory element in a P-well provided in an N-type substrate or an insulating substrate. , by reversing all the impurity polarities and power supply polarities, the device can also be constructed using the 'kP channel process.

Furthermore, although molybdenum silicide is used as the address line 14, it may be made of other high melting point metal silicides, or it may be of a so-called polycide structure in which polysilicon is laid under the silicide, or polysilicon may be used as long as it is devised to lower the resistance of the address line. .

Furthermore, as the dielectric material 7, silicon dioxide or a high dielectric material with a small leakage current may be used instead of silicon nitride.

(Effects of the Invention) As explained above, in the method for manufacturing a conductor device of the present invention, a groove is dug in an insulator for isolation between elements, and a capacitor is manufactured by fully utilizing the side and bottom surfaces of the groove. . Therefore, the capacitance per unit area of the capacitor can be reduced compared to a planar structure, and the total area of the capacitor can be reduced.

In addition, the capacitor is not an MO8 type structure, but a conductor electrode.
Since a one-conductor electrode structure is used, there is no need to fully consider interface states, which are a problem in MOS type, and high dielectric materials such as silicon nitride can be used. Therefore, the capacity per unit area of the canister is further increased, and the area of the canister can be further reduced.

Furthermore, since the capacitor is formed in a thick oxide film,
Carriers generated by α rays no longer flow into the capacitor from the substrate, improving the resistance to α rays.

[Brief explanation of drawings]

1 and 2 show a dynamic memory device manufactured according to an embodiment of the present invention, in which FIG. 1 is a plan view;
Fig. 2 is a sectional view taken along the line ■-11 in Fig. 1, Fig. 3 is an electrical equivalent circuit diagram of one dynamic/moly device, and Fig. 4 is a diagram of the method for manufacturing a conductor device of the present invention. FIG. 3 is a cross-sectional view showing one embodiment. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... First groove, 3...
- Oxide film, 5... Second groove, 6... First electrode, 7
...Conductor, 8...Second electrode, 9,10...N
10 diffusion layer, 11...gate oxide film, 12...gate electrode, CI...cano (shita), T+...transfer gate transistor. Patent applicant Oki Electric Industry Co., Ltd. 1, .1.j ( A) Figure 3 (C) □ Figure 4 ( (

Claims (1)

[Claims] a step of digging a first groove in the surface of the semiconductor substrate, a step of embedding an insulator for isolation between elements in the first groove, and a step of flattening the surface of the substrate, a step of digging a second groove in the insulator, That m
1. A method for manufacturing a semiconductor device, comprising the steps of sequentially embedding a first electrode, a dielectric material, and a second electrode in a groove of No. 2, and forming a MOS (MOS) transistor in the substrate.