JPS6113389B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a one-transistor memory cell.

Insulated gate field effect transistor (hereinafter referred to as
Memory cells configured with MISFETs have been provided with various circuit configurations. Among these, the one-transistor type memory cell, which consists of one MIS-structured capacitive element (hereinafter referred to as MIS capacitive element) and a writing/reading switching MISFET, has a small number of components, so it is highly integrated. It can be said that it is suitable for increasing storage capacity. However, unlike other circuit-type memory cells, this one-transistor type memory cell does not obtain the read voltage through amplifying MISEFT, but directly reads out the charge accumulated in the storage capacitor element. Read voltage ΔV is small, S/N
The problem is that the signal-to-noise ratio is poor.

Therefore, it is an object of the present invention to provide a one-transistor memory cell with a higher read voltage.

In order to achieve the above object, according to the present invention,
a semiconductor substrate of a first conductivity type; a first semiconductor region of a second conductivity type selectively formed on the surface of the substrate; a second conductivity type selectively formed on the surface of the substrate apart from the first semiconductor region; a second semiconductor region of the mold, a first electrode formed on the substrate between the first semiconductor region and the second semiconductor region via a first insulating film, and a second electrode formed on the second semiconductor region. a second electrode formed through an insulating film, the first insulating film formed between both ends of the first semiconductor region and the second semiconductor region spaced apart from each other; and Switching with the first electrode
A MISFET is configured, the first semiconductor region is electrically connected to a bit line, the first electrode is electrically connected to a word line, and the second semiconductor region, the second insulating film, and the second electrode are electrically connected to each other. Tode
A capacitive element having an MIS structure is configured, and a signal voltage to be stored in the capacitive element having the MIS structure is applied to the bit line, and the second conductivity type is applied to the second electrode. The one-transistor type memory cell is characterized in that a voltage having a polarity such that the surface of the second semiconductor region is more likely to be of the second conductivity type is applied thereto.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to embodiments and drawings.

FIG. 1 is a cross-sectional view for explaining a memory cell according to the present invention.

A conductive polycrystalline silicon 6 is formed on a p-type substrate 1 via a thin SiO ₂ film 2, and this is used as a gate electrode to convert the p-type substrate, which has a different substrate potential from V _SS (for example, -5V), into an n-type. voltage V _DD (e.g. +
12V) is applied to the gate electrode 6 to form an induced channel layer on the substrate surface under this electrode, and a storage MIS capacitor consisting of a drain 3, a source 4, and conductive polycrystalline silicon. In a one-transistor memory cell consisting of a switching MISFET consisting of a gate 7, the present invention puts the storage MIS capacitor in depletion mode in order to increase the read voltage.
Let it be MIS capacity. For this purpose, an n-type impurity is implanted into the surface of the substrate 1 under the gate electrode 6 by ion implantation to form an n ^- layer 5 (in the case of an n-channel MISFET).

The manufacturing method is the usual depression type.
As in the case of MISFET, for example, after forming a gate oxide film, this
N-type impurities are selectively introduced into the substrate surface directly under the gate of the MIS capacitor by ion implantation. After that, a polycrystalline silicon layer is formed on the gate oxide film to form the gate of the MIS capacitor and the gate of the switching MISEFT, and the source and drain are formed by diffusing n-type impurities using this gate as a mask. It is something.

In the example, the reason why a conductive polycrystalline silicon layer is used for the gate electrode is that the gate electrode of MISEFT constitutes a word line, and the MIS capacitor constitutes a power supply line.
Since the bit line connected to the source 4 of the MISFET must be arranged perpendicular to the word line and power supply line as shown in Figure 2, it is necessary to use an Al wiring layer for this bit line. It is. This Al wiring layer is
It is insulated from the conductive polycrystalline silicon film by an oxide film formed by CVD or the like, and can be electrically isolated from and orthogonal to a word line or the like.

According to the present invention having the above configuration, the object can be achieved for the following reasons.

Let the “1” level of the store voltage V _S be V _DD ,
If the “0” level is 0V, the maximum potential difference ΔV obtained on the bit line BL is the enhancement type
In the case of a conventional memory cell using MIS capacity (1)
The formula according to the present invention is shown in formula (2). In these equations, C _S is the MIS capacitance value, C _B is the parasitic capacitance value of the bit line, and Q _ST is the amount of charge accumulated in the MIS capacitance. Further, V _T is the threshold voltage of the MISFET.

ΔV _1nax = Q _ST / C _S + C _B = C _S (V _DD - V _T )
/C _S +C _B (1) ΔV _2nax =Q _ST /C _S +C _B =C _S (V _DD +V _T )
/C _S +C _B (2) Therefore, the read voltage ΔV ₂ according to the invention
is improved compared to the conventional read voltage ΔV ₁ as shown in equation (3).

ΔV ₂ /ΔV ₁ = V _DD + |V _T |/V _DD −V _T (3) However, since the store voltage V _S is not normally made larger than V _DD , it is practically as shown in equation (4). will be improved.

ΔV ₂ /ΔV ₁ = V _DD /V _DD −V _T (4) In the above equations (1) to (4), the drain junction capacitance of MISFET, which changes depending on the store voltage, is omitted from the explanation. It is.

That is, according to the present invention, the signal voltage (V _S ) (report voltage) applied to the bit line is +V _DD volts (“1” level) and 0 volts (“0” level).
In the case ^of
Since it is biased to _DD volts, V _S = +V _D
When the voltage is _D volts, it becomes 0 volts, and when V _S = 0 volts, it becomes +V _DD (voltage with a polarity in the direction that the gate electrode 6 further changes the n ^- layer 5 to n-type), and the voltage is accumulated in the MIS capacitance at this time. ^The _{charge Q}
Since it changes from to V _THD , Q _ST = C _S V _DD without being affected by the threshold voltage.
The amount of charge that can be stored is compared to the conventional one C _S (V _DD −V _TH
E ) can be increased. At this time,
The capacitance versus voltage characteristic (C-V characteristic) of the MIS capacitor is in a region where there is little change in capacitance due to the bias voltage applied to the gate electrode 6, so the amount of accumulated charge due to a change in signal voltage can be further increased. .

These matters can be explained qualitatively as follows.

As shown in Figure 3, when the MIT capacitor is in enhancement mode, the accumulated charge Q with respect to the write voltage V is curved because there is a loss in the store voltage by the voltage required for channel induction, that is, the threshold voltage V _THE . l It becomes as shown in ₁ . On the other hand, in depression mode, this curve
The curve l ₂ is obtained by moving l ₁ in parallel to the maximum store voltage V _DD + |V _THD |. Therefore, the maximum stored charge is
_Q2 . These things are
This can be easily understood from the gate voltage-drain current characteristics of MISFET.

The present invention is not limited to the above embodiments, and similar effects can be obtained in other embodiments as described below.

For example, using an n-type substrate to create a p-channel type
The memory cell may be configured with MISFET.

In this case, a voltage with a polarity that changes the n-type substrate to p-type, for example, -12V, is applied to the gate electrode constituting the MIS capacitor. In the present invention, any means for depleting the MIS capacitance may be used, and the p ⁺
Any method may be used to form the regions. Furthermore, although the gate electrodes of MISFETs and MIS capacitors may be composed of layers of Al, it must be noted that they must have a double wiring structure. Furthermore, the wiring pattern can be modified in various ways.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a memory cell according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a one-transistor type memory cell, and FIG. 3 is a characteristic diagram for explaining the present invention. 1...Substrate, 2...SiO ₂ film, 3...Drain, 4...Source, 5...Channel region, 6,
7...Gate electrode.

Claims (1)

[Claims] 1 a first conductivity type semiconductor substrate; a second conductivity type first semiconductor region selectively formed on the surface of the substrate;
a second semiconductor region of a second conductivity type selectively formed on the surface of the substrate apart from the first semiconductor region; a first insulating region on the substrate between the first semiconductor region and the second semiconductor region; a first electrode formed through a film, and a second electrode formed on the second semiconductor region through a second insulating film, the first semiconductor region and the second semiconductor spaced apart from each other; A switching MISFET is configured by both ends of the region, the first insulating film and the first electrode formed between the two ends, and the first semiconductor region is used as a bit line, and the first electrode is used as a word line. The second semiconductor region, the second insulating film, and the second electrode constitute a capacitive element of an MIS structure, and the bit line has a capacitor of the MIS structure. a signal to be stored in the element is applied to the second element;
A one-transistor memory cell characterized in that a voltage having a polarity such that the surface of the second semiconductor region of the second conductivity type is more likely to become the second conductivity type is applied to the electrode. .