JPS59135B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a semiconductor memory device having a memory cell composed of one transistor and one capacitor.

Conventionally, it has been said that a semiconductor memory device having a memory cell composed of one transistor and one capacitor can have a high degree of integration.

However, in a typical 1-transistor, 1-capacitor memory cell, the transistor and the capacitor are arranged laterally, that is, in a planar manner on the surface of the semiconductor substrate.

Therefore, this transistor and capacitor are arranged vertically,
That is, it is possible to further improve the degree of integration of this type of device by arranging it three-dimensionally.
This has been realized as seen in issue 1.

As described above, the present invention improves the characteristics of a highly integrated semiconductor memory device by arranging transistors and capacitors three-dimensionally.Examples will be described in detail below.

FIG. 1 is a sectional side view of a main part of an embodiment of the present invention.

In the figure, 1 is an n-type silicon semiconductor substrate, 2 is a field insulating film, 3 is a p-type charge storage region, 4 is an insulating film for charge storage region, 5 is a p-type silicon semiconductor layer (channel region), and 6 is an n-type silicon semiconductor layer. type source region, T is an n-type drain region, 8 is a gate insulating film, 9 is a gate electrode, Vs is a source terminal, V
G indicates a gate terminal, and VD indicates a drain terminal. In this embodiment, the silicon semiconductor layer 5 is grown after patterning the insulating film 4 and exposing a part of the surface of the substrate 1, so that the silicon semiconductor layer 5 formed on the surface of the substrate 1 is 5 is a single crystal, and
The layers formed on the insulating film 4 and the insulating film 2 are polycrystalline. In the illustrated portion, the single crystal silicon semiconductor layer 5 is a channel region, and the source region 6 and drain region T are made of polycrystalline silicon. In addition, the above-mentioned patent application
In No. 1-125951, the channel region is made of polycrystalline silicon, and the charge storage region is in contact with the source region (or drain region), but in the present invention, the channel region is made of single crystal silicon, and the charge storage region 3 is made of polycrystalline silicon. Since it is in contact with the channel region, its operating characteristics are different. 2 and 3 are explanatory diagrams showing the flow of charges and the polarity of the voltage applied to each terminal during the write operation and read operation in the embodiment of FIG. 1, and FIGS. 4 a and b , c are diagrams illustrating the states of charges e during writing, storage, and reading, respectively.

In FIG. 4, 4 and 8 are the same insulating films as shown in FIG. 1, and 3'' and 5'' are the interface between the charge storage region 3 and the insulating film 4, and the channel region 5 and the insulating film. Interface with 8, e
indicate the electric charge, respectively. Next, the write, storage, and read modes will be explained with reference to these figures.

4th ship F? When write terminals Vs and VG are set to high level and terminal VD is set to low level, charges injected from terminal VD are transferred to source region 6.
, are accumulated in the depletion layer at the interface between the charge storage region 3 and the insulating film 4, which is caused by the high level of the source region, via the channel region 5.

Note that if the insulating film 4 is thin, charge may be injected directly from the terminal s as a tunnel current. If Vs and D are set to low levels, no charge injection will occur.

When the memory terminal s is set to high level and the other terminals VG and D are all set to low level, "1° or "
゜0'' is maintained as it is.

When the read terminal Vs is set to a low level and the terminals VG and VD are set to a high level, the potential of the channel region 5 changes depending on the stored "゜1゛" or "O", which causes the so-called back gate effect. will occur.

In this example, when charges (electrons) are accumulated, that is, “
When ゜1゛ is written, an effect similar to that of applying a negative back gate voltage is produced, and therefore, under the same gate voltage (potential of terminal VG), the drain current 1D decreases, Alternatively, the gate threshold voltage Vth apparently increases. This drain current 1D (or gate threshold voltage Vth
) can detect "B" and "O".
As explained in the above reading operation, the present invention is based on the above-mentioned Japanese Patent Application No.
Unlike No. 125951, the stored charge is not directly taken out and read out, but the back gate effect is used for reading out, so the memory cell itself has a charge detection amplification function, and therefore has high sensitivity. This eliminates the need for a detector and requires a smaller amount of accumulated charge, that is, the area of the accumulation region is small, which has the effect of improving the degree of integration.

Furthermore, unlike a transistor using a polycrystalline semiconductor layer in the channel region as disclosed in Japanese Patent Application No. 51-125951, since a single crystal semiconductor layer is used in the channel region, there is a reduction in speed due to a decrease in carrier mobility, and characteristic reproducibility. No problem of sexual deterioration arises. As can be seen from the above explanation, according to the present invention, transistors and capacitors are vertically integrated three-dimensionally, so that the area occupied on the plane is reduced compared to that of a conventional one-transistor, one-capacitor memory. Since it is significantly smaller than a cell, it is convenient for improving the degree of integration, and since all the semiconductor parts involved in carrier movement are single crystal, its mobility is high.
Nuitching speed is fast.

[Brief explanation of drawings]

FIG. 1 is a sectional side view of a main part of an embodiment of the present invention, FIGS. 2 and 3 are schematic diagrams explaining the operation of the embodiment of FIG. 1, and FIG. 4A
, b, and c are explanatory diagrams showing the movement of charges during the operations shown in FIGS. 2 and 3.

Claims (1)

[Claims] 1. A charge storage region of an opposite conductivity type formed on the surface of a semiconductor substrate of one conductivity type surrounded by a thick insulating film, an insulating film located on the region and partially opened with a window, and A channel region made of a single crystal semiconductor layer of an opposite conductivity type and in contact with the charge storage region through the channel region, a source region and a drain region made of a polycrystalline semiconductor layer of one conductivity type facing each other with the channel region interposed therebetween, and the channel region. A semiconductor memory device comprising a gate electrode formed thereon with an insulating film interposed therebetween.