US20010052607A1 - Nonvolatile semiconductor memory - Google Patents
Nonvolatile semiconductor memory Download PDFInfo
- Publication number
- US20010052607A1 US20010052607A1 US09/879,081 US87908101A US2001052607A1 US 20010052607 A1 US20010052607 A1 US 20010052607A1 US 87908101 A US87908101 A US 87908101A US 2001052607 A1 US2001052607 A1 US 2001052607A1
- Authority
- US
- United States
- Prior art keywords
- ferroelectric film
- silicon substrate
- ferroelectric
- gate electrode
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims abstract description 60
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 58
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 58
- 239000010703 silicon Substances 0.000 claims abstract description 58
- 230000010287 polarization Effects 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 229910052814 silicon oxide Inorganic materials 0.000 description 17
- 238000013500 data storage Methods 0.000 description 9
- 239000000969 carrier Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000008030 elimination Effects 0.000 description 3
- 238000003379 elimination reaction Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
Definitions
- the present invention relates to a nonvolatile semiconductor memory using a ferroelectric capacitor for controlling the gate potential of a field effect transistor (FET).
- FET field effect transistor
- a source region 2 and a drain region 3 are formed in a silicon substrate 1 and a silicon oxide film 5 serving as a dielectric film is formed on a channel region 4 formed between the source region 2 and the drain region 3 in the silicon substrate 1 as shown in FIG. 4.
- a ferroelectric film 6 of a metal oxide such as lead zirconate titanate (PZT) or bismuth tantalate—strontium (SBT) is formed on the silicon oxide film 5 , and a gate electrode 7 is formed on the ferroelectric film 6 .
- PZT lead zirconate titanate
- SBT bismuth tantalate—strontium
- the depth of the surface potential of the region in the silicon substrate 1 below the gate electrode 7 controls the resistance between the source region 2 and the drain region 3 , and hence, the resistance between the source region 2 and the drain region 3 is set to a large value or a small value correspondingly to the polarization direction of the ferroelectric film 6 .
- These states are kept (stored) as far as the polarization of the ferroelectric film 6 is kept, and thus, the ferroelectric memory works as a nonvolatile memory.
- the downward polarized state of the ferroelectric film 6 is assumed logic “1” and the upward polarized state thereof is assumed logic “0”.
- FIG. 5A shows energy band obtained in the ferroelectric memory by applying a positive bias voltage to the gate electrode 7 so as to turn the polarization of the ferroelectric film 6 downward (namely, to write a data of logic “1”) and then changing the potential of the gate electrode 7 to the ground potential.
- FIG. 5B shows energy band obtained in the ferroelectric memory by applying a negative bias voltage to the gate electrode 7 so as to turn the polarization of the ferroelectric film 6 upward (namely, to write a data of logic “0”) and then changing the potential of the gate electrode 7 to the ground potential.
- FIGS. 1 shows energy band obtained in the ferroelectric memory by applying a positive bias voltage to the gate electrode 7 so as to turn the polarization of the ferroelectric film 6 downward (namely, to write a data of logic “1”) and then changing the potential of the gate electrode 7 to the ground potential.
- a reference numeral 30 denotes the direction of polarization
- a reference numeral 31 denotes the conduction band of the gate electrode 7
- a reference numeral 32 denotes the energy band of the ferroelectric film 6
- a reference numeral 33 denotes the energy band of the silicon oxide film 5
- a reference numeral 35 denotes an n-type conduction channel and a broken line denotes the Fermi level.
- the n-type conduction channel 35 is formed in the region in the silicon substrate 1 below the gate electrode 7 (namely, in the channel region 4 ), and hence, the surface potential of the silicon substrate 1 is lower than the ground potential.
- the surface potential of the region in the silicon substrate 1 below the gate electrode is thus different depending upon the polarization direction of the ferroelectric film 6 . Therefore, when a potential difference is caused between the drain region 3 and the source region 2 , a current depending upon the polarization direction flows between the drain region 3 and the source region 2 . Specifically, when the surface potential of the silicon substrate 1 is lower than the ground potential (which corresponds to logic “1”), the resistance between the drain region 3 and the source region 2 is low (which corresponds to an on-state) so that a large current can flow.
- the ferroelectric memory is in an on-state (corresponding to logic “1”) or an off-state (corresponding to logic “0”) by measuring the magnitude of the current flowing between the drain region 3 and the source region 2 .
- the logic state of the ferroelectric memory can be read by causing a potential difference between the source and the drain without applying a bias voltage to the gate electrode 7 . Accordingly, the on-state of the ferroelectric memory corresponds to a depletion state of a MOS transistor.
- the ferroelectric film 6 is an insulating film and has resistivity of approximately 10 15 ⁇ .cm at most. Therefore, when the ferroelectric film 6 has a thickness of 100 nm, the resistance per 1 cm 2 of the ferroelectric film 6 is 10 7 ⁇ .
- the ferroelectric film 6 and the gate electrode 7 have substantially the same area as shown in FIG. 4, and hence, the area of the ferroelectric film 6 and the gate electrode 7 is herein standardized to 1 cm 2 so as to examine the electric characteristic of the ferroelectric memory.
- FIG. 6 shows an equivalent circuit of the ferroelectric memory obtained when the gate electrode 7 and the silicon substrate 1 have the ground potential.
- C ox indicates the capacitance of the silicon oxide film 5
- C F indicates the capacitance of the ferroelectric film 6
- R F indicates the internal resistance of the ferroelectric film 6 .
- the value of C ox is 0.1 ⁇ F/cm 2 at most, which is substantially equal to the capacitance of a silicon oxide film of a standard MOS transistor, and the value of C F is 1 ⁇ F/cm 2 . Therefore, the parallel capacitance of these capacitances is approximately 1 ⁇ F/cm 2 .
- the value of R F is 10 7 ⁇ as described above.
- the virtual floating potential at a point A in the equivalent circuit of FIG. 6 is exponentially lowered by discharging the capacitance C ox and the capacitance C F through the resistance R F .
- the time constant obtained in this case is (C ox +C F ) ⁇ R F , that is, approximately 10 seconds.
- the actual time constant tends to be larger due to trapping in the gate electrode 7 and the shift from the ohm conductivity at a low voltage, and still, the upper limit of the time constant obtained through an experiment is 1 seconds at most.
- the resistivity of the ferroelectric film 6 needs to be increased to at least approximately 10 20 ⁇ .cm, namely, to five or more figures.
- an object of the invention is providing a nonvolatile semiconductor memory capable of storing a data for a long period of time by suppressing loss of charge accompanied by a leakage current in a ferroelectric film.
- the first nonvolatile semiconductor memory of this invention comprises a source region and a drain region formed in a silicon substrate; a dielectric film formed above a region of the silicon substrate between the source region and the drain region; a ferroelectric film formed on the dielectric film; and a gate electrode formed on the ferroelectric film, and the ferroelectric film and the silicon substrate have a p-type conductivity, and the source region and the drain region have an n-type conductivity.
- the second nonvolatile semiconductor memory of this invention comprises a source region and a drain region formed in a silicon substrate; a dielectric film formed above a region of the semiconductor substrate between the source region and the drain region; a ferroelectric film formed on the dielectric film; and a gate electrode formed on the ferroelectric film, and the ferroelectric film and the silicon substrate have an n-type conductivity, and the source region and the drain region have a p-type conductivity.
- the ferroelectric film and the silicon substrate have the same conductivity type. Therefore, even when a bias voltage is applied to the ferroelectric film for writing a data, the loss of charge accompanied by a leakage current is minimally caused in the ferroelectric film because there are few carriers of charge with the same polarity as the bias voltage. Accordingly, a conduction channel formed in a surface portion of the silicon substrate can be kept for a long period of time and is constantly kept until an operation for eliminating the conduction channel is carried out. Also, after the operation for eliminating the conduction is carried out, the elimination of the conduction channel can be permanently kept.
- FIG. 1 is a cross-sectional view of a nonvolatile semiconductor memory according to Embodiment 1 or 2 of the invention
- FIGS. 2A and 2B are energy band diagrams of the nonvolatile semiconductor memory of Embodiment 1 obtained in its data storage state;
- FIGS. 3A and 3B are energy band diagrams of the nonvolatile semiconductor memory of Embodiment 2 obtained in its data storage state;
- FIG. 4 is a cross-sectional view of a conventional nonvolatile semiconductor memory
- FIGS. 5A and 5B are energy band diagrams of the conventional nonvolatile semiconductor memory obtained in its data storage state.
- FIG. 6 is an equivalent circuit diagram of a conventional ferroelectric memory obtained when a gate electrode and a silicon substrate have the ground potential.
- FIG. 1 shows the cross-sectional structure of the nonvolatile semiconductor memory commonly employed in Embodiments 1 and 2.
- a source region 11 and a drain region 12 are formed in a silicon substrate 10 , and a silicon oxide film 14 serving as a dielectric film is formed on a channel region 13 formed in the silicon substrate 10 between the source region 11 and the drain region 12 .
- a ferroelectric film 15 of a metal oxide is formed on the silicon oxide film 14 , and a gate electrode 16 is formed on the ferroelectric film 15 .
- the ferroelectric film 15 has the p-type conductivity
- the silicon substrate 10 has the p-type conductivity
- the source region 11 and the drain region 12 have the n-type conductivity. Accordingly, a field effect transistor of the ferroelectric memory is an n-channel transistor.
- FIGS. 2A and 2B are energy band diagrams of the nonvolatile semiconductor memory of Embodiment 1, namely, the ferroelectric memory including the ferroelectric film 15 and the silicon substrate 10 both having the p-type conductivity, obtained in its data storage state.
- a reference numeral 20 denotes the direction of polarization
- a reference numeral 21 denotes the energy band of the gate electrode 16
- a reference numeral 22 denotes the energy band of the ferroelectric film 15
- a reference numeral 23 denotes the energy band of the silicon oxide film 14
- a reference numeral 24 denotes the energy band of the p-type silicon substrate 10
- a broken line denotes the Fermi level.
- a bias voltage positive with respect to the p-type silicon substrate 10 is applied to the gate electrode 16 so as to turn the polarization of the ferroelectric film 15 downward and the bias voltage is then changed to zero.
- an n-type conduction channel 25 formed on the p-type silicon substrate 10 is kept as shown in FIG. 2A.
- a bias voltage negative with respect to the silicon substrate 10 is applied to the ferroelectric film 15 . Since the negative bias voltage is thus applied, the carriers of charge are injected into the ferroelectric film 15 either as holes injected from the silicon oxide film 14 or as electrons injected from the gate electrode 16 .
- the silicon substrate 10 has the p-type 5 conductivity and the ferroelectric film 15 has the p-type conductivity in Embodiment 1
- the electrons injected from the gate electrode 16 cannot be conducted through the ferroelectric film 15 . Therefore, the electrons that cannot be conducted are locally present on the interface between the gate electrode 16 and the ferroelectric film 15 .
- the surface potential of the ferroelectric film 15 with respect to the electrons is acceleratingly increased, so that the electrons cannot be actually injected.
- the bias voltage applied to the ferroelectric film 15 can be kept for a long period of time. Accordingly, the n-type conduction channel 25 formed in the surface portion of the p-type silicon substrate 10 can be kept.
- a bias voltage negative with respect to the p-type silicon substrate 10 is applied to the gate electrode 16 so as to turn the polarization of the ferroelectric film 15 upward and the bias voltage is then changed to zero.
- the n-type conduction channel 25 formed in the surface portion of the p-type silicon substrate 10 is eliminated as shown in FIG. 2B.
- the negative bias voltage applied to the gate electrode 16 is set to a sufficiently small value so as not to be applied to the ferroelectric film 15 . Therefore, the energy band is substantially placed in thermal equilibrium state as shown in FIG. 2B, and hence, the elimination of the n-type conduction channel 25 can be permanently kept.
- the ferroelectric film 15 has the n-type conductivity
- the silicon substrate 10 has the n-type conductivity
- the source region 11 and the drain region 12 have the p-type conductivity. Therefore, the field effect transistor of the ferroelectric memory is a p-channel transistor.
- FIGS. 3A and 3B are energy band diagrams of the nonvolatile semiconductor memory of Embodiment 2, namely, the ferroelectric memory including the ferroelectric film 15 and the silicon substrate 10 both having the n-type conductivity, obtained in its data storage state.
- a reference numeral 20 denotes the direction of polarization
- a reference numeral 21 denotes the energy band of the gate electrode 16
- a reference numeral 22 denotes the energy band of the ferroelectric film 15
- a reference numeral 23 denotes the energy band of the silicon oxide film 14
- a reference numeral 24 denotes the energy band of the n-type silicon substrate 10
- a broken line denotes the Fermi level.
- a bias voltage negative with respect to the n-type silicon substrate 10 is applied to the gate electrode 16 so as to turn the polarization of the ferroelectric film 15 upward and the bias voltage is then changed to zero.
- a p-type conduction channel 27 formed in the surface portion of the n-type silicon substrate 10 is kept as shown in FIG. 3A.
- a bias voltage positive with respect to the silicon substrate 10 is applied to the ferroelectric film 15 . Since the positive bias voltage is thus applied, the carriers of charge are injected into the ferroelectric film 15 either as electrons injected from the silicon oxide film 14 or as holes injected from the gate electrode 16 .
- the silicon substrate 10 has the n-type conductivity and the ferroelectric film 15 has the n-type conductivity in Embodiment 2
- the holes injected from the gate electrode 16 cannot be conducted through the ferroelectric film 15 . Therefore, the holes that cannot be conducted are locally present on the interface between the gate electrode 16 and the ferroelectric film 15 .
- the surface potential of the ferroelectric film 15 with respect to the holes is acceleratingly increased, so that the holes cannot be actually injected.
- the bias voltage applied to the ferroelectric film 15 can be kept for a long period of time. Accordingly, the p-type conduction channel 27 formed in the surface portion of the n-type silicon substrate 10 can be kept.
- a bias voltage positive with respect to the n-type silicon substrate 10 is applied to the gate electrode 16 so as to turn the polarization of the ferroelectric film 15 downward and the bias voltage is then changed to zero.
- the p-type conduction channel 27 formed in the surface portion of the n-type silicon substrate 10 is eliminated as shown in FIG. 3B.
- the positive bias voltage applied to the gate electrode 16 is set to a sufficiently small value so as not to be applied to the ferroelectric film 15 . Therefore, the energy band is substantially placed in thermal equilibrium state as shown in FIG. 3B, and hence, the elimination of the p-type conduction channel 27 can be permanently kept.
- the data storage time can be longer when a p-channel FET is formed by using an n-type silicon substrate than when an n-channel FET is formed by using a p-type silicon substrate.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
- The present invention relates to a nonvolatile semiconductor memory using a ferroelectric capacitor for controlling the gate potential of a field effect transistor (FET).
- In a conventional nonvolatile ferroelectric memory using a ferroelectric capacitor for controlling the gate potential of a FET, a
source region 2 and adrain region 3 are formed in a silicon substrate 1 and a silicon oxide film 5 serving as a dielectric film is formed on achannel region 4 formed between thesource region 2 and thedrain region 3 in the silicon substrate 1 as shown in FIG. 4. A ferroelectric film 6 of a metal oxide such as lead zirconate titanate (PZT) or bismuth tantalate—strontium (SBT) is formed on the silicon oxide film 5, and agate electrode 7 is formed on the ferroelectric film 6. - In the ferroelectric memory, upward or downward polarization can be caused in the ferroelectric film6, and the depth of the surface potential of a region in the silicon substrate 1 below the
gate electrode 7 can be set to two different values respectively corresponding to the two polarized states of the ferroelectric film 6. - In this case, the depth of the surface potential of the region in the silicon substrate1 below the gate electrode 7 (namely, the channel region) controls the resistance between the
source region 2 and thedrain region 3, and hence, the resistance between thesource region 2 and thedrain region 3 is set to a large value or a small value correspondingly to the polarization direction of the ferroelectric film 6. These states are kept (stored) as far as the polarization of the ferroelectric film 6 is kept, and thus, the ferroelectric memory works as a nonvolatile memory. - For storing any of two logic states in the ferroelectric memory or reading any of the two logic states from the ferroelectric memory, for example, the downward polarized state of the ferroelectric film6 is assumed logic “1” and the upward polarized state thereof is assumed logic “0”.
- In order to turn the polarization of the ferroelectric film6 downward to write a data (of logic “1”) in the ferroelectric memory, a large positive voltage is applied to the
gate electrode 7 with the silicon substrate 1 set to the ground potential. On the other hand, in order to turn the polarization of the ferroelectric film 6 upward to write a data (of logic “0”) in the ferroelectric memory, a large negative voltage is applied to thegate electrode 7 with the silicon substrate 1 set to the ground potential. Thereafter, the potential of thegate electrode 7 is rapidly changed to the ground potential due to a junction leakage current of the FET, namely, a potential difference between thegate electrode 7 and the silicon substrate 1 is rapidly eliminated, and thus, the written data is kept. - The data storage state of the ferroelectric memory will now be described with reference to energy band diagrams of FIGS. 5A and 5B.
- It is assumed, for example, that the silicon substrate1 has the p-type conductivity and the
source region 2 and thedrain region 3 have the n-type conductivity. FIG. 5A shows energy band obtained in the ferroelectric memory by applying a positive bias voltage to thegate electrode 7 so as to turn the polarization of the ferroelectric film 6 downward (namely, to write a data of logic “1”) and then changing the potential of thegate electrode 7 to the ground potential. FIG. 5B shows energy band obtained in the ferroelectric memory by applying a negative bias voltage to thegate electrode 7 so as to turn the polarization of the ferroelectric film 6 upward (namely, to write a data of logic “0”) and then changing the potential of thegate electrode 7 to the ground potential. In FIGS. 5A and 5B, areference numeral 30 denotes the direction of polarization, areference numeral 31 denotes the conduction band of thegate electrode 7, areference numeral 32 denotes the energy band of the ferroelectric film 6, areference numeral 33 denotes the energy band of the silicon oxide film 5, areference numeral 35 denotes an n-type conduction channel and a broken line denotes the Fermi level. - When the polarization of the ferroelectric film6 is downward, a negatively ionized depletion layer extends to a deep region of the silicon substrate 1. Therefore, as shown in FIG. 5A, the n-
type conduction channel 35 is formed in the region in the silicon substrate 1 below the gate electrode 7 (namely, in the channel region 4), and hence, the surface potential of the silicon substrate 1 is lower than the ground potential. - On the other hand, when the polarization of the ferroelectric film6 is upward, holes, that is, p-type carriers, are stored in the region in the silicon substrate 1 below the gate electrode 7 (namely, in the channel region 4) and hence the n-type conduction channel is not formed in the
channel region 4 as shown in FIG. 5B. Therefore, the surface potential of the silicon substrate 1 accords with the ground potential. - The surface potential of the region in the silicon substrate1 below the gate electrode is thus different depending upon the polarization direction of the ferroelectric film 6. Therefore, when a potential difference is caused between the
drain region 3 and thesource region 2, a current depending upon the polarization direction flows between thedrain region 3 and thesource region 2. Specifically, when the surface potential of the silicon substrate 1 is lower than the ground potential (which corresponds to logic “1”), the resistance between thedrain region 3 and thesource region 2 is low (which corresponds to an on-state) so that a large current can flow. When the surface potential of the silicon substrate 1 accords with the ground potential (which corresponds to logic “0”), the resistance between thedrain region 3 and thesource region 2 is high (which corresponds to an off-state) so that a current can minimally flow. Accordingly, it can be determined that the ferroelectric memory is in an on-state (corresponding to logic “1”) or an off-state (corresponding to logic “0”) by measuring the magnitude of the current flowing between thedrain region 3 and thesource region 2. - In this manner, the logic state of the ferroelectric memory can be read by causing a potential difference between the source and the drain without applying a bias voltage to the
gate electrode 7. Accordingly, the on-state of the ferroelectric memory corresponds to a depletion state of a MOS transistor. - After writing a data in the ferroelectric memory, a positive or negative bias voltage is inevitably generated in the ferroelectric film6 as shown in FIGS. 5A and 5B. The silicon oxide film 5 and the silicon substrate 1 are supplied with potentials so as to cancel the bias voltage, and whether the ferroelectric memory is in an on-state or off-state depends upon the thus supplied potentials.
- The ferroelectric film6 is an insulating film and has resistivity of approximately 1015 Ω.cm at most. Therefore, when the ferroelectric film 6 has a thickness of 100 nm, the resistance per 1 cm2 of the ferroelectric film 6 is 107 Ω.
- The ferroelectric film6 and the
gate electrode 7 have substantially the same area as shown in FIG. 4, and hence, the area of the ferroelectric film 6 and thegate electrode 7 is herein standardized to 1 cm2 so as to examine the electric characteristic of the ferroelectric memory. - FIG. 6 shows an equivalent circuit of the ferroelectric memory obtained when the
gate electrode 7 and the silicon substrate 1 have the ground potential. In FIG. 6, Cox indicates the capacitance of the silicon oxide film 5, CF indicates the capacitance of the ferroelectric film 6 and RF indicates the internal resistance of the ferroelectric film 6. The value of Cox is 0.1 μF/cm2 at most, which is substantially equal to the capacitance of a silicon oxide film of a standard MOS transistor, and the value of CF is 1 μF/cm2. Therefore, the parallel capacitance of these capacitances is approximately 1 μF/cm2. The value of RF is 107 Ω as described above. Accordingly, the virtual floating potential at a point A in the equivalent circuit of FIG. 6 is exponentially lowered by discharging the capacitance Cox and the capacitance CF through the resistance RF. The time constant obtained in this case is (Cox+CF)×RF, that is, approximately 10 seconds. The actual time constant tends to be larger due to trapping in thegate electrode 7 and the shift from the ohm conductivity at a low voltage, and still, the upper limit of the time constant obtained through an experiment is 1 seconds at most. - This means that the bias voltage applied to the ferroelectric film6 is lost so as to eliminate the conduction channel within approximately 103 seconds.
- In order to practically use the ferroelectric memory as a nonvolatile memory, the data storage time is desired to be 10 years (=108 seconds) or more. In order to attain this data storage time, the resistivity of the ferroelectric film 6 needs to be increased to at least approximately 1020 Ω.cm, namely, to five or more figures.
- However, a ferroelectric film with such large resistivity cannot be obtained at the present day, which hinders the practical use of a ferroelectric memory.
- In consideration of the aforementioned circumstances, an object of the invention is providing a nonvolatile semiconductor memory capable of storing a data for a long period of time by suppressing loss of charge accompanied by a leakage current in a ferroelectric film.
- In order to achieve the object, the first nonvolatile semiconductor memory of this invention comprises a source region and a drain region formed in a silicon substrate; a dielectric film formed above a region of the silicon substrate between the source region and the drain region; a ferroelectric film formed on the dielectric film; and a gate electrode formed on the ferroelectric film, and the ferroelectric film and the silicon substrate have a p-type conductivity, and the source region and the drain region have an n-type conductivity.
- Also in order to achieve the object, the second nonvolatile semiconductor memory of this invention comprises a source region and a drain region formed in a silicon substrate; a dielectric film formed above a region of the semiconductor substrate between the source region and the drain region; a ferroelectric film formed on the dielectric film; and a gate electrode formed on the ferroelectric film, and the ferroelectric film and the silicon substrate have an n-type conductivity, and the source region and the drain region have a p-type conductivity.
- In the first or second nonvolatile semiconductor memory of this invention, the ferroelectric film and the silicon substrate have the same conductivity type. Therefore, even when a bias voltage is applied to the ferroelectric film for writing a data, the loss of charge accompanied by a leakage current is minimally caused in the ferroelectric film because there are few carriers of charge with the same polarity as the bias voltage. Accordingly, a conduction channel formed in a surface portion of the silicon substrate can be kept for a long period of time and is constantly kept until an operation for eliminating the conduction channel is carried out. Also, after the operation for eliminating the conduction is carried out, the elimination of the conduction channel can be permanently kept.
- As a result, a data can be stored for a long period of time in the first or second nonvolatile semiconductor memory of the invention.
- FIG. 1 is a cross-sectional view of a nonvolatile semiconductor memory according to
Embodiment 1 or 2 of the invention; - FIGS. 2A and 2B are energy band diagrams of the nonvolatile semiconductor memory of Embodiment 1 obtained in its data storage state;
- FIGS. 3A and 3B are energy band diagrams of the nonvolatile semiconductor memory of
Embodiment 2 obtained in its data storage state; - FIG. 4 is a cross-sectional view of a conventional nonvolatile semiconductor memory;
- FIGS. 5A and 5B are energy band diagrams of the conventional nonvolatile semiconductor memory obtained in its data storage state; and
- FIG. 6 is an equivalent circuit diagram of a conventional ferroelectric memory obtained when a gate electrode and a silicon substrate have the ground potential.
- The cross-sectional structure of a nonvolatile semiconductor memory according to
Embodiment 1 or 2 of the invention will now be described with reference to FIG. 1. - FIG. 1 shows the cross-sectional structure of the nonvolatile semiconductor memory commonly employed in
Embodiments 1 and 2. Asource region 11 and adrain region 12 are formed in asilicon substrate 10, and a silicon oxide film 14 serving as a dielectric film is formed on achannel region 13 formed in thesilicon substrate 10 between thesource region 11 and thedrain region 12. A ferroelectric film 15 of a metal oxide is formed on the silicon oxide film 14, and agate electrode 16 is formed on the ferroelectric film 15. - In the ferroelectric memory according to Embodiment 1 of the invention, the ferroelectric film15 has the p-type conductivity, the
silicon substrate 10 has the p-type conductivity, and thesource region 11 and thedrain region 12 have the n-type conductivity. Accordingly, a field effect transistor of the ferroelectric memory is an n-channel transistor. - Owing to this structure, the loss of charge accompanied by a leakage current is minimally caused in the ferroelectric film15, so that a data can be stored for a long period of time. The reason will now be described with reference to FIGS. 2A and 2B.
- FIGS. 2A and 2B are energy band diagrams of the nonvolatile semiconductor memory of Embodiment 1, namely, the ferroelectric memory including the ferroelectric film15 and the
silicon substrate 10 both having the p-type conductivity, obtained in its data storage state. - In FIGS. 2A and 2B, a
reference numeral 20 denotes the direction of polarization, areference numeral 21 denotes the energy band of thegate electrode 16, areference numeral 22 denotes the energy band of the ferroelectric film 15, areference numeral 23 denotes the energy band of the silicon oxide film 14, areference numeral 24 denotes the energy band of the p-type silicon substrate 10, and a broken line denotes the Fermi level. - Now, attention is paid to carriers of charge of a leakage current flowing through the internal resistance of the ferroelectric film15 of the ferroelectric memory. Since the ferroelectric film 15 and the silicon oxide film 14 are in direct contact with each other, charge present on their interface is polarization charge. Accordingly, freely movable carriers are not present on the interface.
- In order to place the ferroelectric memory of Embodiment 1 in an on-state, a bias voltage positive with respect to the p-
type silicon substrate 10 is applied to thegate electrode 16 so as to turn the polarization of the ferroelectric film 15 downward and the bias voltage is then changed to zero. Thus, an n-type conduction channel 25 formed on the p-type silicon substrate 10 is kept as shown in FIG. 2A. - At this point, as obvious from FIG. 2A, a bias voltage negative with respect to the
silicon substrate 10 is applied to the ferroelectric film 15. Since the negative bias voltage is thus applied, the carriers of charge are injected into the ferroelectric film 15 either as holes injected from the silicon oxide film 14 or as electrons injected from thegate electrode 16. - However, there is no freely movable carrier in the vicinity of the interface between the ferroelectric film15 and the silicon oxide film 14, and therefore, holes are never injected from the silicon oxide film 14. Accordingly, the injected carriers are merely the electrons injected from the
gate electrode 16. - Since the
silicon substrate 10 has the p-type 5 conductivity and the ferroelectric film 15 has the p-type conductivity in Embodiment 1, the electrons injected from thegate electrode 16 cannot be conducted through the ferroelectric film 15. Therefore, the electrons that cannot be conducted are locally present on the interface between thegate electrode 16 and the ferroelectric film 15. As a result, the surface potential of the ferroelectric film 15 with respect to the electrons is acceleratingly increased, so that the electrons cannot be actually injected. - Since the electrons are not injected from the
gate electrode 16 in this manner, the bias voltage applied to the ferroelectric film 15 can be kept for a long period of time. Accordingly, the n-type conduction channel 25 formed in the surface portion of the p-type silicon substrate 10 can be kept. - In order to place the ferroelectric memory of Embodiment 1 in an off-state, a bias voltage negative with respect to the p-
type silicon substrate 10 is applied to thegate electrode 16 so as to turn the polarization of the ferroelectric film 15 upward and the bias voltage is then changed to zero. Thus, the n-type conduction channel 25 formed in the surface portion of the p-type silicon substrate 10 is eliminated as shown in FIG. 2B. - At this point, the negative bias voltage applied to the
gate electrode 16 is set to a sufficiently small value so as not to be applied to the ferroelectric film 15. Therefore, the energy band is substantially placed in thermal equilibrium state as shown in FIG. 2B, and hence, the elimination of the n-type conduction channel 25 can be permanently kept. - In the ferroelectric memory of
Embodiment 2, the ferroelectric film 15 has the n-type conductivity, thesilicon substrate 10 has the n-type conductivity, and thesource region 11 and thedrain region 12 have the p-type conductivity. Therefore, the field effect transistor of the ferroelectric memory is a p-channel transistor. - Owing to this structure, the loss of charge accompanied by a leakage current is minimally caused in the ferroelectric film15, so that a data can be stored for a long period of time. The reason will now be described with reference to FIGS. 3A and 3B.
- FIGS. 3A and 3B are energy band diagrams of the nonvolatile semiconductor memory of
Embodiment 2, namely, the ferroelectric memory including the ferroelectric film 15 and thesilicon substrate 10 both having the n-type conductivity, obtained in its data storage state. - In FIGS. 3A and 3B, a
reference numeral 20 denotes the direction of polarization, areference numeral 21 denotes the energy band of thegate electrode 16, areference numeral 22 denotes the energy band of the ferroelectric film 15, areference numeral 23 denotes the energy band of the silicon oxide film 14, areference numeral 24 denotes the energy band of the n-type silicon substrate 10, and a broken line denotes the Fermi level. - In order to place the ferroelectric memory of
Embodiment 2 in an on-state, a bias voltage negative with respect to the n-type silicon substrate 10 is applied to thegate electrode 16 so as to turn the polarization of the ferroelectric film 15 upward and the bias voltage is then changed to zero. Thus, a p-type conduction channel 27 formed in the surface portion of the n-type silicon substrate 10 is kept as shown in FIG. 3A. - At this point, as obvious from FIG. 3A, a bias voltage positive with respect to the
silicon substrate 10 is applied to the ferroelectric film 15. Since the positive bias voltage is thus applied, the carriers of charge are injected into the ferroelectric film 15 either as electrons injected from the silicon oxide film 14 or as holes injected from thegate electrode 16. - However, there is no freely movable carrier in the vicinity of the interface between the ferroelectric film15 and the silicon oxide film 14, and therefore, electrons are never injected from the silicon oxide film 14. Accordingly, the injected carriers are merely the holes injected from the
gate electrode 16. - Since the
silicon substrate 10 has the n-type conductivity and the ferroelectric film 15 has the n-type conductivity inEmbodiment 2, the holes injected from thegate electrode 16 cannot be conducted through the ferroelectric film 15. Therefore, the holes that cannot be conducted are locally present on the interface between thegate electrode 16 and the ferroelectric film 15. As a result, the surface potential of the ferroelectric film 15 with respect to the holes is acceleratingly increased, so that the holes cannot be actually injected. - Since the holes are not injected from the
gate electrode 16 in this manner, the bias voltage applied to the ferroelectric film 15 can be kept for a long period of time. Accordingly, the p-type conduction channel 27 formed in the surface portion of the n-type silicon substrate 10 can be kept. - In order to place the ferroelectric memory of
Embodiment 2 in an off-state, a bias voltage positive with respect to the n-type silicon substrate 10 is applied to thegate electrode 16 so as to turn the polarization of the ferroelectric film 15 downward and the bias voltage is then changed to zero. Thus, the p-type conduction channel 27 formed in the surface portion of the n-type silicon substrate 10 is eliminated as shown in FIG. 3B. - At this point, the positive bias voltage applied to the
gate electrode 16 is set to a sufficiently small value so as not to be applied to the ferroelectric film 15. Therefore, the energy band is substantially placed in thermal equilibrium state as shown in FIG. 3B, and hence, the elimination of the p-type conduction channel 27 can be permanently kept. - Accordingly, in the case where the ferroelectric film15 is formed from, for example, a SrBi2(Ta, Nb)2O9 film having the n-type conductivity, the data storage time can be longer when a p-channel FET is formed by using an n-type silicon substrate than when an n-channel FET is formed by using a p-type silicon substrate.
Claims (2)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000182643A JP2002009255A (en) | 2000-06-19 | 2000-06-19 | Nonvolatile semiconductor storage |
JP2000-182643 | 2000-06-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010052607A1 true US20010052607A1 (en) | 2001-12-20 |
US6455883B2 US6455883B2 (en) | 2002-09-24 |
Family
ID=18683366
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/879,081 Expired - Fee Related US6455883B2 (en) | 2000-06-19 | 2001-06-13 | Nonvolatile semiconductor memory |
Country Status (7)
Country | Link |
---|---|
US (1) | US6455883B2 (en) |
EP (1) | EP1168454B1 (en) |
JP (1) | JP2002009255A (en) |
KR (1) | KR100655028B1 (en) |
CN (1) | CN1181553C (en) |
DE (1) | DE60118061T2 (en) |
TW (1) | TW511275B (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004047176A1 (en) * | 2002-11-20 | 2004-06-03 | National Institute Of Advanced Industrial Science And Technology | Ferroelectric memory array |
US20140169061A1 (en) * | 2011-03-31 | 2014-06-19 | Thales | Method of implementing a ferroelectric tunnel junction, device comprising a ferroelectric tunnel junction and use of such a device |
US11018239B2 (en) * | 2019-04-13 | 2021-05-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4831562B2 (en) * | 2005-06-23 | 2011-12-07 | 富士通株式会社 | Ferroelectric memory device |
US11502103B2 (en) * | 2018-08-28 | 2022-11-15 | Intel Corporation | Memory cell with a ferroelectric capacitor integrated with a transtor gate |
US11980037B2 (en) | 2020-06-19 | 2024-05-07 | Intel Corporation | Memory cells with ferroelectric capacitors separate from transistor gate stacks |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5578846A (en) * | 1995-03-17 | 1996-11-26 | Evans, Jr.; Joseph T. | Static ferroelectric memory transistor having improved data retention |
KR0141160B1 (en) * | 1995-03-22 | 1998-06-01 | 김광호 | Ferroelectric memory and manufacturing method thereof |
-
2000
- 2000-06-19 JP JP2000182643A patent/JP2002009255A/en active Pending
-
2001
- 2001-06-13 US US09/879,081 patent/US6455883B2/en not_active Expired - Fee Related
- 2001-06-19 TW TW090114863A patent/TW511275B/en not_active IP Right Cessation
- 2001-06-19 DE DE60118061T patent/DE60118061T2/en not_active Expired - Lifetime
- 2001-06-19 EP EP01114688A patent/EP1168454B1/en not_active Expired - Lifetime
- 2001-06-19 KR KR1020010034609A patent/KR100655028B1/en not_active IP Right Cessation
- 2001-06-19 CN CNB011188332A patent/CN1181553C/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004047176A1 (en) * | 2002-11-20 | 2004-06-03 | National Institute Of Advanced Industrial Science And Technology | Ferroelectric memory array |
US20140169061A1 (en) * | 2011-03-31 | 2014-06-19 | Thales | Method of implementing a ferroelectric tunnel junction, device comprising a ferroelectric tunnel junction and use of such a device |
US9312471B2 (en) * | 2011-03-31 | 2016-04-12 | Thales | Method of implementing a ferroelectric tunnel junction, device comprising a ferroelectric tunnel junction and use of such a device |
US11018239B2 (en) * | 2019-04-13 | 2021-05-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
EP1168454A2 (en) | 2002-01-02 |
EP1168454A3 (en) | 2004-03-03 |
DE60118061D1 (en) | 2006-05-11 |
KR20010113555A (en) | 2001-12-28 |
US6455883B2 (en) | 2002-09-24 |
DE60118061T2 (en) | 2006-08-17 |
TW511275B (en) | 2002-11-21 |
EP1168454B1 (en) | 2006-03-22 |
CN1350333A (en) | 2002-05-22 |
KR100655028B1 (en) | 2006-12-07 |
JP2002009255A (en) | 2002-01-11 |
CN1181553C (en) | 2004-12-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7123503B2 (en) | Writing to ferroelectric memory devices | |
US5877977A (en) | Nonvolatile memory based on metal-ferroelectric-metal-insulator semiconductor structure | |
US7253464B2 (en) | Junction-isolated depletion mode ferroelectric memory devices and systems | |
US6714435B1 (en) | Ferroelectric transistor for storing two data bits | |
US6128212A (en) | Metal ferroelectric silicon field effect transistor memory | |
KR100629543B1 (en) | Memory cell arrangement | |
KR100716391B1 (en) | Semiconductor memory device, method for driving the same and method for fabricating the same | |
US6888736B2 (en) | Ferroelectric transistor for storing two data bits | |
US6455883B2 (en) | Nonvolatile semiconductor memory | |
KR20030009073A (en) | Semiconductor memory device and method for driving the same | |
KR20010051175A (en) | Tunneling transistor applicable to nonvolatile memory | |
US6771530B2 (en) | Semiconductor memory and method for driving the same | |
US6574131B1 (en) | Depletion mode ferroelectric memory device and method of writing to and reading from the same | |
US6509594B2 (en) | Semiconductor memory device having MFMIS transistor and increased data storage time |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHIMADA, YASUHIRO;KATO, YOSHIHISA;REEL/FRAME:011899/0379 Effective date: 20010530 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20140924 |