JPS6335111B2 - - Google Patents

Info

Publication number
JPS6335111B2
JPS6335111B2 JP54096421A JP9642179A JPS6335111B2 JP S6335111 B2 JPS6335111 B2 JP S6335111B2 JP 54096421 A JP54096421 A JP 54096421A JP 9642179 A JP9642179 A JP 9642179A JP S6335111 B2 JPS6335111 B2 JP S6335111B2
Authority
JP
Japan
Prior art keywords
region
drain region
type
transistor
floating gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54096421A
Other languages
Japanese (ja)
Other versions
JPS5621375A (en
Inventor
Shinpei Tsucha
Takashi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9642179A priority Critical patent/JPS5621375A/en
Priority to EP80302039A priority patent/EP0021777B1/en
Priority to DE8080302039T priority patent/DE3065360D1/en
Priority to CA000354232A priority patent/CA1139880A/en
Publication of JPS5621375A publication Critical patent/JPS5621375A/en
Priority to US06/526,219 priority patent/US4491859A/en
Publication of JPS6335111B2 publication Critical patent/JPS6335111B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7886—Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Description

【発明の詳細な説明】 本発明は、ゲート絶縁膜中に電荷を捕獲し得る
フローテイング・ゲートが形成され、そこでの電
荷の有無によるゲート閾値電圧の変化を記憶機能
として利用する形式の半導体不揮発性記憶装置に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor nonvolatile device in which a floating gate capable of trapping charges is formed in a gate insulating film, and changes in gate threshold voltage depending on the presence or absence of charges there are used as a memory function. Concerning sexual memory.

一般に、半導体不揮発性記憶装置としては、大
別すると、ゲート絶縁膜中に電荷を蓄積する導体
層を有するもの即ちフローテイング・ゲート型、
異種絶縁膜界面などにトラツプが形成されること
を利用してこれをゲート絶縁膜とするもの例えば
MNOS型或いはMAOS型が知られている。これ
等はいずれもフローテイング・ゲートやトラツプ
へ電荷を注入して蓄積できるようにし、その蓄積
電荷の有無に依つてゲート閾値電圧が変化するこ
とを利用して記憶作用に結び付けているものであ
る。 In general, semiconductor nonvolatile memory devices can be roughly divided into those that have a conductor layer that accumulates charges in a gate insulating film, that is, floating gate type;
For example, a method that utilizes the formation of traps at the interface of different types of insulating films and uses this as a gate insulating film.
MNOS type and MAOS type are known. All of these devices allow charge to be injected into the floating gate or trap so that it can be accumulated, and the gate threshold voltage changes depending on the presence or absence of the accumulated charge, which is linked to the memory effect. .

この際の電荷の注入は、フローテイング・ゲー
ト型はアバランシエ・ブレイク・ダウンに依つて
ホツト・キヤリヤを注入するアバランシエ注入
で、また、MNOS型などではトンネル効果を利
用したトンネル注入でそれぞれ行なうようにして
いるものである。 Charge injection at this time is carried out by avalanche injection, which injects a hot carrier using avalanche breakdown, for floating gate types, and by tunnel injection, which utilizes the tunnel effect, for MNOS types. It is something that

ところで、これ等従来の装置は種々の欠点を持
つているが、その最大のものは、フローテイン
グ・ゲート或いはトラツプへ電荷を注入する所謂
書込み時に高い電圧を必要とし、しかもそれが極
性の異なる電圧である為、書込み用の特別な電源
を必要とすることである。 By the way, these conventional devices have various drawbacks, but the biggest one is that they require a high voltage during so-called writing, which injects charge into the floating gate or trap, and moreover, the voltage is of a different polarity. Therefore, a special power supply for writing is required.

このような欠点に対処する為には、例えば、フ
ローテイング・ゲート型では、ドレイン接合近傍
でのアバランシエ・ブレイク・ダウンが起り易い
ように、即ち、低電圧でそれが発生するようにで
きれば良いので、ドレイン領域との間でｐ・ｎ接
合を形成する部分の不純物濃度を高めることが行
なわれる。しかしながら、従来の装置では、書込
み及び消去の時と読出し時とに於いて動作するド
レイン回路は同一であるから、アバランシエ・ブ
レイク・ダウン電圧を低下させると読出し時にも
僅かながらホツト・キヤリヤが発生してフローテ
イング・ゲートに注入される為、ゲート閾値電圧
の変動を正確に検出することが困難となる惧れが
ある。従つて、充分な書込み及び消去電圧の低下
はなし得ない状態にある。また、MNOS型など
絶縁膜中のトラツプを利用するものでは、第２層
目の絶縁膜を薄くすることに依り書込み及び消去
電圧を低下させることが考えられている。しかし
ながら、そのようにすると、記憶保持特性の劣化
を生じ、そして、この型式のものに於いても読出
し時のキヤリヤ注入が発生する。従つて、この場
合も書込み及び消去電圧の充分な低下はなし得な
い。 In order to deal with these drawbacks, for example, in the floating gate type, it is necessary to make avalanche breakdown more likely to occur near the drain junction, that is, to make it occur at a lower voltage. , the impurity concentration in a portion forming a p/n junction with the drain region is increased. However, in conventional devices, the drain circuit that operates during writing and erasing and during reading is the same, so if the avalanche breakdown voltage is lowered, a small amount of hot carrier will occur during reading as well. Since the current is injected into the floating gate, it may be difficult to accurately detect fluctuations in the gate threshold voltage. Therefore, it is impossible to reduce the write and erase voltages sufficiently. Furthermore, in devices such as the MNOS type that utilize traps in an insulating film, it is considered that the write and erase voltages can be lowered by making the second layer of the insulating film thinner. However, doing so causes deterioration of memory retention characteristics, and even in this type, carrier injection occurs during reading. Therefore, in this case as well, the write and erase voltages cannot be lowered sufficiently.

本発明は、フローテイング・ゲート型の半導体
不揮発性記憶装置に於いて、ドレイン接合でのア
バランシエ・ブレイク・ダウン電圧を低下させる
ようにしても、読出し時にホツト・キヤリヤが発
生しないようにし、従つて、書込み及び消去電圧
を大幅に低下させることができるようにするもの
であり、以下これを詳細に説明する。 The present invention prevents the generation of hot carriers during reading even if the avalanche breakdown voltage at the drain junction is lowered in a floating gate type semiconductor non-volatile memory device. , it is possible to significantly lower the write and erase voltages, and this will be explained in detail below.

第１図は本発明一実施例の要部側断面図であ
る。 FIG. 1 is a sectional side view of a main part of an embodiment of the present invention.

図に於いて、１は1015〜1016〔cm-3〕程度の不純
物濃度を有するｐ型シリコン半導体基板、２は不
純物濃度が例えば1020〔cm-3〕程度のn+型ソース
領域、３は不純物濃度が例えば1017〔cm-3〕程度
のn+型ドレイン領域、４はn+型ソース領域、５
はn+型ドレイン領域、６はp+型領域、７はフロ
ーテイング・ゲート、８はゲート電極、９は燐硅
酸ガラス（PSG）などの絶縁膜、１０は例えば
アルミニウムのソース電極・配線、１１はp+型
領域６とドレイン領域５とを結ぶ例えばアルミニ
ウムの配線、１２は例えばアルミニウムのソース
電極・配線、１３はメモリ・トランジスタの第１
層膜である熱窒化膜からなるゲート絶縁膜、１４
はスイツチング・トランジスタに於ける二酸化シ
リコンのゲート絶縁膜、１５は例えばアルミニウ
ムからなるゲート配線、１６は二酸化シリコンの
フイールド絶縁膜、QMはメモリ・トランジスタ、
QSはスイツチング・トランジスタをそれぞれ示
す。 In the figure, 1 is a p-type silicon semiconductor substrate having an impurity concentration of about 10 15 to 10 16 [cm -3 ], 2 is an n + type source region having an impurity concentration of about 10 20 [cm -3 ], for example, 3 is an n + type drain region with an impurity concentration of, for example, about 10 17 [cm -3 ], 4 is an n + type source region, and 5 is an n + type source region.
is an n + type drain region, 6 is a p + type region, 7 is a floating gate, 8 is a gate electrode, 9 is an insulating film such as phosphosilicate glass (PSG), 10 is a source electrode/wiring made of aluminum, for example, 11 is a wiring made of aluminum, for example, connecting the p + type region 6 and the drain region 5, 12 is a source electrode/wiring made of aluminum, and 13 is the first part of the memory transistor.
A gate insulating film made of a thermal nitride film, which is a layered film, 14
is a silicon dioxide gate insulating film in a switching transistor, 15 is a gate wiring made of aluminum, 16 is a silicon dioxide field insulating film, Q M is a memory transistor,
Q S represents a switching transistor, respectively.

本実施例に於けるp+型領域６の不純物濃度は
基板１よりも高くすることが必要であり、例えば
1020〔cm-3〕程度に選ばれる。そして、これに依
りドレイン領域３とp+型領域６との間のｐ・ｎ
接合に於ける耐圧は５〔〕程度となる。また、
ゲート絶縁膜１３の厚さは50〜60〔Å〕である。 In this embodiment, the impurity concentration of the p + type region 6 needs to be higher than that of the substrate 1, for example.
It is chosen to be around 10 20 [cm -3 ]. As a result, p/n between the drain region 3 and the p + type region 6
The breakdown voltage in the bonding is about 5[]. Also,
The thickness of the gate insulating film 13 is 50 to 60 [Å].

第２図はドレイン領域３内に形成されたp+型
領域６の様子を説明する為の要部平面図である。
図から判るように、p+型領域６はドレイン領域
３に完全に囲まれ、ソース領域２と対向するｐ・
ｎ接合面はフローテイング・ゲート７の下或いは
端面に重なるようにしてある。 FIG. 2 is a plan view of a main part for explaining the state of the p + type region 6 formed in the drain region 3. FIG.
As can be seen from the figure, the p + type region 6 is completely surrounded by the drain region 3, and the p + type region 6 facing the source region 2
The n-junction surface is arranged to overlap the bottom or end surface of the floating gate 7.

本実施例の動作は次の通りである。即ち、スイ
ツチング・トランジスタQSのソース領域４は常
に接地されていて、書込み及び消去の際は、トラ
ンジスタQSのゲート電極８に正電圧を印加して
導通させる。メモリ・トランジスタQMのドレイ
ン領域３には電圧が印加されるようになつている
為、トランジスタQSの導通に依つて、その電圧
はドレイン領域３とp+型領域６との間で形成さ
れるｐ・ｎ接合に印加されるようになる。ドレイ
ン領域３に印加する電圧を例えば５〔〕に上昇
させると前記ｐ・ｎ接合でアバランシエ・ブレイ
ク・ダウンを生じる。この時、トランジスタQM
のソース領域２を正電位に保つと、ソース領域２
と重なり容量を介して結合されているフローテイ
ング・ゲート７も正電位に保たれ、前記アバラン
シエ・ブレイク・ダウンで発生したホツト・エレ
クトロンがフローテイング・ゲート７に注入され
るものであり、従つて、トランジスタQMのチヤ
ネル領域はｐ型、即ちオフとなつて書込みが行な
われたことになる。また、トランジスタQMのソ
ース領域２を接地電位に保つと、同様にフローテ
イング・ゲート７も接地電位に近づく為、アバラ
ンシエ・ブレイク・ダウン領域からホツト・ホー
ルがフローテイング・ゲート７に注入され、トラ
ンジスタQMのチヤネル領域はｎ型に反転、即ち
オンとなり消去が行なわれる。さて、読出しの際
は、トランジスタQSのゲート電極８を接地電位
にしてオフとする。このようにすると、ドレイン
領域３に正電圧が印加されていても、その電圧は
ドレイン領域３とp+型領域６とで形成される
ｐ・ｎ接合には印加されず、アバランシエ・ブレ
イク・ダウンは発生しない。この時、トランジス
タQMのソース領域２を接地電位にすると、この
トランジスタQMのオン・オフがドレイン領域３
に印加された正電位に依つて読出されるものであ
る。 The operation of this embodiment is as follows. That is, the source region 4 of the switching transistor Q S is always grounded, and during writing and erasing, a positive voltage is applied to the gate electrode 8 of the transistor Q S to make it conductive. Since a voltage is applied to the drain region 3 of the memory transistor Q M , the voltage is formed between the drain region 3 and the p + type region 6 depending on the conduction of the transistor Q S. The current is applied to the p-n junction. When the voltage applied to the drain region 3 is increased to, for example, 5[], avalanche breakdown occurs at the p/n junction. At this time, transistor Q M
When the source region 2 of is kept at a positive potential, the source region 2
The floating gate 7, which overlaps and is coupled via capacitance, is also kept at a positive potential, and the hot electrons generated in the avalanche breakdown are injected into the floating gate 7. , the channel region of transistor Q M is p-type, ie, off, and writing is performed. Furthermore, when the source region 2 of the transistor Q M is kept at the ground potential, the floating gate 7 similarly approaches the ground potential, so hot holes are injected into the floating gate 7 from the avalanche breakdown region. The channel region of the transistor Q M is inverted to n-type, that is, turned on, and erasing is performed. Now, at the time of reading, the gate electrode 8 of the transistor Q S is set to the ground potential to be turned off. In this way, even if a positive voltage is applied to the drain region 3, that voltage is not applied to the p-n junction formed between the drain region 3 and the p + type region 6, resulting in avalanche breakdown. does not occur. At this time, if the source region 2 of the transistor Q M is set to the ground potential, the on/off of this transistor Q M is controlled by the drain region 3
It is read out depending on the positive potential applied to.

前記実施例では、メモリ・トランジスタQMの
ゲート絶縁膜として熱窒化膜を採用したが、これ
は他の種類の絶縁膜にすることができるのは勿論
であり、また、同じくメモリ・トランジスタQM
のコントロール・ゲートとしてソース電極１０を
用いているが、これは従来多用されているように
フローテイング・ゲート上に絶縁膜を介して形成
したコントロール・ゲートの形式にしても良く、
また、紫外線消去をする形式の場合には除去する
ことも可能であり、その他種々の改変を加えるこ
とができる。 In the above embodiment, a thermal nitride film was used as the gate insulating film of the memory transistor Q M , but it is of course possible to use other types of insulating film, and it is also possible to use a thermal nitride film as the gate insulating film of the memory transistor Q M
Although the source electrode 10 is used as a control gate in the present invention, this may be in the form of a control gate formed on a floating gate with an insulating film interposed therebetween, as is often used in the past.
Further, in the case of a type that uses ultraviolet rays, it can be removed, and various other modifications can be made.

第３図及び第４図は他の一実施例を説明する為
の要部側断面図及び要部平面図である。 3 and 4 are a side sectional view and a plan view of a main part for explaining another embodiment.

この実施例は所謂SOS型であつて、基板として
γ―Al2O3，α―Al2O3，スピネルなどの単結晶
絶縁基板１７を用いて形成したものであり、第１
図及び第２図に関して説明した部分と同部分を同
記号で指示してあり、その動作は全く同様であ
る。尚、１８，１９はチヤネル領域であるｐ型領
域である。 This embodiment is of the so-called SOS type, and is formed using a single crystal insulating substrate 17 made of γ-Al 2 O 3 , α-Al 2 O 3 , spinel, etc. as a substrate.
The same parts as those explained with reference to FIGS. and 2 are designated by the same symbols, and their operations are exactly the same. Note that 18 and 19 are p-type regions which are channel regions.

以上の説明で判るように、本発明に依れば、メ
モリ・トランジスタのドレイン領域に接してそれ
とは反対導電型の領域を形成し、その領域を接地
電位とフロートとに切換えることに依つてブレイ
ク・ダウン回路の形成及び切離しを行なつてい
る。従つて読出しの際にはブレイク・ダウン回路
が切離されていて、メモリ・トランジスタのドレ
イン領域とそれに接して形成された反対導電型領
域とで形成された接合の耐圧を充分に低下させて
も、読出し時に蓄積情報が悪影響を受けることは
ない。その為、従来のものに比較してアバランシ
エ・ブレイク・ダウン電圧を著しく低下させるこ
とが可能である。また、既説明実施例に見られる
ように、メモリ・トランジスタのソース電極を書
込み及び消去時のコントロール電極として使用す
る場合にはゲート絶縁膜（熱窒化膜）が極めて薄
い為、コントロール電極に印加する電圧は低電圧
で済むものである。このように、本発明の装置で
は、従来のものに比較して書込み及び消去電圧の
著しい低減が可能であつて、メモリ・セルは５
〔〕のみで動作し、集積化した場合であつても
７〔〕程度の集積回路標準電源のみを用いて書
込み、消去、読出しの全ての動作をさせることが
でき、何等特別な電源を必要とせず、また、消費
電力も僅少化できる。 As can be seen from the above description, according to the present invention, a region of the opposite conductivity type is formed in contact with the drain region of the memory transistor, and the break is achieved by switching the region between a ground potential and a float. - Forming and disconnecting down circuits. Therefore, the breakdown circuit is disconnected during readout, and even if the breakdown voltage of the junction formed between the drain region of the memory transistor and the opposite conductivity type region formed in contact with it is sufficiently lowered, , the stored information is not adversely affected when read. Therefore, it is possible to significantly reduce the avalanche breakdown voltage compared to the conventional one. Furthermore, as seen in the previously described embodiments, when the source electrode of a memory transistor is used as a control electrode during writing and erasing, since the gate insulating film (thermal nitride film) is extremely thin, it is necessary to apply a voltage to the control electrode. A low voltage is sufficient. Thus, in the device of the present invention, it is possible to significantly reduce the write and erase voltages compared to the conventional device, and the memory cell can be
It operates only with [ ], and even when integrated, it can perform all write, erase, and read operations using only a standard power supply of about 7 [], and does not require any special power supply. Furthermore, power consumption can also be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明一実施例の要部側断面図、第２
図は第１図実施例の要部平面図、第３図は他の実
施例の要部側断面図、第４図は第３図実施例の要
部平面図である。 図に於いて、１は基板、２はソース領域、３は
ドレイン領域、４はソース領域、５はドレイン領
域、６はp+型領域、７はフローテイング・ゲー
ト、８はゲート電極、１０，１２はソース電極・
配線、１１は配線、１３，１４はゲート絶縁膜、
１５はゲート配線である。 Fig. 1 is a side sectional view of the main part of one embodiment of the present invention, Fig.
The drawings are a plan view of the main part of the embodiment shown in FIG. 1, FIG. 3 is a side sectional view of the main part of another embodiment, and FIG. 4 is a plan view of the main part of the embodiment shown in FIG. In the figure, 1 is a substrate, 2 is a source region, 3 is a drain region, 4 is a source region, 5 is a drain region, 6 is a p + type region, 7 is a floating gate, 8 is a gate electrode, 10, 12 is the source electrode
Wiring, 11 is wiring, 13 and 14 are gate insulating films,
15 is a gate wiring.

Claims (1)

【特許請求の範囲】[Claims] １ チヤネル領域を介して対向するソース領域及
びドレイン領域、前記チヤネル領域上に絶縁膜を
介して形成されたフローテイング・ゲート、前記
ドレイン領域に接し且つ前記フローテイング・ゲ
ートの端部に近接して形成され前記ドレイン領域
とは反対導電型を有して前記ドレイン領域とｐ・
ｎ接合を形成する不純物導入領域を備えてなるメ
モリ・トランジスタと、前記メモリ・トランジス
タの書込み・消去時に前記ｐ・ｎ接合に対してア
バランシエ・ブレイク・ダウンを生起せしめる所
定電位を印加し、前記メモリ・トランジスタの読
出し時には前記所定電位を与えず、アバランシ
エ・ブレイク・ダウンを生起させないようにする
スイツチング手段とを具備してなることを特徴と
する半導体不揮発性記憶装置。1. A source region and a drain region facing each other via a channel region, a floating gate formed on the channel region with an insulating film interposed therebetween, and a region in contact with the drain region and close to an end of the floating gate. is formed and has a conductivity type opposite to that of the drain region, and has a p-conductivity with the drain region.
A memory transistor comprising an impurity-introduced region that forms an n-junction; - A semiconductor nonvolatile memory device characterized by comprising: switching means that does not apply the predetermined potential during readout of the transistor to prevent avalanche breakdown from occurring.
JP9642179A 1979-06-18 1979-07-28 Semiconductor nonvolatile memory device Granted JPS5621375A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP9642179A JPS5621375A (en) 1979-07-28 1979-07-28 Semiconductor nonvolatile memory device
EP80302039A EP0021777B1 (en) 1979-06-18 1980-06-17 Semiconductor non-volatile memory device
DE8080302039T DE3065360D1 (en) 1979-06-18 1980-06-17 Semiconductor non-volatile memory device
CA000354232A CA1139880A (en) 1979-06-18 1980-06-18 Semiconductor non-volatile memory device
US06/526,219 US4491859A (en) 1979-06-18 1983-08-25 Semiconductor non-volatile memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9642179A JPS5621375A (en) 1979-07-28 1979-07-28 Semiconductor nonvolatile memory device

Publications (2)

Publication Number Publication Date
JPS5621375A JPS5621375A (en) 1981-02-27
JPS6335111B2 true JPS6335111B2 (en) 1988-07-13

Family

ID=14164509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9642179A Granted JPS5621375A (en) 1979-06-18 1979-07-28 Semiconductor nonvolatile memory device

Country Status (1)

Country Link
JP (1) JPS5621375A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0614843B2 (en) * 1988-08-26 1994-03-02 キッコーマン株式会社 Stabilization method of seafood or meat extract flavor
EP1178540B1 (en) 2000-07-31 2014-10-22 Micron Technology, Inc. Nonvolatile memory cell with high programming efficiency
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49118376A (en) * 1973-03-12 1974-11-12

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49118376A (en) * 1973-03-12 1974-11-12

Also Published As

Publication number Publication date
JPS5621375A (en) 1981-02-27

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