JPH0677491A - Semiconductor device - Google Patents

Abstract

PURPOSE:To write information at a low voltage and to enhance the charge holding performance of a device in a memory circuit constituted of a one- transistor/cell structure. CONSTITUTION:The gate structure of a memory cell is a structure in which a MONOS memory 2 is sandwiched between MOS transistors 45. Consequently, the transistors 45 function as selection transistors, and a memory circuit having a one-transistor/cell structure which does not cause an erroneous readout operation can be constituted. In the memory cell constituted in this manner, a silicon oxide film 13 formed on the surface of a silicon nitride film 11 dams up electrons and holes which tunnel through a silicon oxide film 9 and flows into a gate electrode 17 in an information write operation and an erasure operation, and it prevents that the electrons which have been once captured by the nitride film 11 are leaked to the electrode 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory device, and more particularly to a memory device having a trap type one transistor / cell structure.

[0002]

2. Description of the Related Art Generally, in a semiconductor memory device, a field effect transistor is used as a memory to form a memory circuit. In addition, in such a memory circuit configuration, a transistor for selecting a desired memory at the time of reading information is required in addition to the transistor serving as the storage means, and the memory circuit is configured with a two-transistor / cell structure.

With the development of the semiconductor industry, it has been desired to integrate a nonvolatile memory device, and it has been considered to construct a memory circuit with a one-transistor / cell structure (Japanese Patent Laid-Open No. 58-2).
1871). A memory cell having a one-transistor / cell structure will be described below. FIG. 8 is a schematic sectional view showing the memory cell.

As shown in FIG. 8, an N type drain layer 5 and a source layer 7 are provided in a P type silicon well layer 3 provided in a substrate (not shown). A gate oxide film 35 (thickness 1.5 to 3.0 is formed on the upper surface of the substrate near the center between the two layers.
nm) and silicon nitride film (SiN film) 33 (thickness 30 to 60 n
m) are stacked in this order to form the gate structure 43. A silicon oxide film 14 (thickness: 50 to 100 nm) is provided on both sides of the gate structure 43 on the upper surface of the substrate except where the gate structure 43 is formed.
Further, the silicon nitride film 33 and the silicon oxide film 14
A gate electrode 17 is formed on the upper surface of the. Considering a gate structure including the above-described gate structure 43 as an element, MNOS (Metal-Nitride-Oxide-) located in the central portion is considered.
Semicondactor type memory 1 is replaced with MOS (Metal-Oxide-Sem)
It is a structure sandwiched between (icondactor) type transistors 45.
The MNOS type memory 1 and the MOS type transistor 4
The threshold voltages of 5 are both adjusted to a positive value V1 (V1 <2 [v]).

The above MNOS type memory 1 has information "0".
Can be stored in two states, that is, a state in which electrons are trapped in the SiN film 33 and a state in which information "1" is stored (a state in which electrons are not trapped in the SiN film 33).
A storage device can be provided by utilizing this feature.

These two states will be described based on the hysteresis loop of the memory 1 shown in FIG. The horizontal axis of FIG. 9 represents the gate voltage Vg, and the vertical axis represents the threshold voltage Vth. The gate voltage Vg is a voltage applied to the gate electrode of the memory. The threshold voltage Vth is a gate voltage when a current flows between the source and the drain at a constant drain voltage when the voltage applied to the gate electrode is increased. The threshold voltage Vth is given by the following formula.

[0007]

[Equation 1]

When writing information "0" to the memory 1, a write programming voltage of about 10 V is applied to the gate electrode 17 of the memory 1. At this time, an electric field generated between the gate electrode 17 and the channel region 15 causes electrons in the channel region 15 to have high energy, and some electrons tunnel through the silicon oxide film 35.
It enters into the SiN film 33 and is trapped. Due to such a change, the threshold voltage VQ1 rises to about 3V (see Q1 in FIG. 9). That is, the memory 1 operates as an enhancement type transistor having a threshold voltage of 3V. That is, this state is a state in which the information "0" is written in the memory 1. The threshold voltage remains unchanged even when the gate voltage is cut off (see R1 in FIG. 9).

Next, in order to erase the information "0", it is necessary to return the trapped electrons to the channel region 15. Therefore, a voltage of about 10 V is applied to the channel region 15 to generate an electric field in the direction opposite to that at the time of writing information, and electrons are returned to the channel region 15. Further, the holes in the channel region 15 are trapped by tunneling through the silicon oxide film 35. Due to such a change, the threshold voltage VQ1 of about 3V is changed to the threshold voltage VS of about -1V.
It changes to 1 (see S1 in FIG. 9). That is, the memory 1
Operates as a depletion type transistor having a threshold voltage of -1V. This state in which the information "0" is erased means that the memory 1 stores the information "1".
Even if the gate voltage is cut off, the threshold voltage remains unchanged (see T1 in FIG. 9). In reading information, when a sense voltage Vdd intermediate between the voltage V1 and the voltage VQ1 is applied to the gate electrode 17 and a read voltage Vm of about 2V is applied between the drain layer 5 and the source layer 7 of the memory, the channel region is formed. Whether or not information "0" is stored or information "1" is stored is determined depending on whether or not a current flows through 15.

That is, when the information "0" is stored, the sense voltage Vdd applied to the gate electrode 17 is smaller than the threshold voltage VQ1 (about 3 [v]) of the memory 1, but it is on both sides of the memory 1. It is higher than the threshold voltage V1 of the MOS type transistors 45 provided so as to be adjacent to each other. Therefore, the channel regions 23 and 27 are conductive, but the channel region 25 is not conductive. That is, the channel area 1
No current flows through 5. On the other hand, when the information “1” is stored, the sense voltage Vd applied to the gate electrode 17
d is larger than both the threshold voltage VS1 (about −1 [v]) of the memory 1 and the threshold voltage V1 of the MOS transistor 45.
Therefore, the channel regions 23, 27 and 25 are all in the conductive state. That is, a current flows through the channel region 15.

The above memory cells are arranged in a matrix,
A gate line for connecting the gate electrodes 17 of all the memory cells in each row is provided for each row, and a drain side line for connecting the drain layers 5 and a source side line for connecting the source layers 7 of all the memory cells in each column are provided respectively. Provide for each row. By configuring the memory circuit as described above,
Information can be written, read, and collectively erased accurately.

[0012]

However, the conventional nonvolatile memory device using the memory cell has the following problems.

With the development of the semiconductor industry, miniaturization and integration of nonvolatile semiconductor memory devices are required.
In order to meet the demand, it is desired to lower the write programming voltage. In the MNOS type memory, generally, the thinning of the nitride film is performed for the purpose of a low write programming voltage. This is because, in order to write information, it is necessary to apply an electric field to the gate oxide film so that electrons can tunnel through the gate oxide film, but the division ratio of the write programming voltage applied to the oxide film is equal to that of the nitride film. It rises as it becomes thinner. Therefore, by thinning the nitride film, the minimum electric field strength necessary for writing information can be obtained with a lower write programming voltage.

However, in the conventional memory cell, the silicon nitride film 33 could not be made thinner. This is because if the silicon nitride film 33 is made too thin, the electrons tunneling through the silicon oxide film 35 will not be trapped in the silicon nitride film 33 and will not be trapped in the gate electrode 1.
The reason is that it will fall to 7.

Further, due to the thinning of the silicon nitride film 33, holes tunneling through the silicon oxide film 35 are not trapped in the silicon nitride film 33 but escape to the gate electrode 17 even when erasing information, and the information is erased. Was sometimes incomplete.

On the other hand, when this memory device is used for a long period of time, in the memory cell storing the information "0", the nitride film 33 is formed.
The electrons trapped in the gate may leak to the gate electrode 17. In an extreme case, since the threshold potential in the information writing state is lowered, erroneous reading may occur during information reading. It has been a problem in terms of long term reliability of the device.

Further, holes may be generated in the gate electrode 17, but at this time, the holes sometimes reach the silicon oxide film 35 through the silicon nitride film 33. The holes may collide with the silicon oxide film 35 to deteriorate the silicon oxide film 35. If the deterioration of the silicon oxide film 35 proceeds, there is a high possibility that the trapped electrons will return to the channel region 15.
In this case, erroneous reading may occur at the time of reading information because the threshold potential in the information writing state is lowered as in the above case. It has been a problem in terms of long term reliability of the device.

Therefore, the present invention solves the above problems, and in a memory matrix circuit having a one-transistor / cell structure, information can be written at a low voltage and the charge retention performance is excellent. Another object of the present invention is to provide a nonvolatile memory device.

[0019]

According to another aspect of the present invention, there is provided a semiconductor device having a first conductivity type semiconductor substrate and at least a pair of second conductivity type diffusion regions formed in the semiconductor substrate.
A first insulating film provided on a part of the semiconductor substrate between a pair of diffusion regions, and a part of the semiconductor substrate between a pair of diffusion regions adjacent to the first insulating film. A second insulating film, a third insulating film for holding charges provided on the first insulating film, a fourth insulating film provided on the third insulating film, the second insulating film, and And a control electrode provided on the third insulating film.

A semiconductor device according to a second aspect is the semiconductor device according to the first aspect, wherein at least the pair of diffusion layers are a source layer and a drain layer, and the control electrode is a memory gate electrode.

According to a third aspect of the present invention, there is provided a method of using the semiconductor device according to the second aspect, in which the memory cells having the structure according to the second aspect are arranged in a matrix and the memory gate electrodes of the memory cells arranged in the same row are arranged. A word line to be connected is provided for each row, a drain side line for connecting the drains of the memory cells arranged in the same column is provided for each column, and a source side line for connecting the sources of the memory cells arranged in the same column is provided. Provided for each column, when writing information, the write programming voltage is applied to the word line that connects the memory gate electrode of the memory cell you want to write, and the drain side that connects the drain of the memory cell you want to write Apply programming inhibit voltage to all drain side lines except lines, and when reading information, read desired memory cell The read voltage is applied to the drain side line connecting the drain layer of the read desired memory cell to apply a sense voltage to the memory gate electrode,
It is characterized by detecting whether or not a current flows between the drain and the source of the memory cell desired to be read.

A method of manufacturing a semiconductor device according to a fourth aspect is
A step of laminating a first insulating film, a third insulating film for holding charge, and a fourth insulating film in this order on the entire surface of the first conductivity type semiconductor substrate,
A gate stack including a first insulating film, a third insulating film, and a fourth insulating film, by selectively removing the first insulating film, the third insulating film, and the fourth insulating film formed on the semiconductor substrate. And a step of forming a second insulating film on the upper surface of the substrate around the gate stack by oxidizing the surface of the substrate, and a memory gate electrode on the upper surface of the gate stack and the second insulating film. Forming step and using the memory gate electrode as a mask, implanting and diffusing second conductivity type impurities,
And a step of forming a pair of second conductivity type diffusion regions.

[0023]

In the semiconductor device and the method of manufacturing the same according to claims 1, 2, and 4, the fourth insulating film provided between the third insulating film for holding charges and the control electrode is used for writing information. The electrons that tunnel through the first insulating film and try to flow into the control electrode are stopped. Further, at the time of erasing information, the first insulating film is tunneled to block the holes that try to flow into the control electrode.

Further, the fourth insulating film prevents the electrons captured by the third insulating film from leaking to the control electrode. Further, the fourth insulating film prevents holes generated from the control electrode from reaching the first insulating film.

In the method of using the semiconductor device according to the third aspect, the memory cells having the structure according to the second aspect are arranged in a matrix, and the word line connecting the memory gate electrodes of the memory cells arranged in the same row is formed. A drain-side line that connects the drains of the memory cells arranged in the same column is provided for each column, and a source-side line that connects the sources of the memory cells arranged in the same column is provided for each column , When writing information, apply the write programming voltage to the word line that connects the memory gate electrode of the memory cell you want to write, and all except the drain side line that connects the drain of the memory cell you want to write. Applying a programming inhibit voltage to the drain side line, and when reading information, the memory gate of the memory cell you want to read It is possible to detect whether or not a current flows between the drain and source of the desired memory cell to be read by applying a sense voltage to the electrodes and applying a read voltage to the drain side line connecting the drain layer of the desired memory cell to be read. It has a feature.

Therefore, erroneous writing and erroneous reading are prevented in a semiconductor device having a one-transistor / cell structure.

[0027]

EXAMPLE A memory cell of a nonvolatile memory device according to an example of the present invention will be described below. FIG. 1 shows a schematic sectional view of the memory cell.

In the P-type silicon well layer 3 which is a semiconductor region of the first conductivity type provided on the substrate (not shown), the N-type drain layers 5 and N which are a pair of diffusion regions of the second conductivity type.
Shaped source layer 7 is provided. On the surface of the substrate, a silicon oxide film 9 (thickness: about 2 nm) which is a first insulating film is formed in the central portion between the drain layer 5 and the source layer 7, and a silicon nitride (SiN) which is a third insulating film for holding charges. Membrane 11 (thickness 10 nm
Degree), the silicon oxide film 13 (thickness 5
(about nm) are stacked in this order to form the gate stacked body 12. A silicon oxide film 14 (having a thickness of about 40 nm) as a second insulating film is provided on both sides of the gate stacked body 12 so as to reach the drain layer 5 and the source layer 7. A polysilicon film 17, which is a control electrode, is formed on the upper surfaces of the silicon oxide film 13 and the silicon oxide film 14.
The control electrode is formed so that the region between the drain layer 5 and the source layer 7 (hereinafter referred to as the channel region 15) can be controlled. Further, in the channel region 15, the portions located below the silicon oxide film 14 are referred to as channel regions 23 and 27, respectively, and the portions located below the gate stacked body 12 are referred to as channel regions 25.

In the above memory cell, considering the gate structure including the gate stack 12 as an element, M0NOS (Metal-Oxide-Nitrid) located at the center of the gate structure is considered.
e-Oxide-Semicondactor) type memory 2 is replaced with MOS (Metal-O)
It is a structure sandwiched between xide-Semicondactor) type transistors 45. The threshold voltage and the MOS of the MONOS type memory
Type transistor 45 has a positive threshold voltage V2 (V2 <3
[v]). That is, it works as an enhancement type transistor.

The MONOS type memory 2 has the information "
There are two possible modes: a state in which 0 "is stored (a state in which electrons are trapped in the SiN film 11) and a state in which information" 1 "is stored (a state in which electrons are not trapped in the SiN film 11). A storage device can be provided by utilizing the characteristics.

These two states will be described based on the hysteresis loop of the memory 2 shown in FIG. Information in memory 2 "
When writing "0", a programming voltage VP1 of about 6 V is applied to the gate electrode 17 of the memory 2. At this time, the electrons in the channel region 15 are high due to the electric field generated between the gate electrode 17 and the channel region 15. It becomes to have energy, some electrons tunnel through the silicon oxide film 9 and flow into the SiN film 11, and the SiN film 1
Move in 1. The moving electrons are stopped by the silicon oxide film 13 which acts as a barrier. Therefore, the electrons are trapped in the SiN film 11 without passing through the gate electrode 17. With such a change, the threshold voltage VQ2 rises to about 3V (see Q2 in FIG. 3). That is, the memory 2 comes to function as an enhancement type transistor having a threshold voltage of 3V. That is, this state is the state in which the information "0" is written in the memory 2.
The threshold voltage remains unchanged even when the gate voltage is cut off (see R2 in FIG. 3).

Next, in order to erase the information "0", it is necessary to return the trapped electrons to the channel region 15. Therefore, a programming voltage VP2 of about 6 V is applied to the channel region 15 to generate an electric field in the direction opposite to that at the time of writing information, and electrons are returned to the channel region 15. At the same time, due to this electric field, the channel region 15
Holes tunnel through the silicon oxide film 9 and, like the electrons described above, do not escape to the gate electrode 17 and the SiN film 11
Trapped inside. With such a change, the threshold voltage of about 3V changes to the threshold voltage VS2 of about -1V (FIG. 3).
See S2). That is, the memory 2 comes to function as a depletion type transistor having a threshold voltage of -1V. This state in which the information "0" is erased means that the memory 1 stores the information "1". Even if the gate voltage is cut off, the threshold voltage remains unchanged (see T2 in FIG. 3).

In reading information, the gate electrode 1
Whether a current flows through the channel region 15 when a sense voltage Vdd intermediate between the voltage V2 and the voltage VQ2 is applied to 7 and a constant read voltage Vm between the drain layer 5 and the source layer 7 of the memory is applied. , It is determined whether the information “0” is stored or the information “1” is stored.

More specifically, when the information "0" is stored, the sense voltage V applied to the gate electrode 17
dd is lower than the threshold voltage VQ2 (about 3 [v]) of the memory 2, but higher than the threshold voltage V2 of the MOS transistor 45 provided adjacent to both sides of the memory 2. Therefore,
The channel regions 23 and 27 are conductive, but the channel region 25 is not conductive. That is, no current flows in the channel region 15.

On the other hand, when the information "1" is stored, the sense voltage Vdd applied to the gate electrode 17 is the threshold voltage VS2 (about -1 [v]) of the memory 2 and the threshold voltage of the MOS transistor 45. Greater than either V2. Therefore, the channel regions 23, 27 and 25 are all in the conductive state. That is, a current flows through the channel region 15.

A non-volatile memory device according to an embodiment of the present invention has the above memory cells arranged in a matrix and has a one-transistor / cell structure. For example, 4
FIG. 2 is a conceptual diagram of a memory circuit composed of one memory cell.
Shown in. The configuration of the memory circuit will be described below with reference to FIG.

Gate electrode 17 of memory cells 2A and 2B
Is connected to the word line W1, and the word line W2 is connected to the gate electrodes 17 of the memory cells 2C and 2D. The drain side line D1 is connected to the drain layers 5 of the memory cells 2A and 2C, and the drain side line D2 is connected to the drain layers 5 of the memory cells 2B and 2D. Further, the source side line S1 is connected to the source layer 7 of the memory cells 2A and 2C, and the source side line S2 is connected to the source layer 7 of the memory cells 2B and 2D. In addition, the well line WEL is formed in the well layer 3 of each memory cell.
Are connected.

Next, FIG. 4 shows potential states of the word line, the drain side line, the source side line and the well line at the time of writing, reading and erasing information. First, the case of writing information in a desired memory cell will be described with reference to FIGS.

For example, by selecting the memory cell 2A, information "
When writing "0", the row decoder 19 writes a write programming voltage VP1 of about 6V into the word line W1.
And a programming inhibit voltage Vi of about 4V is applied to the drain side line D2. The source side lines S1 and S2 are opened, and the word line W2, the drain side line D1 and the well line WEL are grounded.

At this time, in the selected memory cell 2A, since the programming voltage VP1 is applied to the gate electrode 17, electrons are generated in the silicon nitride film 11 by the electric field generated between the well layer 3 and the gate electrode 17 as described above. To be trapped. In this state, the memory cell 2A stores the information "0".

On the other hand, the memory 2B which is a non-selected memory cell
Then, although the programming voltage VP1 is applied to the gate electrode 17, the programming inhibit voltage V is applied to the drain layer 5.
Since i is applied, the electric field necessary for writing information is not generated. Further, in the other non-selected memory cells, that is, the memory cells 2C and 2D, the write programming voltage is not applied to the gate electrode 17, and no electric field is generated. That is, no information is written.

Next, reading of information from a desired memory cell will be described with reference to FIGS. For example, when the memory cell 2A is selected and information is read, the row decoder 19 applies the sense voltage Vdd of about 2V to the word line W1 and the read voltage Vm of about 2V to the drain side line D1. Done. The drain side line D2 and the source side line S2 are opened, and the word line W2, the source side line S1 and the well line WEL are grounded.

At this time, the selected memory cell 2A has information "0".
Is stored (electrons are trapped in the silicon nitride film)
In the case of the state, since the sense voltage Vdd is applied to the gate electrode 17, the channel regions 23 and 27 are in the conductive state as described above, but the channel region 25 is not in the conductive state. That is, the channel region 15 is not conductive as a whole. In the non-selected memory cell 2C connected to the drain side line D1, the channel region 15 is not conductive regardless of the type of information stored because the sense voltage Vdd is not applied to the gate electrode 17. Therefore, the current flowing through the drain side line D1 is
It is not leaked to A, and is directly input to the column decoder 21.

On the other hand, the memory cell 2A stores information "1" (electrons are not trapped in the silicon nitride film).
In the case of the state, since the sense voltage Vdd is applied to the gate electrode 17, as described above, the channel region 23,
25 and 27 are all in a conductive state. That is, the channel region 15 is in the conductive state. Further, the non-selected memory cell 2D is not in the conductive state for the same reason as above. Therefore, the current flowing through the drain side line D1 flows through the channel region 15 of the memory cell 2A and drops to the ground potential through the source side line S1. That is, no current is input to the column decoder 21. The unselected memory cells 2B and 2B
A read voltage Vm is applied to the drain side line connecting D
Is not applied. In this way, the column decoder 2
Information is identified and read depending on whether or not a current is input to the unit 1.

Finally, the information "on the basis of FIGS. 2 and 4"
A case of erasing "0" for each word line will be described. For example, the memory cell 2A connected to the word line W1.
When erasing the information "0" of 2B and 2B, a programming voltage VP2 of about -6V is applied to the word line W1,
This is performed by grounding the well layer 3. The drain side lines D1 and D2 and the source side lines S1 and S
2 is opened and the word line W2 is grounded.

At this time, since the programming voltage VP2 is applied to the gate electrode 17 in the memory cells 2A and 2B, the time "0" is written in the information "0" generated between the well layer 3 and the gate electrode 17 as described above. The electrons trapped in the silicon nitride film 11 by the electric field in the opposite direction return to the well layer 3. This state is the erased state of the memory cell, that is, the state in which the information "1" is stored. In the memory cells 2C and 2D connected to the word line W2, the electric field is not generated because the programming voltage VP2 is not applied to the gate electrode, and information is not erased.

Next, a method of manufacturing this memory circuit will be described focusing on the memory cell portion. 5, 6 and 7 are views for explaining the manufacturing process.

An N-type silicon substrate 4 (thickness 2-5 Ωcm) having an orientation (100) is prepared, and boron (B ⁺ ) is implanted and diffused from the upper surface to form a P-type well layer 3 (FIG. 5A). Next, an element isolation region is formed by the field oxide film 6 by the LOCOS method (FIG. 5B). Next, a silicon oxide film 9 (thickness: about 2 nm), a silicon nitride film 11 (thickness: 10 nm), and a silicon oxide film 13 are formed on the substrate.
(Thickness of about 5 nm) is deposited in this order (FIG. 5C).

Next, the above-mentioned laminated portion is selectively cut by patterning a mask to form a gate laminated body 12 in which the silicon nitride film 11 is sandwiched between the silicon oxide films 9 and 13 (FIG. 6A). Next, the silicon surface is oxidized by thermal oxidation to form a silicon oxide film 14 having a thickness of about 40 nm on both sides of the gate stacked body 12 (FIG. 6B).

Next, a gate electrode 17 is formed so as to reach the gate stacked body 12 and a part of the silicon oxide film 14 on both sides of the upper surface thereof (FIG. 6C). Next, using the gate electrode 17 as a mask, N-type impurities such as arsenic are implanted and diffused to form the N ⁺ drain layer 5 and the N ⁺ source layer 7 (FIG. 7A). Next, an interlayer insulating film 29 such as a silicon oxide film is grown, and required contact holes are formed in the interlayer insulating film 29. Further, the metal wiring of each electrode is formed by using the metal layer 31 such as Al-Si.

In the manufacturing method according to the present invention, as described above, the silicon oxide film 9 (thickness: about 2 nm) and the silicon nitride film 1 are formed.
1 (thickness about 10 nm), silicon oxide film 13 (thickness 5
It is characterized in that the silicon oxide film 14 having a thickness of about 40 nm, which is the second insulating film, is formed by thermal oxidation from the surface of the substrate after forming the gate stacked body 12 composed of about 2 nm). Therefore, at this time, the gate stack 1
It is possible to form the silicon oxide film 14 having a film thickness of about 40 nm on the upper surface of the silicon substrate 4 while keeping the film thickness of the uppermost silicon oxide film 13 of 2 at about 5 nm. In addition,
Although the film thickness of the silicon oxide film 13 is slightly grown by this thermal oxidation, it is advisable to set the film thickness of the silicon oxide film 13 in consideration of such a growth amount in advance.

Although the first conductivity type is P type and the second conductivity type is N type in the above embodiment, the first conductivity type may be P type and the second conductivity type may be N type.

[0053]

According to the semiconductor device and the method of manufacturing the same according to claims 1, 2, and 4, the fourth insulating film provided between the third insulating film for holding charges and the control electrode is made of information. At the time of writing, the first insulating film is tunneled to stop the electrons that try to flow into the control electrode. Further, at the time of erasing information, the first insulating film is tunneled to block the holes that try to flow into the control electrode.

Therefore, it is possible to reduce the film thickness of the third insulating film for holding electric charges, and it is possible to reduce the write voltage and the erase voltage.

Further, the fourth insulating film prevents the electrons trapped in the third insulating film from leaking to the control electrode.

Therefore, the charge retention performance of the semiconductor device is improved.

Further, the fourth insulating film prevents holes generated from the control electrode from reaching the first insulating film.

Therefore, deterioration of the first insulating film due to damage of the first insulating film due to holes is prevented. Therefore, return of trapped electrons into the substrate due to deterioration of the first insulating film is prevented. That is, the charge retention performance of the semiconductor device is improved.

In the method of using the semiconductor device according to the third aspect, the memory cells having the structure according to the second aspect are arranged in a matrix, and the word lines connecting the memory gate electrodes of the memory cells arranged in the same row are formed. A drain-side line that connects the drains of the memory cells arranged in the same column is provided for each column, and a source-side line that connects the sources of the memory cells arranged in the same column is provided for each column , When writing information, apply the write programming voltage to the word line that connects the memory gate electrode of the memory cell you want to write, and all except the drain side line that connects the drain of the memory cell you want to write. Applying a programming inhibit voltage to the drain side line, and when reading information, the memory gate of the memory cell you want to read It is possible to detect whether or not a current flows between the drain and the source of the desired memory cell to be read by applying a sense voltage to the electrodes and applying a read voltage to the drain side line connecting the drain layer of the desired memory cell to be read. It has a feature. Therefore, erroneous writing and erroneous reading are prevented in the semiconductor device having the one-transistor / cell structure.

Therefore, it is possible to provide a semiconductor device having a one-transistor / cell structure and improve the degree of integration of the device.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of a memory cell according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a memory circuit according to an embodiment of the present invention.

FIG. 3 is a diagram showing a hysteresis loop of a threshold potential of the memory 2 according to the embodiment of the present invention.

FIG. 4 is a diagram showing a potential state of each wiring line at the time of writing, reading, and erasing information.

FIG. 5 is a diagram showing a manufacturing process of the memory circuit according to the embodiment of the present invention.

FIG. 6 is a diagram showing a manufacturing process of a memory circuit according to an embodiment of the present invention.

FIG. 7 is a diagram showing a manufacturing process of the memory circuit according to the embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view of a conventional memory cell.

FIG. 9 is a diagram showing a hysteresis loop of the threshold potential of the conventional memory 2.

[Explanation of symbols]

 3 ... P-type well layer 5 ... N-type drain layer 7 ... N-type source layer 9 ... Silicon oxide film 11 ... Silicon nitride film 12 ... Gate laminated body 13 ... Silicon Oxide film 14 ... Silicon oxide film 17 ... Polysilicon film W1, W2 ... Word line D1, D2 ... Drain side line S1, S2 ... Source side line

Claims (4)

[Claims] 1. A semiconductor region of a first conductivity type, at least a pair of diffusion regions of a second conductivity type formed in the semiconductor region, and a part of the semiconductor region provided between the pair of diffusion regions. A first insulating film, a second insulating film provided between the pair of diffusion regions on the semiconductor region so as to be adjacent to the first insulating film, and a charge retention film provided on the first insulating film. A third insulating film, a fourth insulating film provided on the third insulating film, and a control electrode provided on the second insulating film and the fourth insulating film. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the pair of diffusion layers are a source layer and a drain layer, and the control electrode is a memory gate electrode. 3. The memory cells having the structure according to claim 2 are arranged in a matrix, and word lines for connecting the memory gate electrodes of the memory cells arranged in the same row are provided for each row and arranged in the same column. A drain side line connecting the drains of the memory cells arranged in each column is provided for each column, and a source side line connecting the sources of the memory cells arranged in the same column is provided for each column. The programming programming voltage is applied to the word line connecting the memory gate electrode of the desired memory cell, and the programming inhibiting voltage is applied to all drain side lines except the drain side line connecting the drain of the desired memory cell. To read information, apply a sense voltage to the memory gate electrode of the memory cell you want to read. A read voltage is applied to the drain side line connecting the drain layer of the memory cell desired to be read, and whether or not a current flows between the drain and source of the memory cell desired to be read is detected. how to use. 4. A step of laminating a first insulating film, a third insulating film for holding a charge, and a fourth insulating film in this order on the entire surface of the first conductivity type semiconductor substrate, and a first film formed on the semiconductor substrate. A step of selectively removing the insulating film, the third insulating film and the fourth insulating film to form a gate laminated body composed of the first insulating film, the third insulating film and the fourth insulating film; Forming a second insulating film on the upper surface of the substrate around the gate stack by oxidation, forming a memory gate electrode on the upper surface of the gate stack and the second insulating film, and forming the memory gate electrode And a step of implanting and diffusing a second conductivity type impurity to form a pair of second conductivity type diffusion regions, using the mask as a mask.