KR910001765A - Nonvolatile memory device - Google Patents

Nonvolatile memory device Download PDF

Info

Publication number
KR910001765A
KR910001765A KR1019890009305A KR890009305A KR910001765A KR 910001765 A KR910001765 A KR 910001765A KR 1019890009305 A KR1019890009305 A KR 1019890009305A KR 890009305 A KR890009305 A KR 890009305A KR 910001765 A KR910001765 A KR 910001765A
Authority
KR
South Korea
Prior art keywords
region
electrode
gate electrodes
memory device
nonvolatile memory
Prior art date
Application number
KR1019890009305A
Other languages
Korean (ko)
Other versions
KR920009668B1 (en
Inventor
구니요시 요시카와
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR910001765A publication Critical patent/KR910001765A/en
Application granted granted Critical
Publication of KR920009668B1 publication Critical patent/KR920009668B1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors

Abstract

내용 없음No content

Description

불휘발성메모리 장치Nonvolatile memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 제1실시예에 관한 불휘발성메모리장치에 대해 설명하는 단면도1 is a cross-sectional view for explaining a nonvolatile memory device in accordance with the first embodiment of the present invention.

제2도는 본 발명의 제2실시예에 관한 불휘발성메모리장치에 대해 설명하는 단면도2 is a cross-sectional view for explaining a nonvolatile memory device in accordance with a second embodiment of the present invention.

Claims (6)

반도체기판(1)의 표면영역에 형성된 제1영역(소오스확산층:2) 및 제2영역(드레인확산층:3a,3b)과, 이 제1영역(2) 및 제2영역(3a,3b)사이의 챈널영역상에 형성되어 전기적으로 부유상태로 되는 제1게이트전극(부유게이트전극:5a,5b), 이 제1게이트전극(5a,5b)상에 제1절연막을 매개해서 형성되어 제어게이트로 기능하는 제2게이트전극(9a,9b)을 갖춘 트랜지스터를 메모리셀로서 사용하는 불휘발성메모리 장치에 있어서, 상기 제1게이트전극(5a,5b)의 측벽에 형성된 제2절연막(터널산화막:6a,6b)과, 이 제2절연막(6a,6b)을 상기 제1게이트전극(5a,5b)과 사이에 두고서 형성되어 상기 제1영역(2) 또는 제2영역(3a,3b)중 어느 한쪽에 전기적으로 접속되는 제3전극(소거게이트전극:7)이 설치되어 구성된 것을 특징으로 하는 불휘발성메모리장치.Between the first region (source diffusion layer: 2) and the second region (drain diffusion layers: 3a, 3b) formed in the surface region of the semiconductor substrate 1, and between the first region 2 and the second region 3a, 3b. A first gate electrode (floating gate electrodes 5a, 5b) formed on the channel region of the substrate to be electrically floating, and formed on the first gate electrodes 5a, 5b via a first insulating film to form a control gate. In a nonvolatile memory device using a transistor having functioning second gate electrodes 9a and 9b as a memory cell, a second insulating film (tunnel oxide film: 6a) formed on sidewalls of the first gate electrodes 5a and 5b. 6b and the second insulating films 6a and 6b are formed between the first gate electrodes 5a and 5b so as to be disposed on either the first region 2 or the second region 3a or 3b. A nonvolatile memory device, characterized in that a third electrode (erasure gate electrode) 7 is electrically connected. 제1항에 있어서, 상기 제3전극(소거게이트전극:7)에 필요한 전위를 공급해서 상기 제1게이트전극(부유게이트전극:5a,5b)에 축적된 전하를 상기 제2절연막(6a,6b)을 매개해서 상기 제3전극(7)으로 방출시킴으로써 전기적으로 기록의 교환을 수행하도록 된 것을 특징으로 하는 불휘발성 메모리장치.2. The electric charge of the first gate electrode (the floating gate electrodes 5a and 5b) by supplying a potential required to the third electrode (the erase gate electrode 7) is transferred to the second insulating layer 6a and 6b. And (b) electrically discharging the writes to the third electrode (7). 제1항에 있어서, 상기 제2절연막(터널산화막:6a,6b)은 다결정실리콘산화막에 의해 형성된 것을 특징으로 하는 불휘발성메모리장치.The nonvolatile memory device according to claim 1, wherein the second insulating film (tunnel oxide film: 6a, 6b) is formed of a polycrystalline silicon oxide film. 반도체기판(101)의 표면영역에 형성된 제1영역(드레인 확산층:102) 및 제2영역(소오스확산층:103a,103b)과, 이 제1영역(102) 및 제2영역(103a,103b)사이에서의 제1영역(102)에 접하는 챈널영역상에 형성되어 전기적인 부유상태로 되는 제1게이트전극(부유게이트전극:105a,105b), 이 제1게이트전극(105a,105b)상에 형성된 제1절연막과 제2영역(103a,103b)에 접하는 챈널영역상에 위치되는 기판절연막에 형성되어 제어게이트로 작용하는 제2게이트전극(제어게이트전극;9a,9b)을 갖춘 트랜지스터를 메모리셀로서 사용하는 불휘발성메모리 장치에 있어서, 상기 제1게이트전극(105a,105b)에 대한 제1영역(102)측의 측벽에 형성된 제2절연막(터널산화막:106a,106b)과 이 제2절연막(106a,106b)을 상기 제1게이트전극(5a,5b)과 사이에 두고서 형성되어 상기 제1영역(102)에 전기적으로 접속되는 제3전극(소거게이트전극:107)이 설치된 것을 특징으로 하는 불휘발성메모리장치.Between the first region (drain diffusion layer: 102) and the second region (source diffusion layer: 103a, 103b) formed in the surface region of the semiconductor substrate 101, and between the first region 102 and the second region 103a, 103b. A first gate electrode (floating gate electrodes 105a and 105b) formed on a channel region in contact with the first region 102 in U. S. and formed in an electrically floating state, and formed on the first gate electrodes 105a and 105b. A transistor having a second gate electrode (control gate electrode 9a, 9b) formed in a substrate insulating film positioned on a channel region in contact with the insulating film and the second regions 103a and 103b and serving as a control gate is used as a memory cell. In the nonvolatile memory device, a second insulating film (tunnel oxide film: 106a, 106b) formed on a sidewall of the side of the first region 102 with respect to the first gate electrodes 105a, 105b and the second insulating film 106a, A third electrode formed between the first gate electrodes 5a and 5b and electrically connected to the first region 102. A nonvolatile memory device, characterized in that an erase gate electrode is provided. 제4항에 있어서, 상기 제3전극(소거게이트전극:107)에 필요한 전위를 공급해서 상기 제1게이트전극(부유게이트전극:105a,105b)에 축적된 전하를 상기 제2절연막(터널산화막:106a,106b)을 매개해서 상기 제3전극(107)으로 방출시킴으로써 전기적으로 기록의 교환을 수행하도록 된 것을 특징으로 하는 불휘발성메모리장치.The second insulating film (tunnel oxide film) according to claim 4, wherein charges accumulated in the first gate electrode (floating gate electrodes 105a and 105b) are supplied to the third electrode (erasure gate electrode: 107). A nonvolatile memory device, characterized in that electrical exchange of records is carried out by discharging to the third electrode (107) via 106a, 106b. 제4항에 있어서, 상기 제2절연막(터널산화막:106a,106b)은 다결정실리콘산화막에 의해 형성된 것을 특징으로 하는 불휘발성메모리장치.5. The nonvolatile memory device according to claim 4, wherein the second insulating films (tunnel oxide films: 106a and 106b) are formed of polycrystalline silicon oxide films. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임※ Note: The disclosure is based on the initial application.
KR1019890009305A 1988-06-30 1989-06-30 Nonvolatile memory system KR920009668B1 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP63-160826 1988-06-30
JP88-160826 1988-06-30
JP16082688 1988-06-30
JP89-95213 1989-04-17
JP1-95213 1989-04-17
JP1095213A JPH0277169A (en) 1988-06-30 1989-04-17 Nonvolatile memory device

Publications (2)

Publication Number Publication Date
KR910001765A true KR910001765A (en) 1991-01-31
KR920009668B1 KR920009668B1 (en) 1992-10-22

Family

ID=26436482

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890009305A KR920009668B1 (en) 1988-06-30 1989-06-30 Nonvolatile memory system

Country Status (2)

Country Link
JP (1) JPH0277169A (en)
KR (1) KR920009668B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5343063A (en) * 1990-12-18 1994-08-30 Sundisk Corporation Dense vertical programmable read only memory cell structure and processes for making them
JP2914252B2 (en) * 1995-10-14 1999-06-28 日本電気株式会社 Method of manufacturing nonvolatile semiconductor memory device

Also Published As

Publication number Publication date
KR920009668B1 (en) 1992-10-22
JPH0277169A (en) 1990-03-16

Similar Documents

Publication Publication Date Title
TW430997B (en) Nonvolatile semiconductor memory device and method for driving the same
KR900010794A (en) Nonvolatile Semiconductor Memory
JPH0368542B2 (en)
KR940022872A (en) Semiconductor storage device capable of electrically erasing and writing information
EP0616334A4 (en) Non-volatile semiconductor memory device having floating gate.
KR950015763A (en) Nonvolatile Semiconductor Memory
US4084108A (en) Integrated circuit device
KR880011929A (en) Semiconductor memory
KR940005898B1 (en) Nonvolatile semiconductor device
JPH0465879A (en) Nonvolatile semiconductor storage device
JP2580752B2 (en) Nonvolatile semiconductor memory device
KR910001765A (en) Nonvolatile memory device
KR880011808A (en) Nonvolatile Semiconductor Memory
KR960015965A (en) Semiconductor Nonvolatile Memory Cell with Floating Gate Electrode
KR880011928A (en) Semiconductor memory
JPS5787177A (en) Semiconductor memory device
JPS63199464A (en) Non-volatile semiconductor memory device
KR910020897A (en) Nonvolatile Semiconductor Memory
EP1014448A3 (en) Nonvolatile semiconductor memory device and method of manufacturing the same
JPS5939910B2 (en) Fukihatsu Seiki Oxoshi
JPS6335111B2 (en)
KR940006142A (en) Nonvolatile Semiconductor Memory
JPS59135B2 (en) semiconductor storage device
JPS61161769A (en) Insulated gate type non-volatile semiconductor memory device
JPS57162371A (en) Mos semiconductor memory device

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080926

Year of fee payment: 17

EXPY Expiration of term