JPS6351666A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To provide a higher integration and to prevent a soft error from being caused by such radioactive particles as alpha-particles by a method wherein a second conductivity type third semiconductor region, which comes into contact to a first conductivity type second semiconductor region, is formed in a semiconductor film on an insulator film and is connected to a bit line, is provided and a capacity connected to a first semiconductor region is so contrived as to be included. CONSTITUTION:Storage nodes and a N-type region 104 constituting the current-flow electrode on one side of a MOSFET are completely surrounded with an insulator excluding a place where the region 104 comes into contact with a P-type region 105. Therefore, the insulation between the storage nodes of a plurality of neighboring memory cells is easy. Moreover, in the N-type region, as the region 104 and the P-type region 105, which is a part coming into contact to the region 104, are a thin Si film surrounded with an insulator, the number of minority carriers to generate by the incidence of such radioactive particles as alpha-particles in this part is very small. As a N-type region 106 connected to a bit line is also completely surrounded with an insulator excluding places where the region 106 comes into contact with the P-type region 105 and a conductor film 110, the number of minority carriers to be generated by the incidence of such radioactive particles as alpha-particles in these parts is very small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor memory cell that is suitable for high integration and less likely to generate soft errors caused by radioactive particles such as α particles.

[Conventional technology 1 A memory cell (hereinafter abbreviated as ITIC cell) consisting of one transistor and one capacitor as a memory cell for highly integrated semiconductor memory has a small number of constituent elements, and the memory cell area can be easily miniaturized. Therefore, it is widely used.

The output voltage from the 1T1C cell is determined by the capacitance (
Since it is proportional to the cell capacity (hereinafter referred to as cell capacity), in order to guarantee stable operation even with high integration, it is necessary to increase the cell capacity by . In order to further increase integration, it is necessary to reduce the area of the memory cell itself. Therefore, in order to highly integrate a 1T1C cell, a cell capacitor with a small area and a sufficient capacitance value is required. Conventionally, as such cell capacitors, capacitors formed in grooves and capacitors with a laminated structure have been proposed.

As an example of cell leaning formed in a groove, for example, the 1985 International Electronic Devices Conference 1 (1985 International
n-al Electron [)evice t-1
710-page paper in the proceedings” Buri
ed Storage Electrode (BSE
) Ce1lfor ) Iegabit DRA) Is
This BSE cell has a cell capacitance in the form of a conductor buried inside a trench formed on a silicon substrate with an insulating film sandwiched between the conductor and the conductor buried in the trench. as an electrode that stores charge (it becomes electrically floating when storing information, hereinafter referred to as a storage node).
A silicon substrate is used as a counter electrode. The conductor buried in the groove is connected to one current-carrying electrode of a switching MO3FET formed on the surface of the silicon substrate. This BSE cell has the following advantages. That is, (1) since insulation between storage nodes of a plurality of adjacent memory cells is easy, the interval between these memory cells can be made sufficiently small; (2) Since the storage node is surrounded by an insulating film, even if a large amount of minority carriers are injected into the silicon substrate due to incidence of radioactive particles such as α particles, there is a low probability that they will be collected in the storage node. .

In other words, soft errors caused by radioactive particles such as α particles are less likely to occur.

Problems to be Solved by the Invention] However, the BSE cell has the following problems. When radioactive particles such as α particles are incident on an electrode of the opposite conductivity type to that of the silicon substrate, such as a current-carrying electrode of a MOSFET on a silicon substrate, an accelerated collection phenomenon of minority carriers called the funneling effect occurs. IEEE Electron Device
Letters 1 V Kano, ED-32, No
, 2゜258 pages of C, t'lu's paper" Alpha
a-Particle-Induced Field
and Enhanced Co11ection o
Because of this phenomenon, even in a BSE cell, if radioactive particles such as alpha particles
When incident on one of the current-carrying electrodes, a considerable amount of minority carriers will be collected at the recording node. Therefore,
In this case, the effect of the BSE cell structure is lost, and soft errors are likely to occur as in a normal 1T1C cell.

Just as soft errors occur when minority carriers generated by radioactive particles such as alpha particles flow into storage nodes of memory cells, soft errors that occur when similar minority carriers flow into bit lines are also a serious problem for memory. It is. However, with conventional memory cells such as 83-day cells,
One current-carrying electrode of the MOSFET (this is an electrode of the opposite conductivity type to the silicon substrate on the silicon substrate) is always connected to the bit line. Therefore, in a memory using these memory cells, when radioactive particles such as α particles are incident on the electrode, a funneling effect occurs, minority carriers flow into the bit line, and soft errors are likely to occur.

IEE is a memory cell that is less prone to soft errors.
E Electron Device Letters
s, VOL.

EDL-4, No. 1.8 page R, D, Jolly
Paper “A Dynamic RAM Ce1l” by et al.
In Recrystal! 1zedPOIySi l
A Koni 1C cell formed on a silicon layer as thin as 1con" has been proposed. However, in the case of this memory cell, it is difficult to connect the MO3FE substrate for switching to a constant potential power supply. As a result, In this memory cell, an unstable MOSFET whose substrate is electrically floating must be used as a switching transistor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory cell that is suitable for high integration, is less prone to soft errors due to radioactive particles such as α particles, and can use a MOSFET with a stable substrate potential as a switching transistor.

[Means for Solving the Problems] The present invention includes a first conductive type semiconductor substrate, an insulating film formed on a part of one main surface of the semiconductor substrate, and a - part on the insulating film. A first semiconductor region of a second conductivity type formed in the semiconductor film on the insulator film is configured to constitute a MOSFET at least as a component of a semiconductor film which is present and a part of which is in contact with the semiconductor substrate; , a first conductivity type second semiconductor region formed in the semiconductor film so as to be in contact with the first semiconductor region and the semiconductor substrate; a third semiconductor region of a second conductivity type connected to a bit line;
A semiconductor memory cell characterized by including a capacitor connected to a semiconductor region.

[Examples] Examples of the present invention will be described below with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and a cross-sectional view showing the structure of another embodiment of the semiconductor memory cell of the present invention, respectively, and FIG. 117-1
17 is a cross-sectional view taken along line 17. Figure 1 (a), (b)
, 101 is a P-type silicon crystal substrate, 102 is an insulating film, 104, 105, and 106 are silicon films.
is its N-type region, 105 is its P-type head region, and 106 is its N-type? J[, io8 is gate iit body s, 109.1
10 Harl 1 body membrane, 111 high concentration P type head loss, 112.1
13 is an insulating film, 114 is a trench opening, 115 is a contact hole, 116 is a boundary between an active region and an isolation region, 118
is the boundary between silicon films 104, 105 and 106, 109°
In order to avoid obscuring the corresponding portions of this memory cell and other adjacent memory cells, some lines are omitted.

The silicon films 104, 105, 106, gate insulator film 108, and conductor film 109 in this figure are Nf Yarnel MO3FETs.
The silicon film 104, the insulator film 102, and the highly doped P-type head region 111 each constitute a cell capacitor formed in the trench. A conductive film 10 that becomes the gate electrode of this MOSFET
9 also serves as a word line. The conductor film 110 is used as a bit line. P type head I4.105, high concentration P type head I
Ji! 111 is electrically connected to the P-type silicon substrate 101 and supplied with a constant potential.

In the memory cell of FIG. 1(a), (1)), except for the location where the N-type region 104 constituting the storage node and one of the current-carrying electrodes of the MOSFET contacts the P-type head 105,
Completely surrounded by insulation. Therefore, insulation between storage nodes of a plurality of adjacent memory cells can be easily achieved. Furthermore, since the N-type region 104 and the P-type region 105 in contact with it are located in a thin silicon film surrounded by an insulator, the number of minority carriers generated by the incidence of radioactive particles such as α particles in these regions is small. Very few. Therefore, there is almost no probability that a funneling effect will occur and many minority carriers will be acceleratedly collected in the storage node.

Similarly, in the memory cells of FIGS. 1(a) and 1(b), the N-type region 106 connected to the bit line is also connected to the P-type region 1. i 10
5 and the conductor film 110 are completely surrounded by an insulator. Therefore, in this part, the number of minority carriers generated by the incidence of radioactive particles such as α particles is extremely small, a funneling effect occurs, and there is almost no ra rate at which many minority carriers are collected on the bit line at a rate of 7 Jfl.

Furthermore, in the embodiments shown in FIGS. 1(a) and 1(b), a thin film MO8FET on a silicon film is used as a switching transistor, but since the substrate 105 of this MOSFET and the silicon substrate 101 are of the same conductivity type and are in contact with each other, This M
The substrate of the OSFET is connected to a constant potential power source.

As described above, the semiconductor memory cell of the present invention can be easily combined with the cell capacitance formed in the trench as in the above embodiment, so that a sufficient capacitance value can be obtained in a small area. Features such as high integration can be achieved because storage nodes can be easily insulated like in cells, and soft errors due to radioactive particles such as alpha particles are less likely to occur.

For convenience of explanation, the embodiments having the structures shown in FIGS. 1(a) and 1(b) have been used above, but the present invention is not limited thereto. The type and conductivity type of the transistor may be other suitable ones.

[Effects of the Invention] As explained above, the memory cell of the present invention is suitable for high integration, is resistant to soft errors caused by radioactive particles such as α particles, and has a stable substrate potential.
This is necessary because it has an effect such that T can be used as a switching transistor.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view showing the structure of an embodiment of the semiconductor memory cell of the present invention, and FIG.
It is a sectional view taken along the line 7-117°. 102...Insulator film 105.111...P-type head region 106...N-type region

Claims (1)

[Claims] (1) a first conductivity type semiconductor substrate, an insulating film formed on a part of one main surface of the semiconductor substrate, a part of which is on the insulating film and a part of which is in contact with the semiconductor substrate; a second conductivity type first semiconductor region formed in the semiconductor film on the insulator film, the first semiconductor region and the semiconductor substrate; a first conductivity type second semiconductor region formed in the semiconductor film so as to be in contact with the second semiconductor region;
A semiconductor memory cell characterized in that a third semiconductor region of a second conductivity type is formed in a semiconductor film on the insulating film and connected to a bit line, and includes a capacitor connected to the first semiconductor region.