JP5674121B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a lateral bipolar transistor and a manufacturing method thereof.

  Conventionally, semiconductor devices having various configurations have been developed in order to improve the breakdown voltage performance of bipolar transistors (for example, Patent Document 1).

  As shown in FIG. 8, the semiconductor device 500 disclosed in Patent Document 1 includes a silicon oxide film 20 b (second side surface isolation insulator region) that separates the base region 25 and the surface collector region 27 in the collector breakdown voltage region 24. It has. FIG. 8 is an example of a longitudinal sectional view showing a configuration of a conventional semiconductor device. Note that the silicon oxide film 20 b is not divided up to the buried collector region 23. By providing this silicon oxide film 20b, the electric field between the base region 25 and the surface collector region 27 is relaxed, and even if the distance between the base region 25 and the surface collector region 27 is reduced (the semiconductor device is miniaturized and integrated). Even) high pressure resistance can be maintained.

JP-A-6-232149

  However, the semiconductor device disclosed in Patent Document 1 has a problem that the number of manufacturing steps increases. Specifically, the silicon oxide film 20b (second side surface isolation insulator region) and the silicon oxide film 20a (first side surface isolation insulator region) surrounding the element formation region shown in FIG. After the trench groove is formed by etching, the inner surface of the trench groove is filled with oxidation and polysilicon. However, the silicon oxide film 20b needs to be formed shallower than the silicon oxide film 20a so as not to divide the buried collector region 23. That is, when forming the silicon oxide film 20a and the silicon oxide film 20b, it is necessary to form trench grooves having different depths. Therefore, the silicon oxide film 20b and the silicon oxide film 20a cannot be etched simultaneously under the same conditions. Therefore, when manufacturing the semiconductor device according to Patent Document 1, it is necessary to perform etching a plurality of times by changing the etching conditions according to the depths of the silicon oxide film 20a and the silicon oxide film 20b. .

  As described above, the conventional semiconductor device has a problem that the performance of the product is improved while the number of manufacturing processes is increased, and the manufacturing cost is increased and the manufacturing time is increased.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device having high pressure resistance while being manufacturable with a small number of man-hours.

  In order to solve the above problems, the present application adopts the following configuration. That is, according to the first aspect of the present invention, in order to insulate and separate the substrate, the element formation region formed on the substrate, and the element formation region from the external region, the element formation region side surface is formed at a depth from the element formation region surface to the substrate surface. A first insulating trench region formed so as to surround the element, wherein the element forming region includes a buried collector region of a high concentration first conductivity type formed on the upper surface of the substrate via a buried oxide film; A low-concentration first conductivity type collector breakdown voltage region formed on the buried collector region, a second conductivity type base region formed on the surface of the collector breakdown voltage region, and a base region on the surface of the collector breakdown voltage region A high-concentration first conductivity type surface collector region formed separately, a high-concentration first conductivity type emitter region formed on the surface of the base region, a base region, and a surface collector region A second insulating trench region formed at a depth from the surface of the element formation region to the surface of the substrate between the regions so as to block the linear movement of carriers in the semiconductor device. A carrier bypass region is formed between the insulating trench and the first insulating trench region so that carriers bypass the second insulating trench and move between the base region and the surface collector region. It is a semiconductor device.

  According to a second invention, in the first invention, the second insulating trench region is formed so as to be separated from the first insulating trench region when the element forming region is viewed in plan.

  According to a third invention, in the second invention, the first insulating trench region and the second insulating trench region are electrically connected to each of the first insulating trench region and the second insulating trench region, and the first insulating trench region and the second insulating trench region are predetermined. It is further characterized by further including a potential control unit that controls the potential.

  According to a fourth invention, in the first invention, when the element forming region is viewed in plan, the second insulating trench region is integrally formed at one end so as to be connected to the first insulating trench region, and the other end The first insulating trench region is formed so as to be separated from the first insulating trench region.

  According to a fifth aspect of the present invention, in the fourth aspect, the first insulating trench region electrically connected at any part of the integrally formed first insulating trench region and the second insulating trench region. And a potential controller for controlling the second insulating trench region to have a predetermined potential.

  A sixth invention is a method of manufacturing a semiconductor device according to the first invention, wherein a collector collector region is formed on an upper surface of a substrate via an oxide film, and a collector breakdown voltage region is formed above the buried collector region. A region forming step, an etching step of forming a trench by etching a region in which the first insulating trench region and the second insulating trench region are formed in the buried collector region and the collector breakdown voltage region, and forming an insulating layer in the trench An insulating region forming step for simultaneously forming the first insulating trench region and the second insulating trench region, and implanting the first conductivity type ions and the second conductivity type ions into the collector breakdown voltage region to thereby form the base region and the surface collector. And an electrode region forming step for forming an emitter region It is a manufacturing method of a semiconductor device.

  According to the first invention, since the first insulating trench region and the second insulating trench region are formed with the same depth, these regions can be formed simultaneously in the same process. Since the second insulating trench region is formed between the base region and the surface collector region, the potential between the base region and the surface collector region is stabilized, and high breakdown voltage performance can be obtained. Since a carrier bypass region is formed between the first insulating trench region and the second insulating trench region, the second insulating trench region completely moves carriers between the base region and the surface collector region. There is no disconnection, and the function as a transistor is not impaired.

  According to the second invention, the first insulating trench region and the second insulating trench region can be formed separately.

  According to the third aspect, by fixing the potentials of the first insulating trench region and the second insulating trench region, the potential distribution between the base region and the surface collector region can be further stabilized.

  According to the fourth invention, the first insulating trench region and the second insulating trench region can be integrally formed.

  According to the fifth aspect, by fixing the potentials of the first insulating trench region and the second insulating trench region, the potential distribution between the base region and the surface collector region can be further stabilized. In addition, since the first insulating trench region and the second insulating trench region are integrally formed, by connecting the potential control unit to either the first insulating trench region or the second insulating trench region, the first insulating trench is formed. The potentials of both the region and the second insulating trench region can be controlled simultaneously.

  According to the sixth invention, since the first insulating trench region and the second insulating trench region can be formed in the same process, the semiconductor device according to the first invention can be manufactured with a relatively small number of steps.

Plane layout diagram showing the configuration of the semiconductor device 100 according to the first embodiment 1 is a cross-sectional view taken along the line AA ′ in FIG. 1, showing the configuration of the semiconductor device 100 according to the first embodiment. The figure which shows the manufacturing process of the semiconductor device 100 which concerns on 1st Embodiment. The figure which shows the manufacturing process of the semiconductor device 100 which concerns on 1st Embodiment. The figure which shows electric potential distribution at the time of planarly viewing the semiconductor device 100 which concerns on 1st Embodiment. The figure which shows potential distribution at the time of planar view of the conventional semiconductor device which is not provided with the 2nd insulation trench 10b. Plane layout diagram showing the configuration of the semiconductor device 200 according to the second embodiment An example of a longitudinal sectional view showing a configuration of a conventional semiconductor device

(First embodiment)
Hereinafter, the semiconductor device 100 according to the first embodiment of the present invention will be described. The semiconductor device 100 is a so-called bipolar transistor device. First, the configuration of the semiconductor device 100 will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view layout diagram showing the configuration of the semiconductor device 100 according to the first embodiment. FIG. 2 is a cross-sectional view taken along the line AA ′ in FIG. 1, showing the configuration of the semiconductor device 100 according to the first embodiment. In the following, the configuration and the like of the semiconductor device 100 will be described using an XYZ coordinate system in which the substrate plane of the semiconductor device 100 illustrated in FIG. 1 is the XY plane and the cross section illustrated in FIG. 2 is the XZ plane.

  As shown in FIGS. 1 and 2, the semiconductor device 100 includes a silicon substrate 1, an element formation region 11, a first insulating trench region 10 a, and a potential control unit 13. The element formation region 11 is formed on the silicon substrate 1, and the first insulating trench region 10 a is formed so as to surround the side surface of the element formation region 11. The silicon substrate 1 is typically a support base for single crystal silicon.

  The first insulating trench region 10a is an insulating portion that insulates and isolates the element forming region 11 from the external region. The first insulating trench region 10a has a depth from the surface of the element formation region 11 to the surface of the silicon substrate 1 as shown in FIG. The first insulating trench region 10 a is made of the trench sidewall oxide film 6 and the trench buried polysilicon 7.

  The element formation region 11 includes a buried collector region 3, a collector breakdown voltage region 4, a base region 5, an emitter region 8a, a surface collector region 8b, and a second insulating trench 10b. Further, an emitter electrode 9a, a base electrode 9b, a collector electrode 9c, and a surface oxide film 16 are formed on the element forming region 11. In the present embodiment, as shown in FIG. 1, the element formation region 11 is formed as a rectangular region in plan view.

A buried oxide film 2 is formed on the bottom surface of the element formation region 11, that is, on the top surface of the silicon substrate 1. The buried oxide film 2 is typically a BOX (Buried Oxide) oxide film. A buried collector region 3 is formed on the buried oxide film 2. The buried collector region 3 is an N ⁺ type region. Further, a collector breakdown voltage region 4 is formed on the buried collector region 3. The collector breakdown voltage region 4 is an N ⁻ type region. The upper surface of the collector breakdown voltage region 4 is covered with a surface oxide film 16 except for regions (so-called contact holes) connected to the emitter electrode 9a, the base electrode 9b, and the collector electrode 9c.

The base region 5 is a P ⁺ type region formed in an island shape on the surface portion of the collector breakdown voltage region 4. The base electrode 9 b is an electrode that is electrically connected to the base region 5. The surface collector region 8 b is an island-like N ⁺ type region formed away from the base region 5 in the surface portion of the collector breakdown voltage region 4. The collector electrode 9c is an electrode that is electrically connected to the surface collector region 8b. The emitter region 8 a is an N ⁺ type region formed in an island shape on the surface portion of the base region 5. The emitter electrode 9a is an electrode that is electrically connected to the emitter region 8a. The emitter electrode 9a, the base electrode 9b, and the collector electrode 9c are typically electrodes made of metal such as aluminum.

  The second insulating trench region 10b is an insulating region formed so as to block the linear movement of carriers between the base region 5 and the surface collector region 8b. As shown in FIG. 2, when the semiconductor device 100 is viewed in a longitudinal section, the second insulating trench region 10 b is formed from the surface of the element formation region 11 to the surface of the silicon substrate 1. The second insulating trench region 10b is made of the trench side wall oxide film 6 and the trench embedded polysilicon 7 like the first insulating trench region 10a. As shown in FIG. 1, when the semiconductor device 100 is viewed in plan, carrier bypass regions 12a and 12b are formed between the second insulating trench 10b and the first insulating trench region 10a. That is, the second insulating trench 10b and the first insulating trench region 10a are formed separately. More specifically, the second insulating trench 10b is a wall-like region extending in the Y-axis direction when viewed in plan, and both ends thereof are separated from the first insulating trench region 10a by a certain distance. It is formed as follows. These separated areas correspond to the carrier bypass areas 12a and 12b.

  The shape and arrangement of the second insulating trench 10b in the XY plane are not limited to those shown in FIG. 1, and may be modified into any form as long as the second insulating trench 10b is formed so as to block the linear movement of the carrier. However, when the semiconductor device 100 is viewed in plan, the second insulating trench 10b blocks a straight line connecting an arbitrary point on the outer periphery of the base region 5 and an arbitrary point on the outer periphery of the surface collector region 8b. More preferably, it is formed.

  With the above configuration, when a predetermined voltage is biased between the collector and the base of the semiconductor device 100, carriers pass between the base region 5 and the surface collector region 8b through the carrier bypass regions 12a and 12b. Can be moved. More specifically, the carrier can move between the base region 5 and the surface collector region 8b along a path indicated by a thick arrow CM1 in FIG. Thus, by providing the carrier bypass regions 12a and 12b, even if the second insulating trench region 10b is formed at a depth from the surface of the element formation region 11 to the surface of the silicon substrate 1, A movement path is secured and the function of the semiconductor device 100 as a transistor is not impaired.

  As shown in FIG. 1, the first insulating trench region 10 a is electrically connected to the potential controller 13 via the first connection line 14, and the second insulating trench 10 b is electrically connected to the potential control unit 13 via the second connection line 15. The The potential control unit 13 is a circuit or member that fixes the potentials of the first insulating trench region 10a and the second insulating trench 10b. The potential control unit 13 is typically a ground terminal block.

  A method for manufacturing the semiconductor device 100 will be described with reference to FIGS. FIG. 3 and FIG. 4 are diagrams showing a manufacturing process of the semiconductor device 100 according to the first embodiment.

First, N ^- prepared -type semiconductor substrate, by implanting diffusing high-concentration N ⁺ type ions in one surface of the semiconductor substrate, N ⁺ -type buried collector region 3 and the N ^- type collector withstand voltage region 4 Are formed in layers. Next, for example, a P ⁻ -type semiconductor substrate is separately prepared, and the semiconductor substrate is thermally oxidized to form the silicon substrate 1 and the buried oxide film 2 in layers. Then, by heating and pressing these two substrates together, as shown in FIG. 3, the semiconductor substrate 1, the buried oxide film 2, the buried collector region 3, and the collector withstand voltage region 4 were sequentially laminated. A so-called SOI (Silicon on Insulator) substrate is manufactured. Note that the above method is an example, and a conventionally known method may be used as a method for manufacturing an SOI substrate as shown in FIG.

  Next, in the SOI substrate shown in FIG. 3, a resist mask is formed in regions other than the regions where the first insulating trench region 10a and the second insulating trench 10b are to be formed. Then, by performing an etching process such as plasma etching, a trench groove is formed in a region where the first insulating trench region 10a and the second insulating trench 10b are to be formed. Note that any conventionally known method may be used as the etching method. The trench sidewall oxide film 6 is formed on the inner surface of the trench groove by thermally oxidizing the SOI substrate after the trench groove is formed. Then, the trench embedded polysilicon 7 is formed by injecting polysilicon into the cavity in the trench groove. Through such steps, the first insulating trench region 10a and the second insulating trench 10b are simultaneously formed as shown in FIG.

  Next, the base region 5, the emitter region 8a, and the surface collector region 8b are formed by sequentially implanting the corresponding conductivity type ions into the SOI substrate as shown in FIG. Thereafter, a surface oxide film 16 is formed by CVD (Chemical Vapor Deposition) or the like. The surface oxide film 16 is subjected to photolithography and etching to form contact holes (openings) for joining the base region 5, the emitter region 8a, and the surface collector region 8b to corresponding electrodes. Then, an emitter electrode 9a, a base electrode 9b, and a collector electrode 9c are formed by evaporating a metal wiring such as aluminum in the contact hole.

  As described above, since the first insulating trench region 10a and the second insulating trench 10b are formed at the same depth in the semiconductor device 100 according to the present invention, they can be formed in the same process. That is, since it is not necessary to repeatedly perform etching by changing the etching conditions in order to form the first insulating trench region 10a and the second insulating trench 10b, it can be manufactured at a lower cost and in a shorter time than a conventional semiconductor device. can do.

  Since the semiconductor device 100 described above includes the second insulating trench 10b, the electric field between the base region 5 and the surface collector region 8b can be relaxed and high breakdown voltage performance can be obtained. Hereinafter, the manner in which the electric field is relaxed in the semiconductor device 100 will be described with reference to FIGS. FIG. 5 is a diagram illustrating a potential distribution when the semiconductor device 100 according to the first embodiment is viewed in plan. FIG. 6 is a diagram showing a potential distribution when a conventional semiconductor device not provided with the second insulating trench 10b is viewed in plan. More specifically, FIG. 5 and FIG. 6 show equipotential lines passing through the same potential portions in the plan views of the respective semiconductor devices. The equipotential lines shown in FIG. 5 and FIG. 6 are based on the assumption that the same positive voltage is biased between the collector and the base for each of the semiconductor device 100 and the conventional semiconductor device having the same dimensions. It is the simulation result obtained by performing.

  When comparing the equipotential line intervals between the base region 5 and the surface collector region 8b shown in FIGS. 5 and 6 (regions surrounded by dotted lines in FIGS. 5 and 6), the semiconductor device shown in FIG. In the case of 100, the interval between the equipotential lines is longer than that of the conventional product shown in FIG. That is, in the semiconductor device 100, the amount of potential change per unit length between the base region 5 and the surface collector region 8b is smaller than that of the conventional product, and the electric field strength in the region is relaxed. This is due to the fact that in the semiconductor device 100, the linear movement of carriers between the base region 5 and the surface collector region 8b is blocked by the presence of the second insulating trench 10b. As described above, according to the semiconductor device 100 of the present invention, the electric field strength between the base region 5 and the surface collector region 8b can be relaxed, and high breakdown voltage performance can be obtained.

  As described above, according to the semiconductor device 100 according to the first embodiment of the present invention, high withstand voltage performance can be obtained while being manufactured with a small number of man-hours.

(Second Embodiment)
In the first embodiment, the example in which the second insulating trench 10b is formed separately from the first insulating trench region 10a has been described. However, the second insulating trench 10b is integrated with the first insulating trench region 10a. It may be formed. Hereinafter, the semiconductor device 200 according to the second embodiment will be described.

  As shown in FIG. 7, the semiconductor device 200 according to the second embodiment is integrally formed so that one end of the second insulating trench 10b is connected to the first insulating trench region 10a. FIG. 7 is a plan view layout diagram showing the configuration of the semiconductor device 200 according to the second embodiment. In FIG. 7, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. As shown in FIG. 7, the second insulating trench 10b is a wall-like region extending in the Y-axis direction when viewed in plan, and the other end of the second insulating trench 10b is the first insulating trench region. It is separated from 10a. And the said separation | spacing location functions as the carrier bypass area | region 12c.

  With the above configuration, when the semiconductor device 200 is biased with a predetermined voltage between the collector and the base, carriers move between the base region 5 and the surface collector region 8b through the carrier bypass region 12c. can do. More specifically, the carrier can move between the base region 5 and the surface collector region 8b along the path indicated by the thick arrow CM2 in FIG. That is, by providing the carrier bypass region 12c, the carrier movement path is ensured in the semiconductor device 200 according to the second embodiment as in the first embodiment, and the function of the semiconductor device 200 as a transistor is achieved. Will not be damaged.

  Further, as described above, the semiconductor device 200 according to the second embodiment also includes the first insulating trench region 10a and the second insulating trench 10b having the same depth, and thus the semiconductor device according to the first embodiment described above. Similar to 100, the first insulating trench region 10a and the second insulating trench 10b can be formed in the same process. As described above, similarly to the semiconductor device 100 according to the first embodiment, the semiconductor device 200 according to the second embodiment can obtain a high withstand voltage performance while being able to be manufactured with a small number of steps.

  Note that, also in the semiconductor device 200 according to the second embodiment, it is preferable that the first insulating trench region 10 a and the second insulating trench 10 b are electrically connected to the potential control unit 13. Here, in the semiconductor device 200, since the first insulating trench region 10a and the second insulating trench 10b are integrally formed and electrically connected, the first insulating trench region 10a and the second insulating trench 10b One wiring for connecting the potential control unit 13 can be formed. 7 shows an example in which the first insulating trench region 10a and the second insulating trench 10b and the potential control unit 13 are wired so as to be connected to the first insulating trench region 10a by the first connection line 14. However, the connection line may be connected to any location of the first insulating trench region 10a and the second insulating trench 10b.

  In each of the above embodiments, the example in which the potential is fixed by connecting the first insulating trench region 10a and the second insulating trench 10b to the potential control unit 13 has been described. Even if the potential of the second insulating trench 10b is not fixed, the electric field strength between the base region 5 and the surface collector region 8b can be moderated to some extent only by forming the second insulating trench 10b. That is, the configurations of the potential control unit 13, the first connection line 14, and the second connection line 15 may be omitted as appropriate in consideration of performance, cost, and layout required for the semiconductor device.

  The semiconductor device according to the present invention is useful as a semiconductor device having high withstand voltage performance while being manufacturable with a small number of steps.

1 silicon substrate 2 buried oxide film 3 buried collector region 4 collector breakdown voltage region 5 base region 6 trench sidewall oxide film 7 trench buried polysilicon 8a emitter region 8b surface collector region 9a emitter electrode 9b base electrode 9c collector electrode 10a first insulation Trench region 10b Second insulating trench 11 Element formation region 12a, 12b Carrier detour region 13 Potential control unit 14 First connection line 15 Second connection line 16 Surface oxide film 100, 200 Semiconductor device

Claims (3)

A substrate,
An element formation region formed on the substrate;
A first insulating trench region formed so as to surround a side surface of the element formation region at a depth from the surface of the element formation region to the surface of the substrate so as to insulate and isolate the element formation region from an external region. And
The element formation region is
A high concentration first conductivity type buried collector region formed on the upper surface of the substrate via a buried oxide film;
A low-concentration first conductivity type collector breakdown voltage region formed on the buried collector region;
A base region of a second conductivity type formed on a surface portion of the collector breakdown voltage region;
A high-concentration first conductivity type surface collector region formed apart from the base region on the surface of the collector withstand voltage region so as to be island-shaped in the collector withstand voltage region
A high-concentration first conductivity type emitter region formed on a surface portion of the base region;
The base region and to block the linear movement of the carrier between the said surface collector region, a second isolation trench region formed from said device formation region surface between the region at a depth in said substrate table Menma And
When the semiconductor device is viewed in plan, the carrier bypasses the second insulating trench and is between the base region and the surface collector region between the second insulating trench and the first insulating trench region. A carrier detour area for moving the vehicle ,
The semiconductor device, wherein the second insulating trench region is formed to be separated from the first insulating trench region when the element forming region is viewed in plan . The first insulating trench region and the second insulating trench region have buried polysilicon inside the trench,
Said buried polysilicon of the first isolation trench region, and the second is the buried polysilicon respectively electrically connected to the insulating trench region, said buried polysilicon of the first isolation trench region, and the second insulating and further comprising a potential control unit for controlling so that the stipulated buried polysilicon advance the potential of the trench region, the semiconductor device according to claim 1. A method of manufacturing the semiconductor device according to claim 1,
A collector region forming step of forming the buried collector region on the upper surface of the substrate via the oxide film, and the collector breakdown voltage region on the buried collector region;
The buried among the collector region and the collector withstand voltage region, by etching the area where the first insulating trench region and the second isolation trench region is formed, the trench and the second isolation trench region of said first isolation trench region An etching step of forming a trench so as to be separated from the trench,
An insulating region forming step of simultaneously forming the first insulating trench region and the second insulating trench region by forming an insulating layer in the trench;
An ion implantation step of forming the base region, the surface collector region, and the emitter region by implanting the first conductivity type ions and the second conductivity type ions into the collector breakdown voltage region. A method for manufacturing a semiconductor device.

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