JP2008085117A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, along with its manufacturing method, of which a parasitic capacitance is reduced for excellent high frequency characteristics. <P>SOLUTION: The semiconductor device comprises a substrate, a gate insulating film, a gate electrode, a drain/source region, a first interlayer insulating film formed on the substrate, and a second interlayer insulating film formed on or above the first interlayer insulating film. The drain region is formed away from the gate electrode in gate length direction. On the first interlayer insulating film, a field plate provided between the gate electrode and the drain region and a metal film which connects to the gate electrode and extends over the source region are formed. On the second interlayer insulating film, a metal film 17b which bestrides the gate electrode to cover above the field plate and the source region and connects to the field plate is formed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device that handles high-frequency signals and a method for manufacturing the same.

  In recent years, with the widespread use of wireless communication devices such as mobile phones, there is an increasing demand for high-frequency ICs that can transfer large amounts of data such as image information at high speed. In particular, since MOS transistors are widely used as power amplifier circuits for wireless communication, high speed and high frequency characteristics are required. In order to improve the high frequency characteristics of the MOS transistor, it is important to reduce resistance and parasitic capacitance. The parasitic capacitance in the MOS transistor includes various capacitances such as a capacitance generated between the gate and the drain, a capacitance generated between the gate and the source, and a capacitance generated between the wirings. Among these, the capacitance generated between the gate and the drain occupies a large portion of the parasitic capacitance in the MOS transistor. Therefore, a technique for improving the high frequency characteristics of the MOS transistor by using a field plate that suppresses the capacitance between the gate and the drain has been proposed.

  FIG. 13 is a cross-sectional view showing a conventional semiconductor device provided with a field plate described in Patent Document 1, for example. The conventional semiconductor device shown in FIG. 1 is a high voltage MOS transistor in which a drain region is provided away from a gate electrode. A method for manufacturing this semiconductor device will be briefly described below.

First, as shown in FIG. 13, for example, p-type impurity ions are selectively implanted into a part of the p ⁻ -type silicon substrate 101 containing low-concentration impurities, and the impurity concentration is slightly lower than that of the p ⁻ -type silicon substrate 101. A high p ^- type well 102 is formed. Next, an n ⁻ type well 103 is formed in the drain portion of the p ⁻ type silicon substrate 101 by ion implantation of n type impurities. Next, after forming a thin silicon oxide film and a polysilicon layer on the substrate, patterning is performed to form the gate insulating film 104 and the gate electrode 105. Further, a high breakdown voltage layer (offset gate) 106 is formed in a region extending from the p ⁻ type well 102 to the n ⁻ type well 103 by ion implantation. Next, a silicon oxide film 107 is formed by CVD to cover the upper and side surfaces of the gate electrode 105 and the high breakdown voltage layer 106, and then an n ⁺ source region 108 and an n ⁺ drain region 109 are formed. Then, a field plate 110 provided above the gate electrode 105 and a drain electrode 111 provided on the n ⁺ drain region 109 are formed by Al deposition and selective etching. A conventional semiconductor device can be manufactured through the above steps.

In the conventional semiconductor device described above, the gate electrode 105 made of polysilicon is covered with the silicon oxide film 107, and the field plate 110 that covers the gate electrode from above the insulating film is formed using one metal film. This relaxes the electric field between the gate and the drain, suppresses the generation of capacitance between the gate and the drain, and improves the high frequency characteristics.
JP-A-57-104258

  However, in a conventional semiconductor device which is a MOS transistor used in a power amplifier circuit, it is necessary to increase the gate width because it is necessary to extract a large amount of current. In the conventional semiconductor device structure, when the gate length is reduced to, for example, 1 μm or less, the gate resistance increases. Therefore, in high frequency operation, a desired voltage is not applied to the entire gate electrode, and only a part of the MOS transistor operates at high frequency. There was a fear. For this reason, in order to obtain a large current, a large number of transistors with small dimensions are connected. In this case, the area of the entire device becomes large. In the conventional semiconductor device structure, since there is a step between the source electrode and the gate electrode, the insulating film is generally formed thin in order to reduce the step. When the insulating film is thin, electrons are injected into a portion of the insulating film provided under the field plate located between the source electrode and the gate electrode. As a result, the threshold voltage changes with time, and the reliability of the semiconductor device is impaired.

  In view of the above, an object of the present invention is to provide a semiconductor device having excellent high-frequency characteristics with reduced parasitic capacitance without impairing reliability, and a method for manufacturing the same.

  In order to achieve the above object, a semiconductor device of the present invention includes a semiconductor substrate, a gate electrode formed on the semiconductor substrate with a gate insulating film interposed therebetween, and an impurity formed on the side of the gate electrode in the semiconductor substrate. And a source region including a semiconductor substrate and a side of the semiconductor substrate opposite to the source region when viewed from the gate electrode and in a position away from the gate electrode in the gate length direction. A drain region including the first interlayer insulating film formed on the semiconductor substrate and the gate electrode, a second interlayer insulating film formed on or above the first interlayer insulating film, and a first interlayer A field plate made of metal formed on the insulating film and between the gate electrode and the drain region, and connected to the gate electrode, on the first interlayer insulating film, and at least partially planar You see A first metal film formed at a position overlapping with the gate electrode and a field plate, and formed on a second interlayer insulating film at a position overlapping at least partly with the field plate when viewed in plan. A second metal film, a first contact for connecting the gate electrode and the first metal film, and a second contact for connecting the field plate and the second metal film are provided.

  According to this configuration, the field plate and the second metal film connected to the field plate are disposed between the gate electrode (and the wiring connected to the gate electrode) and the drain electrode (and the wiring connected to the drain electrode). Since the electric field generated in the gate electrode is relaxed, the capacitance generated between the gate and the drain can be reduced. Since the capacitance generated between the gate and the drain occupies a large portion of the parasitic capacitance in the transistor, the high frequency characteristics can be greatly improved by reducing this capacitance. In addition, the field plate is provided with a first interlayer insulating film interposed therebetween as viewed from the gate electrode, and the second metal film is further provided with a second interlayer insulating film interposed therebetween as viewed from the gate electrode. Since the first interlayer insulating film and the second interlayer insulating film have a sufficient thickness, the threshold voltage of the transistor is increased by injecting electrons into the first interlayer insulating film under the field plate. Can be prevented from changing.

  In the semiconductor device of the present invention, it is preferable that the first metal film covers the entire upper portion of the gate electrode. Thereby, it becomes easy to provide a plurality of first contacts, and the resistance value of the gate electrode and the wiring connected to the gate electrode can be reduced. Alternatively, the resistance value of the first contact can be reduced by increasing the width of the first contact in the gate width direction.

  The second metal film preferably extends over the gate electrode to the source region and is connected to the source region. Thereby, the capacitance generated between the gate and the drain can be further reduced. Note that since the second metal film is connected to the source region, there is no need to provide a pad for connection to the outside of the device.

  Further, the second metal film connected to the field plate may be connected to the substrate region. When the substrate region is grounded, the field plate is also at the ground potential, so that the electric field generated between the gate and the drain can be effectively reduced.

  Further, since the first metal film extends from above the gate electrode so as to straddle the source region, it is possible to reduce the capacitance generated as compared with the case where the first metal film extends to the drain side. This is because the capacitance generated between the gate and the drain is significantly larger than the capacitance generated between the gate and the source.

  In addition, the first metal film connected to the gate electrode and the second metal film connected to the field plate are minimized so as not to overlap each other, thereby reducing the capacitance generated between the gate and the source. can do.

  Also, in the method of manufacturing a semiconductor device according to the present invention, after forming a gate insulating film and a gate electrode on a semiconductor substrate, a first conductivity type impurity is introduced into a part of the semiconductor substrate to be positioned laterally of the gate electrode Forming a source region in the region and forming a drain region in a region on the side opposite to the source region when viewed from the gate electrode and away from the gate electrode in the gate length direction; and step (a) Thereafter, a step (b) of forming a first interlayer insulating film on the semiconductor substrate, and one or a plurality of first contacts connected to the gate electrode and penetrating the first interlayer insulating film are formed. Step (c), a field plate formed at a position between the gate electrode and the drain region, a position connected to the gate electrode via the first contact, and a position at least partially overlapping the gate electrode in plan view Formed into A step (d) of simultaneously forming the first metal film on the first interlayer insulating film, a step (e) of forming a second interlayer insulating film on or above the first interlayer insulating film, And (f) forming a second metal film connected to the field plate on the second interlayer insulating film and at least partially overlapping the field plate when seen in a plan view.

  According to this method, it is possible to manufacture a semiconductor device excellent in high frequency characteristics in which the capacitance generated between the gate and the drain is reduced by the field plate and the second metal film connected thereto. In particular, since the wiring connected to the field plate and the gate electrode can be formed in the same process as the first metal film for drawing out in the direction of the source region, the field plate can be manufactured without increasing the number of processes. it can.

  Since the semiconductor device according to the present invention can suppress the gate-drain capacitance and reduce the gate resistance without impairing reliability, it can realize excellent high frequency characteristics. Moreover, according to the method for manufacturing a semiconductor device of the present invention, a highly reliable semiconductor device having excellent high frequency characteristics can be manufactured.

(First embodiment)
FIG. 1A is a plan view showing a wiring layout in a MOS transistor which is a semiconductor device according to the first embodiment of the present invention, and FIG. 1B shows a cross section taken along line Ib-Ib of the MOS transistor. FIG. 6C is a diagram showing a cross section of the MOS transistor taken along line Ic-Ic. The “first layer contact” shown in FIG. 1A means a contact for connecting a gate electrode composed of an impurity diffusion layer in a semiconductor substrate and a polysilicon layer on the semiconductor substrate to the first wiring layer, The “second layer contact” means a contact connecting the first wiring layer and the second wiring layer.

As shown in FIGS. 1A to 1C, the MOS transistor of this embodiment includes a semiconductor substrate 1 made of, for example, p ⁻ type silicon, an n ⁻ type well layer 2 formed in the semiconductor substrate 1, A p ⁻ type well layer 6 formed in the semiconductor substrate 1 and partially in contact with the n ⁻ type well layer 2, an element isolation insulating film (for example, a LOCOS layer) 3 surrounding an element formation region of the semiconductor substrate 1, and a semiconductor A gate insulating film 4 made of, for example, silicon oxide, and a polysilicon gate formed on the substrate 1 and above the n ⁻ type well layer 2 and the p ⁻ type well layer 6 with the gate insulating film 4 interposed therebetween. An electrode 5, a source region 8 including a high concentration n-type impurity formed in a region located on the side of the gate electrode 5 in the p ⁻ type well layer 6, and opposite to the source region 8 when viewed from the gate electrode 5. It is the lateral side of the side n ^- Katau It is formed at a position distant from the gate electrode 5 in Le layer 2, and a drain region 7 comprising a high-concentration n-type impurity, a p ⁺ substrate region 9 formed on the semiconductor substrate 1. Since the drain region 7 is provided away from the gate electrode 5 in the gate length direction (left-right direction in FIG. 1B), the breakdown voltage is higher than when the distance between the drain region 7 and the gate electrode 5 is short. It has improved. The concentrations of impurities contained in the n ⁻ type well layer 2, the p ⁻ type well layer 6, the source region 8 and the drain region 7 are 1 × 10 ¹⁶ cm ⁻³ , 7 × 10 ¹⁷ cm ⁻³ and 1 × 10 ^{21, respectively.} It is about cm ⁻³ .

  In addition, the MOS transistor of the present embodiment is formed on the gate insulating film 4 and the element isolation insulating film 3, and includes a first interlayer insulating film 10 that forms a first wiring layer, and a first interlayer insulating film. 10 and a second interlayer insulating film 13 which forms a second wiring layer. In the first wiring layer, a metal film 16a, a metal film 16b, a metal film 16c, a metal film 16d, and a field plate 12 are provided. The metal films 16a, 16b, 16c, 16d and the field plate 12 are all made of aluminum (Al) and are formed simultaneously. That is, the metal films 16 a, 16 b, 16 c and 16 d and the field plate 12 are provided on the same first interlayer insulating film 10.

Further, in the second wiring layer, a metal film 17a connected to the p ⁺ substrate region 9 via the contact 14a, the metal film 16a and the contact 11a, and a source via the contact 14b, the metal film 16b and the contact 11b A metal film 17b connected to the field plate 12 through the contact 14c, a metal film 17c connected to the drain region 7 through the contact 14d, the metal film 16d, and the contact 11d; 14e, a metal film 16c, and a metal film 17d connected to the gate electrode 5 through the contact 11c. The metal film 17a, the metal film 17b, the metal film 17c, and the metal film 17d are all made of Al, and are formed simultaneously.

  The first feature of the MOS transistor according to the present embodiment is that the field plate 12 and the metal film 17b provided in the second wiring layer and connected to the field plate 12 are viewed in a plan view with the gate electrode 5 and the drain. It exists in being arrange | positioned between the area | regions 7. Thereby, for example, as shown in FIG. 1, the electric field generated between the gate and the drain by connecting the metal film 17b to the source region 8 can be reduced. For this reason, in the MOS transistor of this embodiment, the capacitance generated between the gate and the drain is reduced, and the high frequency characteristics are superior to those of the conventional MOS transistor. Note that the capacitance between the gate and the drain is not only generated between the gate electrode 5 and the drain region 7 but also generated between the wiring connected to the gate electrode 5 and the wiring connected to the drain region 7. Includes capacity. In addition, it is preferable that the source region 8 and the metal film 17b have a ground potential because an electric field generated between the gate and the drain can be effectively relaxed. The field plate 12 and the metal film 17b connected to the field plate 12 are arranged with at least the first interlayer insulating film 10 between the gate electrode 5 and separated from the metal film 16c connected to the gate electrode 5. Therefore, the occurrence of a problem such as a change in threshold voltage that may occur in a conventional MOS transistor is also suppressed.

  Next, a second feature of the MOS transistor of this embodiment is that the metal film 16c provided in the first wiring layer covers the entire upper portion of the gate electrode 5. If the metal film 16c overlaps at least a part of the gate electrode 5 in plan view, the metal film 16c can be connected by contact. However, since the metal film 16c covers the entire upper portion of the gate electrode 5, the metal film 16c can be connected. It is possible to provide a plurality of contacts 11c that connect the gate electrode 5 to each other. Therefore, the resistance between the metal film 16c and the gate electrode 5 can be reduced. This effect is particularly effective when the gate electrode 5 is made of polysilicon having a resistance value larger than that of the metal film 16c. This also contributes to the improvement of the high frequency characteristics of the MOS transistor of this embodiment. In addition, since a plurality of contacts 11c are formed, even if any of the contacts 11c has a connection failure, an electrical connection can be ensured through the remaining contacts 11c, thereby improving operational reliability. Can do.

  Furthermore, the third feature of the MOS transistor of this embodiment is that the wiring (metal films 16c and 17d) connected to the gate electrode 5 is drawn out to the source side instead of the drain side. Since the wiring connected to the gate electrode 5 is pulled out to the source side, the gate-drain capacitance serving as the feedback capacitance can be reduced as much as possible, and the high-frequency characteristics can be improved.

  In addition, since the metal film 17b connected to the source region 8 does not overlap with the metal film 16c connected to the gate electrode 5 in a planar manner, the gate-source capacitance is reduced.

  In the MOS transistor of this embodiment, as shown in FIG. 1A, the length of the field plate 12 in the gate width direction (vertical direction in FIG. 1A) is provided at least above the gate electrode 5. The gate width of the metal film 16c is about the same. The metal film 17b disposed in the second wiring layer covers the entire upper portion of the field plate 12, and a plurality of contacts 14c for connecting the metal film 17b and the field plate 12 are provided. As a result, the electric field generated between the wiring (contacts 11c, 14e, metal films 16c, 17d) connected to the gate electrode 5 and the wiring (contacts 11d, 14d, metal films 16d, 17c) connected to the drain region 7. Can be mitigated more effectively. Therefore, the capacitance generated between the gate and the drain is effectively reduced.

A plurality of contacts 11d and 14d electrically connected to the drain region 7 and a plurality of contacts 11a and 14a electrically connected to the p ⁺ substrate region 9 are also provided. Thereby, the resistance in these wirings is reduced as compared with the case where only one contact is provided.

  Next, a method for manufacturing the MOS transistor of this embodiment will be described. FIGS. 2A to 2G and FIGS. 3A to 3G are cross-sectional views showing a method for manufacturing the MOS transistor of this embodiment. 2A to 2G show cross sections taken along line Ib-Ib in FIG. 1A, and FIGS. 3A to 3G show lines taken along line Ic-Ic in FIG. A cross section is shown.

First, as shown in FIGS. 2A and 3A, an n ⁻ type well layer 2 is formed by ion implantation of an n type impurity into a part of a semiconductor substrate 1 made of, for example, p ⁻ type silicon. Next, a part of the upper portion of the semiconductor substrate 1 is oxidized to form an element isolation insulating film 3 surrounding the element formation region. Instead of the element isolation insulating film 3, STI (Shallow Trench Isolation) may be formed. Next, after forming the gate insulating film 4, a gate electrode 5 made of polysilicon is formed by a known method. The gate insulating film 4 may be formed by a CVD method or the like, or may be formed by thermal oxidation or the like. Subsequently, a p ^- type well layer 6 is formed by ion implantation of p-type impurities into a part of the semiconductor substrate 1. Next, an n-type impurity is ion-implanted into a part of the p ⁻ type well layer 6 and a part of the n ⁻ type well layer 2, and then the impurity is diffused in the lateral direction to form the drain region 7 and the source region 8. . Next, a p ⁺ substrate region 9 is formed by ion implantation of p-type impurities into a part of the semiconductor substrate 1. Thereafter, a first interlayer insulating film 10 made of silicon oxide is deposited on the entire surface of the substrate by CVD or the like.

Next, as shown in FIGS. 2B and 3B, a part of the first interlayer insulating film 10 is selectively etched and viewed in a plan view, the drain region 7, the source region 8, and the gate. A contact hole is formed at a position overlapping the electrode 5 and the p ⁺ substrate region 9. Here, a plurality of contact holes are formed for each of the drain region 7, the source region 8, the gate electrode 5, and the p ⁺ substrate region 9.

  Next, as shown in FIGS. 2C and 3C, after depositing a W (tungsten) film using a CVD method, the entire surface of the W film is subjected to dry etching, thereby forming a contact hole. Contacts 11a, 11b, 11c, and 11d are formed.

Next, as shown in FIGS. 2D and 3D, after the Al film is formed by the CVD method or the sputtering method, the Al film is etched according to the wiring pattern, and the metal films 16a, 16b, 16c, 16d and the field are etched. Plate 12 is formed simultaneously. Here, the field plate 12 is formed on the first interlayer insulating film 10 at a position between the gate electrode 5 and the drain region 7 when viewed in plan. The metal film 16 c is formed so as to cover the entire upper portion of the gate electrode 5, and extends between the source region 8 and the p ⁺ substrate region 9, bypassing the upper region of the source region 8 in plan view. Formed as follows. Further, the metal film 16 d is formed so as to cover the entire upper part of the drain region 7, for example, and the metal film 16 a is formed so as to cover the entire upper part of the p ⁺ substrate region 9.

  Next, as shown in FIGS. 2 (e) and 3 (e), a second layer made of silicon oxide is formed on the metal films 16a, 16b, 16c, 16d and the first interlayer insulating film 10 by, eg, CVD. The interlayer insulating film 13 is formed.

  Next, as shown in FIGS. 2 (f) and 3 (f), a part of the second interlayer insulating film 13 is selectively etched and the metal films 16a, 16b, 16c, 16d and A contact hole is formed at a position overlapping the field plate 12. Also in this case, a plurality of contact holes are formed for each of the metal films 16a, 16b, 16c, 16d and the field plate 12.

Subsequently, as shown in FIGS. 2 (g) and 3 (g), W is deposited using the CVD method to form contacts 14a, 14b, 14c, 14d, and 14e that fill the contact holes. Next, an Al layer is formed on the second interlayer insulating film 13 using the CVD method or the sputtering method, and then the Al layer is etched according to the wiring pattern, thereby forming the metal films 17a, 17b, 17c, and 17d at the same time. To do. Here, the metal film 17b covers the entire upper portion of the field plate 12 and the entire upper portion of the gate electrode 5, and is connected to a pad (not shown) or the like in a later step. A part of the metal film 17 b also extends above the source region 8 and is connected to the source region 8. The metal film 17d is formed at a position (between the source region 8 and the p ⁺ substrate region 9) across the source region 8 when viewed from the gate electrode 5, and is connected to a pad for supplying a gate potential in a later process. Is done.

  According to the above method, the field plate 12 for reducing the strength of the electric field generated between the gate and the drain can be formed simultaneously with the metal films 16a, 16b, 16c, and 16d in the first wiring layer. The MOS transistor of this embodiment can be manufactured with the same number of steps as that of the MOS transistor.

4A and 4B are views showing a contact structure in the semiconductor device of this embodiment. In the MOS transistor of this embodiment, as shown in FIG. 4A and FIGS. 1A to 1C, each of the drain region 7, the gate electrode 5, the p ⁺ substrate region 9, and the field plate 12 is used. A plurality of contacts for connecting the metal film disposed above them were provided, but as shown in FIG. 4B, each portion was embedded in one groove long in the gate width direction. Contact may be formed. The width of the contact in the gate width direction may be at least longer than the width in the gate length direction, and may be about the same as the gate width of the MOS transistor, for example. In this case, since the planar area of the contact is increased, the resistance at the contact connecting the wiring layers can be further reduced, and the high frequency characteristics of the MOS transistor can be further improved.

  1A to 1C show an example in which the metal film 17b formed in the second wiring layer and connected to the field plate 12 also extends above the source region 8. The metal film connected to the region 8 and the metal film connected to the field plate 12 may be provided separately in the second wiring layer. In this case, the capacitance generated between the gate and the drain can be effectively reduced by connecting the field plate 12 to a pad for supplying a ground potential.

1A to 1C, a p ⁺ substrate region 9 for grounding the semiconductor substrate 1 is provided adjacent to the element isolation insulating film 3, but the p ⁺ substrate region 9 is a semiconductor. It can be provided at any position in the substrate 1. In the MOS transistor of this embodiment, the metal films 16a and 17a and the contacts 11a and 14a for grounding the p ⁺ substrate region 9 are provided above the semiconductor substrate 1. Alternatively, the semiconductor substrate 1 may be connected to the ground from the back surface side by continuously introducing impurities from the back surface to the back surface.

  FIG. 5A is a plan view showing a wiring layout in the semiconductor device according to the first modification of the first embodiment, and FIG. 5B is a wiring in the semiconductor device according to the second modification. It is a top view which shows a layout.

  In the semiconductor device according to the first modification shown in FIG. 5A, the metal in the second wiring layer connected to the field plate 12 (see FIG. 1) is compared with the semiconductor device of the first embodiment. The film 17b does not cover the region between the field plate 12 and the gate electrode 5 (or the metal film 16c). When the metal film 17b is connected to the source region 8, a capacitance is also generated in the portion of the metal film 17b disposed near the upper portion of the gate electrode 5, so that the metal film 17b is shaped as in this modification. As a result, the capacitance generated between the gate and the source can be further reduced.

  Further, as shown in FIG. 5B, when the metal film 17 b is connected to the source region 8, the metal film 17 b does not necessarily have to cover the entire upper portion of the gate electrode 5. The smaller the region where the metal film 17b and the gate electrode 5 overlap in plan view, the smaller the capacitance generated between the gate and the source.

  1A to 1C show an example in which the MOS transistor is an n-channel type, the high-frequency characteristics are improved by using the above-described wiring layout even when the MOS transistor is a p-channel type. be able to.

(Second Embodiment)
FIG. 6 is a plan view showing a wiring layout in the MOS transistor according to the second embodiment of the present invention. 7 is a cross-sectional view of the MOS transistor according to the second embodiment taken along line VII-VII shown in FIG. 6, and FIG. 8 is a cross-sectional view taken along line VIII-VIII of the MOS transistor according to the second embodiment. FIG.

  In the MOS transistor of the present embodiment, a metal film 17b connected to the field plate 12 and provided in the second wiring layer is disposed above the source region 8, and via the contact 11b, the metal film 16b, and the contact 14b. Are connected to the source region 8. Further, as shown in FIG. 6, the planar shape of the metal film 17b is rectangular, and the length of the portion covering the source region 8 in the gate width direction (vertical direction in FIG. 6) is the gate electrode 5 and The length of the portion provided above the field plate 12 is equal to the length in the gate width direction. The configuration and wiring layout of the drain region 7 and the source region 8, each well, the gate electrode 5 and the gate insulating film 4 are the same as those of the MOS transistor according to the first embodiment.

  However, in the MOS transistor of the present embodiment, the source region 8 and the field plate 12 provided in the first wiring layer are electrically connected, and the field is generated when the source region 8 is at the ground potential. There is no need to provide a pad (for example, a ground potential supply pad) connected to the plate 12.

  Further, in the MOS transistor of this embodiment, like the MOS transistor of the first embodiment, the metal film 17b provided in the second wiring layer and connected to the field plate 12 is seen in plan view in the gate electrode 5. And the drain region 7. Thereby, the electric field generated between the gate and the drain can be relaxed. For this reason, in the MOS transistor of this embodiment, the capacitance generated between the gate and the drain is reduced.

  Further, since the metal film 16c provided in the first wiring layer covers the entire upper portion of the gate electrode 5, it is possible to provide a plurality of contacts 11c for connecting the metal film 16c and the gate electrode 5. Become. Therefore, the resistance between the metal film 16c and the gate electrode 5 can be reduced, and high frequency characteristics can be improved.

  Further, since the wiring (metal films 16c and 17d) connected to the gate electrode 5 is drawn out to the source side instead of the drain side, it is possible to reduce the capacitance generated between the wirings.

  The MOS transistor of this embodiment can be manufactured by the same method as the MOS transistor according to the first embodiment. Specifically, after the steps shown in FIGS. 2A to 2F, in the step shown in FIG. 2G, the metal film 17b is etched so that the shape of the metal film 17b becomes a rectangle. A transistor can be manufactured.

In the MOS transistor of this embodiment, as in the MOS transistor of the first embodiment, a contact 11c that connects the gate electrode 5 and the metal film 16c, a contact 14c that connects the field plate 12 and the metal film 17b, contact 11d for connecting the drain region 7 and the metal film 17c, 14d, ^{p +} substrate region 9 and the metal film 17a and the contact 11a for connecting may be provided a plurality each of 14a, One contact that is long in the gate width direction may be used. In particular, when each of these contacts is composed of one contact, the contact resistance can be reduced and the high-frequency characteristics can be improved.

  FIGS. 9A to 9C are plan views showing wiring layouts in other modifications of the MOS transistor of this embodiment.

  As shown in FIG. 9A, by rounding the corner portion of the field plate 12, the capacitance generated between the metal film connected to the gate electrode and the field plate, that is, the capacitance generated between the gate and the source is reduced. Therefore, high frequency characteristics can be improved.

  Further, as shown in FIG. 9B, the capacitance generated between the gate and the source can also be reduced by rounding the corners of the metal film 17b connected to the field plate 12 and the source region 8, and the high frequency characteristics. Can be improved.

  Alternatively, as shown in FIG. 9C, the capacitance can be further reduced by further rounding the corner portion of the field plate 12 and the corner portion of the metal film 17b, thereby further improving the high-frequency characteristics.

(Third embodiment)
FIG. 10A is a plan view showing a wiring layout in a MOS transistor according to the third embodiment of the present invention, and FIG. 10B shows a wiring layout in a modification of the MOS transistor according to the third embodiment. FIG. FIG. 11 is a view showing a cross section of the MOS transistor taken along line XI-XI shown in FIG.

The MOS transistor of this embodiment is different from the MOS transistors of the first and second embodiments in that the field plate 12, the source region 8, and the p ⁺ substrate region 9 are the first wiring layer and the second wiring layer. It is electrically connected through metal films 17b, 16a, and 16b provided inside. With this configuration, when the source region 8 and the p ⁺ substrate region 9 are at the ground potential, it is not necessary to connect to the pad for supplying the field plate 12 with the ground potential. Also, the MOS transistor of this embodiment has excellent high-frequency characteristics because the gate-drain capacitance and the resistance of the gate electrode 5 and its wiring are reduced like the MOS transistors of the first and second embodiments. Have.

  In the MOS transistor of the present embodiment, a plurality of contacts 11a, 11c, 11d, 14a, 14c, and 14d may be provided, as in the MOS transistors of the first and second embodiments. Each may be composed of one contact long in the gate width direction. In particular, when each of these contacts is composed of one contact, the contact resistance can be reduced and the high-frequency characteristics can be improved.

  In addition, the MOS transistor of this embodiment can be manufactured by the same method as the first and second MOS transistors.

As shown in FIG. 10B, the metal film 17b connected to the source region 8, the field plate 12, and the p ⁺ substrate region 9 does not overlap with the metal film 16c connected to the gate electrode 5 in a plan view. You may do it. Thereby, the capacitance generated between the gate and the source can be reduced, and the high frequency characteristics can be further improved.

  Further, in the MOS transistor of the present embodiment, the capacitance is further reduced by rounding at least one corner of the field plate 12 or the metal film 17b as in the MOS transistors shown in FIGS. The high frequency characteristics can be further improved.

  Further, the MOS transistor of this embodiment is provided in the second wiring layer and connected to the field plate 12 provided in the first wiring layer, like the MOS transistors of the first and second embodiments. The metal film 17b is disposed between the gate electrode 5 and the drain region 7 in plan view. Thereby, the electric field generated between the gate and the drain can be relaxed. For this reason, in the MOS transistor of this embodiment, the capacitance generated between the gate and the drain is reduced.

  Further, since the metal film 16c provided in the first wiring layer covers the entire upper portion of the gate electrode 5, it is possible to provide a plurality of contacts 11c for connecting the metal film 16c and the gate electrode 5. Become. Therefore, the resistance between the metal film 16c and the gate electrode 5 can be reduced, and high frequency characteristics can be improved.

  Further, since the wiring (metal films 16c and 17d) connected to the gate electrode 5 is drawn out to the source side instead of the drain side, it is possible to reduce the capacitance generated between the wirings.

    (Fourth embodiment).

  12A and 12B are cross-sectional views showing a MOS transistor according to the fourth embodiment of the present invention. FIG. 12A shows a cross section of the MOS transistor of this embodiment along a line corresponding to the Ib-Ib line (see FIG. 1A) of the MOS transistor according to the first embodiment. ) Shows a cross section of the MOS transistor of the present embodiment along a line corresponding to the Ic-Ic line of the MOS transistor according to the first embodiment.

  The MOS transistor according to this embodiment is the same as the MOS transistor according to the first embodiment, in which a third interlayer insulating film 25 is further provided between the first interlayer insulating film 10 and the second interlayer insulating film 13, and Al One wiring layer for arranging the wiring is further formed.

In the MOS transistor of this embodiment, the metal film 26a connected to the p ⁺ substrate region 9 through the contact 21a, the metal film 26b connected to the source region 8 through the contact 21b, and the field plate 12 through the contact 21c. A metal film 26c connected to the gate electrode 5, a metal film 26d connected to the drain region 7 through the contact 21d, and a metal film 26e connected to the gate electrode 5 through the contact 21e are disposed in the second wiring layer. Yes. Further, the metal film 17 a connected to the p ⁺ substrate region 9, the field plate 12, and the source region 8, and the metal film provided from above the gate electrode 5 to the drain region 7 to above the source region 8. 17b, the metal film 17c connected to the drain region 7, and the metal film 17d connected to the gate electrode 5 are disposed in the third wiring layer.

  As a result, the distance between the gate electrode 5 and the metal film 16c connected to the gate electrode 5 and the metal film 17b connected to the field plate 12 is wider than that of the MOS transistor of the first embodiment. The capacitance generated between 16c and the metal film 17b can be reduced, and the high frequency characteristics can be improved.

  A plurality of contacts 21a, 21b, 21c, and 21d may be provided, or a single contact that is long in the gate width direction. With this configuration, the resistance in each wiring can be reduced as compared with the case where the contacts 21a, 21b, 21c, and 21d are configured with only one small contact. As a result, the high frequency characteristics can be improved as in the first to third embodiments while reducing the capacitance between the gate electrode 5 and the metal film 17b.

  The semiconductor device and the manufacturing method thereof of the present invention are useful, for example, for a power amplifier circuit of a wireless communication device that handles high frequencies.

(A) is a top view which shows the wiring layout in the MOS transistor which concerns on the 1st Embodiment of this invention, (b) is a figure which shows the cross section in the Ib-Ib line | wire of the said MOS transistor, (c ) Is a diagram showing a cross section of the MOS transistor taken along line Ic-Ic. (A)-(g) is sectional drawing which shows the manufacturing method of the MOS transistor which concerns on 1st Embodiment. (A)-(g) is sectional drawing which shows the manufacturing method of the MOS transistor which concerns on 1st Embodiment. (A), (b) is a figure which shows the contact structure in the MOS transistor which concerns on 1st Embodiment. (A) is a top view which shows the wiring layout in the semiconductor device which concerns on the 1st modification of 1st Embodiment, (b) is a plane which shows the wiring layout in the semiconductor device which concerns on a 2nd modification. It is a figure It is a top view which shows the wiring layout in the MOS transistor which concerns on the 2nd Embodiment of this invention. It is a figure which shows the cross section in the VII-VII line shown in FIG. 6 of the MOS transistor which concerns on 2nd Embodiment. It is a figure which shows the cross section in the VIII-VIII line shown to Fig.6 (a) of the MOS transistor which concerns on 2nd Embodiment. (A)-(c) is a top view which shows the wiring layout in the modification of the MOS transistor which concerns on 2nd Embodiment. (A) is a top view which shows the wiring layout in the MOS transistor which concerns on the 3rd Embodiment of this invention, (b) is a figure which shows the wiring layout in the modification of the MOS transistor which concerns on 3rd Embodiment. It is. It is a figure which shows the cross section in the XI-XI line | wire shown to Fig.10 (a) of the MOS transistor which concerns on 3rd Embodiment. (A), (b) is sectional drawing which shows the MOS transistor which concerns on the 4th Embodiment of this invention. It is sectional drawing which shows the conventional semiconductor device provided with the field plate.

Explanation of symbols

1 Semiconductor substrate 2 n ^- type well layer
3 Insulating film for element isolation
4 Gate insulation film
5 Gate electrode
6 p ^- type well layer
7 Drain region
8 Source area
9 p ⁺ substrate area
10 First interlayer insulating film
11a, 11b, 11c, 11d contact
14a, 14b, 14c, 14d, 14e Contact
12 Field plate
13 Second interlayer insulating film
16a, 16b, 16c, 16d Metal film
17a, 17b, 17c, 17d Metal film
21a, 21b, 21c, 21d, 21e Contact
25 Third interlayer insulating film
26a, 26b, 26c, 26d, 26e Metal film

Claims (23)

A semiconductor substrate;
A gate electrode formed on the semiconductor substrate with a gate insulating film interposed therebetween;
A source region including an impurity formed on a side of the gate electrode in the semiconductor substrate;
The semiconductor substrate is formed on a side opposite to the source region as viewed from the gate electrode and at a position away from the gate electrode in the gate length direction, and includes impurities of the same conductivity type as the source region. A drain region;
A first interlayer insulating film formed on the semiconductor substrate and the gate electrode;
A second interlayer insulating film formed on or above the first interlayer insulating film;
A field plate made of metal formed on the first interlayer insulating film and between the gate electrode and the drain region;
A first metal film connected to the gate electrode and formed on the first interlayer insulating film at a position at least partially overlapping the gate electrode in plan view;
A second metal film connected to the field plate and formed on the second interlayer insulating film and at least partially overlapping the field plate in plan view;
A first contact connecting the gate electrode and the first metal film;
A semiconductor device comprising: a second contact connecting the field plate and the second metal film.   2. The semiconductor device according to claim 1, wherein the field plate and the first metal film are formed simultaneously.   The semiconductor device according to claim 1, wherein the first metal film covers the entire upper portion of the gate electrode.   The semiconductor device according to claim 1, wherein a plurality of the first contacts are provided.   The semiconductor device according to claim 1, wherein the first contact has a width in the gate width direction larger than a width in the gate length direction.   6. The device according to claim 1, wherein the second metal film extends to the upper side of the source region over the gate electrode and is connected to the source region. The semiconductor device described. A substrate region that is formed in a part of the semiconductor substrate and includes impurities of a conductivity type different from that of the source region and the drain region;
The semiconductor device according to claim 6, wherein the second metal film is further connected to the substrate region.   The semiconductor device according to claim 1, wherein the first metal film extends from above the gate electrode so as to straddle the source region.   9. The method according to claim 1, further comprising at least one third interlayer insulating film disposed between the first interlayer insulating film and the second interlayer insulating film. The semiconductor device according to one.   The semiconductor device according to claim 1, wherein the field plate has a rounded corner portion.   The semiconductor device according to claim 1, wherein the second metal film has a rounded corner portion.   The semiconductor device according to claim 1, wherein the second metal film covers the entire upper portion of the field plate.   The semiconductor device according to claim 1, wherein a plurality of the second contacts are provided.   14. The semiconductor device according to claim 1, wherein the second contact has a width in the gate width direction larger than a width in the gate length direction. After forming the gate insulating film and the gate electrode on the semiconductor substrate, the first conductivity type impurity is introduced into a part of the semiconductor substrate, and the source region is seen from the gate electrode in a region located on the side of the gate electrode. Forming a drain region in a region on the side opposite to the source region and away from the gate electrode in the gate length direction;
After the step (a), a step (b) of forming a first interlayer insulating film on the semiconductor substrate;
Forming one or more first contacts connected to the gate electrode and penetrating through the first interlayer insulating film;
A field plate formed at a position between the gate electrode and the drain region, and connected to the gate electrode via the first contact, and at a position where at least a part thereof overlaps with the gate electrode when seen in a plan view A step (d) of simultaneously forming the formed first metal film on the first interlayer insulating film;
Forming a second interlayer insulating film on or above the first interlayer insulating film (e);
Forming a second metal film on the second interlayer insulating film, the second metal film being connected to the field plate and overlapping the field plate at least partially in plan view; Manufacturing method. In the step (c), a plurality of first contacts are formed,
16. The method of manufacturing a semiconductor device according to claim 15, wherein in the step (d), the first metal film is formed so as to cover the entire upper portion of the gate electrode.   16. The method of manufacturing a semiconductor device according to claim 15, wherein the second contact formed in the step (c) has a width in the gate width direction larger than a width in the gate length direction.   16. The second metal film formed in the step (f) extends over the source region over the gate electrode and is connected to the source region. 18. A method for manufacturing a semiconductor device according to claim 1. Prior to the step (b), the method further includes a step (g) of introducing a second conductivity type impurity into a part of the semiconductor substrate to form a substrate region,
19. The method for manufacturing a semiconductor device according to claim 18, wherein the second metal film formed in the step (f) is further connected to the substrate region.   20. The semiconductor according to claim 15, wherein in the step (d), the first metal film is formed so as to straddle the source region from above the gate electrode. Device manufacturing method.   A step (h) of forming a third interlayer insulating film on the first interlayer insulating film is further provided after the step (d) and before the step (e). The method for manufacturing a semiconductor device according to claim 15.   The semiconductor device according to any one of claims 15 to 21, wherein the first metal film formed in the step (d) has a rounded corner portion. Method.   23. The method of manufacturing a semiconductor device according to claim 15, wherein the second metal film formed in the step (f) has a rounded corner portion. Method.

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