JP2000340683A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce resistance of a power element and increase withstanding voltage of a peripheral circuit at the same time in a semiconductor device, which has a power semiconductor element and a peripheral circuit for the power semiconductor element formed on one and the same semiconductor substrate. SOLUTION: A semiconductor device, wherein a power semiconductor element and a semiconductor element for a circuit which constitutes a peripheral circuit of the power semiconductor element are formed on one and the same semiconductor substrate, is insulated and isolated. In such a semiconductor device, embedded regions 16, 17 are formed on a semiconductor base substrate 1 via an insulation film 3 and an active layer 2 is formed on the buried regions 16, 17. In the active layer 2, the power semiconductor element and the semiconductor element for a circuit are formed. The height of the embedded region 16 on the power semiconductor element side is larger than that of the embedded region 17 on the side of the semiconductor element for circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which a power semiconductor element and its peripheral circuit are formed on the same semiconductor substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, power semiconductor devices (power devices)
And a semiconductor device in which a peripheral circuit for driving the power element, for example, is formed on the same semiconductor substrate. This semiconductor device will be described with reference to FIG.
This semiconductor device uses a horizontal MOSFET as a power element.
(Hereinafter referred to as LDMOSFET), and an NPN bipolar transistor is formed as a peripheral circuit.

[0003] Reference numeral 1 denotes a semiconductor support substrate, on which an N-type silicon active layer 2 as an active region is formed via an oxide film 3 to form a so-called SOI structure. A groove is formed in the silicon active layer 2 from the surface to the oxide film 3. The groove is filled with polysilicon 8 via an oxide film 6 formed on the side and bottom surfaces, which will be described later. The element formation regions 4 and 5 are insulated from each other. On the oxide film 3, a high concentration N + type buried region 7 is formed at the same depth over the element regions 4 and 5.

Next, an element forming region 4 in which an LDMOSFET as a power element is formed will be described. Reference numeral 10 denotes a P-type well region formed on the surface of the active layer 2, and an N + -type source region 9 is formed on the surface of the P-type well region 10. Also, a P-type well region 1 on the surface of the active layer 3
0 is not formed in the N + type drain region 1
1 are formed from the surface of the P-type well region 10 to the N + buried region 7. Reference numeral 14 denotes an insulating film formed on the active layer 2, and a gate electrode 13 made of polysilicon is formed on the P-type well region 10 where the source region 9 is not formed via the insulating film 14. ing. Further, the source region 9, the drain region 11, and the gate electrode 13 are connected to a source wiring 30, a drain wiring 28, and a gate wiring 29 made of aluminum via openings on the insulating film 14, respectively.

Next, the operation will be described. In the state where a predetermined voltage is applied between the drain wiring 28 and the source wiring 30 and a voltage higher than the threshold voltage is applied to the gate wiring 29, the well region immediately below the gate electrode 13 is formed. A channel 12 is formed on the surface 10, and a current flows from the drain region 11 to the N + buried region, the active layer 2, the channel 12, and the source region 9 to turn on as a transistor.

Next, an element forming region 5 in which a bipolar transistor as a peripheral circuit is formed will be described.
Reference numeral 22 denotes an N-type collector region made of the silicon active layer 2, and a P-type base region 23 is formed on the surface of the collector region 22. On the surface of the P-type base region 23, an N + -type emitter region 24 and a P + -type base contact region 31 are formed. On the surface of the collector region 22, an N + type collector contact region 21 is formed. These N + type collector contact regions 2
7, P + type base. The contact region 31 and the N + -type emitter region 24 are formed through an opening formed in the insulating film 14.
Collector wiring 27, base wiring 26, emitter wiring 25
And are connected respectively.

In the semiconductor device thus configured, the LDMOSFET formed in the element forming region 4 is
The shorter the depth of the N + type drain region 11, that is, the shorter the distance between the bottom surface of the P type well region 10 and the surface of the N + type buried region 7, the shorter the current path, so that the on-resistance can be reduced. . The withstand voltage between the base and the collector of the bipolar transistor formed in the element formation region 5 should be increased as the distance between the bottom surface of the base region 23 and the surface of the N + type buried region 7 increases. Can be.

[0008]

However, in the conventional semiconductor device, since the N + type buried region 7 is formed in the same step, the depth of the N + type buried region 7 is reduced. 5, the depth becomes constant, and the low resistance of the power element formed in the element forming region 4 and the element forming region 5
It is difficult to achieve both the high withstand voltage of the peripheral circuit formed at the same time.

In view of the above problems, the present invention provides a semiconductor device in which a power element and a peripheral circuit of the power element are formed on the same semiconductor substrate.
It is an object of the present invention to provide a semiconductor device capable of achieving both high withstand voltage of a peripheral circuit and a method of manufacturing the same.

[0010]

According to a first aspect of the present invention, there is provided a buried region formed on a semiconductor support substrate via an insulating film, and a buried region formed on the buried region. The active layer, a groove formed from the surface of the active layer to the insulating film, and filling the groove with at least an insulator to insulate and separate the active layer into a first active layer and a second active layer. An insulating isolation region, a power buried region formed at the bottom of the first active layer, and a circuit buried region formed at the bottom of the second active layer and lower than the height of the power buried region. The power semiconductor device is formed on the surface of the first active layer, and the circuit semiconductor device is formed on the surface of the second active layer.

Further, in the invention according to claim 2, a step of forming an insulating film on the first semiconductor substrate, a step of forming a groove from the back surface of the second semiconductor substrate, and filling the groove with at least an insulator A step of insulating and separating the first active layer and the second active layer; a step of implanting a first impurity having a predetermined diffusion constant into the back surface of the first active layer; Implanting a second impurity having a low constant;
First and second implanted into the first and second active layers, respectively.
A step of diffusing impurities; a first semiconductor substrate surface;
The method includes a step of joining a surface of a semiconductor substrate, a step of forming a power semiconductor element on the first active layer, and a step of forming a circuit semiconductor element on the second active layer.

According to a third aspect of the present invention, a step of forming an insulating film on the first semiconductor substrate, a step of forming a groove from the back surface of the second semiconductor substrate, and filling the groove with at least an insulator A step of isolating the first active layer and the second active layer, a step of injecting a first impurity into the back surface of the first active layer at a predetermined acceleration voltage, and a step of implanting the first impurity into the back surface of the second active layer. Implanting a second impurity having a low accelerating voltage; diffusing the first and second impurities implanted into the first and second active layers, respectively; It consisted of a step of bonding to the surface, a step of forming a power semiconductor element on the first active layer, and a step of forming a circuit semiconductor element on the second active layer.

[0013]

According to the first aspect of the present invention, the active layer is insulated and separated into the first active layer and the second active layer by the insulating separation region, and a power buried region is formed at the bottom of the first active layer. A circuit buried region lower than the power buried region is formed at the bottom of the second active layer; a power semiconductor element is formed on the surface of the first active layer; Since the configuration is such that the circuit semiconductor element is formed, in a semiconductor device in which the power semiconductor element and the peripheral circuit of the power semiconductor element are formed on the same semiconductor substrate, the low resistance of the power semiconductor element, The high withstand voltage of the peripheral circuit can be easily compatible.

According to the second aspect of the present invention, the step of insulatingly separating the active layer into a first active layer and a second active layer;
Implanting a first impurity having a predetermined diffusion constant into the back surface of the active layer, implanting a second impurity having a lower diffusion constant than the first impurity into the back surface of the second active layer, and implanting a first impurity into the first and second active layers. Diffusing the implanted first and second impurities, joining the first semiconductor substrate surface and the second semiconductor substrate surface, and forming a power semiconductor element on the first active layer; Forming a circuit semiconductor element on the second active layer, the power semiconductor element and a peripheral circuit of the power semiconductor element are formed on the same semiconductor substrate. It is possible to provide a method of manufacturing a semiconductor device capable of easily achieving both low resistance of an element and high withstand voltage of a peripheral circuit.

Further, in the invention according to claim 3, a step of insulatingly separating the active layer into a first active layer and a second active layer;
Implanting a first impurity into the back surface of the active layer with a predetermined acceleration voltage, implanting a second impurity into the back surface of the second active layer with an acceleration voltage lower than the first impurity, and implanting a first impurity into the first and second active layers. Diffusing the implanted first and second impurities, joining the first semiconductor substrate surface and the second semiconductor substrate surface, and forming a power semiconductor element on the first active layer; Forming a circuit semiconductor element on the second active layer, the power semiconductor element and a peripheral circuit of the power semiconductor element are formed on the same semiconductor substrate. It is possible to provide a method of manufacturing a semiconductor device capable of easily achieving both low resistance of an element and high withstand voltage of a peripheral circuit.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view showing a configuration of a semiconductor device of the present invention. This semiconductor device has a lateral MOSFET (hereinafter, LDMOSFE) as a power element.
T), an NPN bipolar transistor is formed as a peripheral circuit.

Reference numeral 1 denotes a semiconductor support substrate, on which an N-type silicon active layer 2 as an active region is formed via an oxide film 3 to form a so-called SOI structure. A groove is formed in the silicon active layer 2 from the surface to the oxide film 3. The groove is filled with polysilicon 8 via an oxide film 6 formed on the side and bottom surfaces, which will be described later. The element formation regions 4 and 5 are insulated from each other. The oxide film 6 and the polysilicon 8 form an insulating isolation region. A high-concentration N + -type buried region 16 is formed on the oxide film 3 in the element formation region 4, and a high-concentration N + -type buried region 17 is formed on the oxide film 3 in the element formation region 5. . The height of the N + type buried region 16 formed in the element formation region 4 is
It is formed higher than the height of the + type buried region 17.

Next, the element formation region 4 where the LDMOSFET as a power element is formed will be described. The active layer 2 in the element formation region 4 corresponds to a first active layer in the claims. Reference numeral 10 denotes a P-type well region formed on the surface of the active layer 2, and an N + -type source region 9 is formed on the surface of the P-type well region 10. In a portion of the surface of the active layer 2 where the P-type well region 10 is not formed, an N + -type drain region 11 is formed from the surface of the P-type well region 10 to the oxide film 3. Reference numeral 14 denotes an insulating film formed on the active layer 2, and a portion of the P-type well region 10 where the source region 9 is not formed is an insulating film 1
4, a gate electrode 13 made of polysilicon is formed. On the source region 9, the drain region 11, and the gate electrode 13, the source line 30, the drain line 28, and the gate line 29 made of aluminum are connected via openings on the insulating film 14, respectively.

Next, the operation will be described. In the state where a predetermined voltage is applied between the drain wiring 28 and the source wiring 30, when a voltage equal to or higher than the threshold voltage is applied to the gate wiring 29, the P A channel 12 is formed on the surface of the well region 10 and a current is applied to the N + type drain region 11.
Flows from the N + -type buried region 16, the active layer 2, the channel 12, and the source region 9 to turn on as a transistor.

Next, a description will be given of the element forming region 5 in which a bipolar transistor as a peripheral circuit is formed.
The active layer 2 in the element formation region 5 corresponds to a second active layer in the claims. Reference numeral 22 denotes an N-type collector region made of the silicon active layer 2;
A P-type base region 23 is formed on the surface. On the surface of the P-type base region 23, an N + -type emitter region 24,
A P + type base contact region 31 is formed.
An N + -type collector contact region 21 is formed on the surface of the N-type collector region 22. These N +
Collector contact region 21, P + type base contact region 31, and N + type emitter region 24
4 are connected to the collector wiring 27, the base wiring 26, and the emitter wiring 25, respectively, through the openings formed in the wiring 4.

Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. First, an oxide film 3 as an insulating film is formed on the entire surface of a semiconductor support substrate 1 serving as a support substrate by thermal oxidation or the like (FIG. 2).

Next, a plurality of grooves are formed from the surface of another semiconductor substrate different from the semiconductor support substrate 1, and an oxide film 6 is formed on the bottom and side surfaces of the grooves. Thereafter, polysilicon 8 is deposited in grooves formed on the bottom and side surfaces of oxide film 6, and the surface is flattened by etch back. Thus, the element isolation regions 4 and 5 are insulated and separated (FIG. 3).

Next, phosphorus 36 (corresponding to a first impurity), which is an N-type impurity, is ion-implanted into a region to be the element forming region 4 (FIG. 4).

Next, arsenic 37 (corresponding to a second impurity), which is an N-type impurity, is ion-implanted into a region to be the element isolation region 5.

Next, heat treatment is performed on the entire substrate into which the phosphorus 36 and the arsenic 37 have been ion-implanted, and thermal diffusion is performed. During this heat treatment, the phosphorus 36 implanted in the element formation region 4 and the arsenic 37 implanted in the element formation region 5 have different diffusion constants in the silicon crystal. Since the diffusion progresses faster than the arsenic 37 formed in the element formation region 5, the N + type buried region 16 formed by this heat treatment is formed higher than the N + type buried region 17. (FIG. 5).

Next, the surfaces of the support substrate formed in the step of FIG. 2 and the substrate formed in the steps of FIGS. 3 to 5 are joined together. Next, by polishing the surface of the region to be the active layer 2, the polysilicon 8 is exposed, and the back surface of the semiconductor supporting substrate 1 is polished to a predetermined thickness (FIG. 6).

Next, a P-type well region 10 and an N + -type drain region 11 constituting an LDMOSFET are formed in the element isolation region 4.
, An N + type source region and a well potential fixed region 33, and a base region 23, a P + type base contact region 31, an emitter region 24, and an N + type collector contact region 21 constituting a bipolar transistor are formed in the element isolation region 5. I do. Thereafter, an insulating film 14 is formed on the surface of the active layer 2, and a gate electrode 13 and wirings 25 to 30 are formed (FIG. 7).

As described above, in the present embodiment, the impurities 36 and 37 having different diffusion constants for each of the element formation regions 4 and 5.
Are implanted to form the buried regions 16 and 17. Therefore, in the device forming region 4 where the LDMOSFET as a power device is formed, the N + -type buried region 16 is formed high to reduce the resistance. In the element formation region 5 where the bipolar transistor, which is a peripheral circuit, is formed, the N + -type buried region 17 is formed low, so that a high breakdown voltage transistor can be obtained. . Also, compared to the conventional manufacturing method, only the number of steps for separately implanting impurities is increased, and excellent effects can be obtained with small changes.

In the ion implantation shown in FIGS. 4 and 5, phosphorus 36 and arsenic 37 are implanted as impurities.
Impurities such as antimony may be used.
An impurity having a different diffusion constant for obtaining a height of 17 may be selected and implanted. Further, in the present embodiment, the depth of the buried regions 16 and 17 is changed by changing the material of the impurity to be diffused. However, the impurity is, for example, one kind of phosphorus, and the acceleration voltage is increased in the element forming region 4. The ion implantation may be performed by lowering the acceleration voltage in the element formation region 5. Alternatively, the height of the buried regions 16 and 17 may be changed by performing ion implantation of silicon or the like on one side to form a crystal defect and then performing ion implantation on both sides under the same conditions.

In this embodiment, the LDMOS
Although the description has been given by taking the FET and the bipolar transistor as examples, the present invention is not limited to this.
It is needless to say that the same effect can be obtained even with such an element.

Although the preferred embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this preferred embodiment, and a design change or the like may be made without departing from the gist of the present invention. Even if present, it is included in the present invention.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing method according to the embodiment of the present invention.

FIG. 3 is a diagram showing a manufacturing method according to the embodiment of the present invention.

FIG. 4 is a diagram showing a manufacturing method according to the embodiment of the present invention.

FIG. 5 is a diagram showing a manufacturing method according to the embodiment of the present invention.

FIG. 6 is a diagram showing a manufacturing method according to the embodiment of the present invention.

FIG. 7 is a diagram showing a manufacturing method according to the embodiment of the present invention.

FIG. 8 is a diagram illustrating a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor support base 2 Silicon active layer 3 Oxide film 4 Element formation region 5 Element formation region 6 Oxide film 7 N + type buried region 8 Polysilicon 9 Source region 10 P type well region 11 N + type drain region 12 Channel 13 Gate electrode 14 Insulating film 16 N + type buried region 17 N + type buried region 21 N + type collector / contact region 22 N type collector region 23 P type base region 24 N + type emitter region 25 Emitter electrode 26 Base electrode 27 Collector wiring 28 drain wiring 29 gate wiring 30 source wiring 31 P + type base / contact region 36 phosphorus 37 arsenic

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F032 AA09 AA16 AA35 AA47 CA01 CA03 CA17 CA18 CA24 CA25 DA34 DA78 5F048 AA05 AC07 BA09 BA12 BA16 BB01 BB05 BC03 BC07 BD07 BF02 BG13 BG14 CA04 CA07

Claims (3)

[Claims] A buried region formed on a semiconductor support substrate via an insulating film; an active layer formed on the buried region; and an active layer formed from the surface of the active layer to reach the insulating film. A groove, an insulating isolation region that insulates and separates the active layer into a first active layer and a second active layer by filling the groove with at least an insulator, and a power supply formed at the bottom of the first active layer. A buried region and a circuit buried region formed at the bottom of the second active layer and lower than the height of the power buried region, wherein the power semiconductor is provided on the surface of the first active layer. An element is formed, and the circuit semiconductor element is formed on a surface of the second active layer. 2. A step of forming an insulating film on a first semiconductor substrate, a step of forming a groove from a back surface of the second semiconductor substrate,
Filling the trench with at least an insulator to insulate and separate the first active layer and the second active layer; implanting a first impurity having a predetermined diffusion constant into the back surface of the first active layer; Implanting a second impurity having a lower diffusion constant than the first impurity into the back surface of the active layer; diffusing the first and second impurities implanted into the first and second active layers, respectively; (I) bonding a semiconductor substrate surface to the surface of the second semiconductor substrate; forming a power semiconductor element on the first active layer; and forming a circuit semiconductor element on the second active layer. And a method for manufacturing a semiconductor device comprising: A step of forming an insulating film on the first semiconductor substrate; and a step of forming a groove from the back surface of the second semiconductor substrate.
Filling the groove with at least an insulator to insulate and separate the first active layer and the second active layer, and implanting a first impurity into the back surface of the first active layer at a predetermined acceleration voltage;
Implanting a second impurity having a lower acceleration voltage than the first impurity into the back surface of the second active layer, and diffusing the first and second impurities implanted into the first and second active layers, respectively; Bonding a surface of the first semiconductor substrate to a surface of the second semiconductor substrate, forming a power semiconductor element on the first active layer, and forming a circuit semiconductor element on the second active layer. Forming a semiconductor device.