JP3161091B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to an insulated gate field effect transistor (hereinafter referred to as a MOSFET) for supplying a current from a first principal surface to a second principal surface of a semiconductor substrate. ) And a power IC in which a control circuit for controlling the MOSFET is provided on the same semiconductor chip (semiconductor substrate).

[0002]

2. Description of the Related Art FIG. 4 shows a cross section of an example of a conventional semiconductor integrated circuit of this kind. A P ⁻ -type silicon epitaxial layer 25 is formed on an N ⁺ -type silicon substrate 3 having a high impurity concentration, and an N ⁺ -type buried layer 26 is formed in the P ⁻ -type epitaxial layer 25. Further, an N ⁻ type silicon epitaxial layer 27 is formed on the P ⁻ type epitaxial layer 25.
Is formed, and a P ⁺ -type diffusion layer 28 for element isolation is formed penetrating through the N ⁻ -type epitaxial layer 27. N
^The N ⁻ -type epitaxial layer 27 is electrically separated into island-like regions 27a, 27b, 27c by reverse-biasing the −-type epitaxial layer 27 and the P ⁺ -type diffusion layer 28. In a region 27a of the N ⁻ -type epitaxial layer 27, a P ⁺ -type collector 4 and a P ⁺
-Type emitter 5 has a N ⁺ -type base contact portion 6 N ^-
A PNP bipolar transistor 36 based on the surface of the mold region 27a is formed as one of the elements of a control circuit for controlling a power MOSFET for power. N
^In the region 27b of the-type epitaxial layer 27, a P well 2
An NPN bipolar transistor 37 having an N ⁺ -type collector 8, an N ⁺ -type emitter 9, and a P ⁺ -type base contact 10, each of which is connected to the electrode 17, is formed on the surface of the P well 29. Are formed as one of the elements of a control circuit for controlling a power MOSFET for electric power. The region 2 of the N ⁻ -type epitaxial layer 27 connected to the N ⁺ -type buried layer 26 and located thereabove.
7c includes an N ⁺ -type source 11 in the P-type region 22, a channel region 24 on the surface of the P-type region 22, and an N ^-- type region 27c.
A source electrode 16 connected to the N ⁺ type source 11, a drain comprising the N ⁺ type buried layer 26 and the N ⁺ type silicon substrate 3,
Drain electrode 1 connected to the back of N ^{+ type} silicon substrate 3
5, a power MOSFET for power having a gate insulating film 41 on the channel region 24 and a gate electrode 42 thereon
39 are formed.

[0003] Typically in the power IC of such a configuration P ^-
Since the N ^- type region 27c, the N ⁺ type buried layer 26 and the N ⁺ type silicon substrate 3 are used at a positive potential, the PN junction therebetween is reverse-biased and the bipolar transistor 36 is used. , 37 and MO
SFET 39 is electrically isolated.

At this time, the reverse bias breakdown voltage of the P ⁻ N ⁺ junction formed between the P ⁻ -type epitaxial layer 25 and the N ⁺ -type silicon substrate 3 is determined by the thickness of the P ⁻ -type epitaxial layer 25. Voltage is 60
In the case of V, about 20 μm is required.

On the other hand, the drain breakdown voltage of the MOSFET is N
^- determined by the thickness of the type epitaxial layer 27, it is necessary to a typical thickness of about 10 [mu] m.

[0006]

In the power IC shown in FIG. 4, the P ⁺ -type diffusion layer 28 is formed to electrically isolate the control transistors 36 and 37 and the MOSFET 39 as a power element. However, the P ⁺ type diffusion layer 28 has a disadvantage that it requires a large area and a long time is required for its formation.

In order to solve this drawback, it is conceivable to use a trench isolation method (trench isolation method) used for a small signal bipolar IC or the like. This method is shown in FIG.
In FIG. 5, the same or similar portions as those in FIG. 4 are denoted by the same reference numerals, and the duplicate description will be omitted. In FIG. 5, the element isolation region is formed by the trench 30 and the insulator layer 13 filled in the trench 30. But,
When the trench isolation method is applied to a conventional power IC, the N ⁻ -type epitaxial layer 27 needs to have a thickness of about 10 μm for the drain breakdown voltage of the MOSFET as described above. It must be formed to a deep depth, which makes the process complicated and difficult and not practical.

[0008]

SUMMARY OF THE INVENTION The present invention is characterized in that a power MOSFET that allows a current to flow from a first main surface of a semiconductor substrate to a second main surface thereof, and a first main surface of the semiconductor substrate. A control element formed on the side for controlling the MOSFET;
In a semiconductor integrated circuit device having an element isolation region for isolating the MOSFET and the control element, the semiconductor substrate has a first conductivity type semiconductor base and an impurity concentration lower than that of the semiconductor base. A first semiconductor layer of the first conductivity type formed thereon and a second semiconductor layer of the second conductivity type formed on the first semiconductor layer, each having the same depth. First and second having
Is provided so as to penetrate the second semiconductor layer and reach the first semiconductor layer, and the element isolation region includes an insulating layer (dielectric layer) formed on the first trench and an inner surface thereof. Body layer), and the MOSFE
A channel region of T is formed in the second semiconductor layer on a side wall of the second trench in a direction perpendicular to the first and second main surfaces of the semiconductor substrate, and the second conductivity type second region is formed .
The surface of the semiconductor layer is the first main surface of the semiconductor substrate.
The second conductivity type of the second conductive type surrounded by the element isolation region.
A first conductivity type well is formed at the location of the semiconductor layer of
The control element is formed in the well of one conductivity type.
That in the semiconductor integrated circuit device.

The present invention is characterized in that an insulated gate field-effect transistor for power, which allows a current to flow from the first main surface side of the semiconductor substrate to the second main surface side, and that the first main surface side of the semiconductor substrate has In a semiconductor integrated circuit device having a formed control element for controlling the insulated gate field-effect transistor and an element isolation region for separating the insulated gate field-effect transistor and the control element, the semiconductor substrate includes a first A semiconductor substrate of a conductivity type, a first semiconductor layer of a first conductivity type formed on the semiconductor substrate with an impurity concentration lower than that of the semiconductor substrate, and a first semiconductor layer formed on the first semiconductor layer. A second conductive type second semiconductor layer; and a first conductive type epitaxial layer formed on the second conductive type second semiconductor layer. 2 semiconductor layers A first trench penetrating therethrough and reaching the first semiconductor layer; and an insulator layer formed on an inner surface of the first trench. The channel region of the insulated gate field effect transistor is formed in the second semiconductor layer. A first conductive type epitaxial layer formed on a side wall of a second trench and serving as a source of the insulated gate field effect transistor; and a first and a second bipolar transistor as the control element; In a semiconductor integrated circuit device, a conductive type epitaxial layer is used as a base of the first bipolar transistor, and the first conductive type epitaxial layer is used as a collector of the second bipolar transistor.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a semiconductor chip according to a first embodiment of the present invention. FIGS. 2A to 2E showing the method of manufacturing the semiconductor chip shown in FIG. 1 and the method shown in FIG.

[0012] First, N on N ⁺ -type silicon substrate 3 having a high impurity concentration ^- -type silicon epitaxial layer 2 a thickness of approximately 10
The semiconductor substrate 50 is formed by growing the P-type silicon epitaxial layer 1 to a thickness of about 3 μm thereon. The semiconductor substrate 50 has a surface of the P-type silicon epitaxial layer 1 as a first main surface 51 and a second surface of the N ⁺ -type silicon substrate 3 in a direction opposite to the surface on which the N ⁻ -type silicon epitaxial layer 2 is formed. And the first surface 52
The second main surfaces 51 and 52 are substantially parallel flat surfaces (FIG. 2A).

Next, a first trench (groove) 14a and a second trench (groove) penetrating the P-type silicon epitaxial layer 1 and reaching the N ⁻ -type silicon epitaxial layer 2
14b is formed perpendicular to the first main surface 51. The first trench 14a is for element isolation, whereby the P-type epitaxial layer 1 is electrically isolated into island-shaped regions 1a, 1b, 1c. The second trench 14b has an island-like region 1c.
And is for a vertical channel gate structure of a MOSFET (FIG. 2B).

Next, the first trench 14a is filled with an insulating film 13 such as silicon dioxide to form an element isolation region. On the other hand, a gate insulating film 21 such as silicon dioxide formed by thermal oxidation is formed on the inner wall of the second trench 14b, and polysilicon is deposited thereon so as to fill the trench 14b to form a gate electrode 12. An insulating film 43 is formed on the electrode 12 (FIG. 2C).

Next, the P-type epitaxial layer 1 is formed in the island-shaped region 1a by photolithography.
Forming the N-type base 7 of the NP bipolar transistor,
The P ⁺ -type collector 4, P ⁺ -type emitter 5, and N ⁺ -type base contact 6 of this transistor are formed therein.
Further, to form a P-type base 18 of there NPN bipolar transistor forming the N-type well 19 in the P-type island region 1b of the epitaxial layer 1, N ⁺ -type collector 8, N ⁺ -type transistor to them An emitter 9 and a P ⁺ type base contact portion 10 are formed. Further, the N ⁺ -type source 11 of the power MOSFET is formed on the outer peripheral surface of the trench 14b in the island-shaped region 1c of the P-type epitaxial layer 1. Then, an insulating film 33 such as silicon dioxide is deposited on the entire surface (FIG. 2D).

Finally, contact holes are formed in the insulating film 33, the electrodes 17 are connected to the respective impurity regions, and the PNP bipolar transistor 36 controls the power MOSFET for the power in the island-like region 1a. NP is formed as one of the elements of the control circuit.
N bipolar transistor 37 is a power MOS for power
It is formed as one of the elements of a control circuit that controls the FET.

Meanwhile, the source electrode 16 to the N ⁺ -type source 11
And N ⁺ that is the second main surface 52 of the semiconductor substrate 50
A drain electrode 15 is connected to the back surface of the mold silicon substrate 3, and a channel region 20 is formed on the side wall of the second trench 14b in a direction perpendicular to the main surface 51 of the semiconductor substrate 50,
A power MOSFET 38 for electric power having a current path between the source electrode 16 on one main surface 51 of the semiconductor substrate and the drain electrode 15 on the other main surface 52 of the semiconductor substrate is formed in an island-like region 1 c To the N ⁻ -type silicon epitaxial layer 2 and the N ⁺ -type silicon substrate 3 to be drains (FIG. 2D and FIG. 1).

FIG. 2 shows the left half of the MOSFET in FIG. Since the second trench 14b shown in the cross section of FIG. 1 has a ring shape in plan view, the second trench 14b shown on the left and right is formed continuously. Therefore, channel region 2
0, the gate insulating film 21 and the source 11 are formed along the inner and outer peripheries of the second trench 14b having a planar shape and a ring shape.

In the present invention described above, the thickness of the P-type silicon epitaxial layer 1 depends on the thickness for obtaining the channel length of the MOSFET 38 (between the source and the drain in the vertical direction) and the thickness for forming the bipolar transistors 36 and 37. About 3 μm is sufficient. Therefore,
Since the depth of 3 to 4 μm is sufficient for the second trench 14b for element isolation, trench isolation can be used for the power IC.

That is, the drain breakdown voltage of the MOSFET is determined by the film thickness of the N ⁻ type silicon epitaxial layer 2, but since the trench penetrates the P − type silicon epitaxial layer 1, the N ⁻ type silicon epitaxial layer 2
Does not penetrate through, the drain breakdown voltage and the depth of the trench become irrelevant.

Further, in the semiconductor integrated circuit device of the present invention, the P-type silicon epitaxial layer 1 is usually used at the ground potential, and the N ⁻ -type silicon epitaxial layer 2 and the N ⁺ -type silicon substrate 3 are used at the positive potential. At this time, the breakdown voltage between P-type silicon epitaxial layer 1 and N ⁻ -type silicon epitaxial layer 2 is
It is determined by the film thickness of the N ⁻ type silicon epitaxial layer 2 as in the case of the drain breakdown voltage of the FET. Thus, FIG. 4, the breakdown voltage in the prior art of FIG. 5 P ^-
In the present invention, the breakdown voltage and the drain withstand voltage are different from each other in that the drain breakdown voltage of the MOSFET depends on the thickness of the N ⁻ type epitaxial layer 27 and the drain breakdown voltage of the MOSFET depends on the thickness of the N ⁻ type epitaxial layer 27. Since it depends only on one layer of the N ⁻ type silicon epitaxial layer 2, the N ⁺ type buried layer 26 in the MOSFET of FIGS. 4 and 5 can be omitted, and the process is further simplified.

FIG. 3 is a sectional view showing a semiconductor chip according to a second embodiment of the present invention. Note that, in FIG. 3, the same or similar portions as those in FIGS. 1 and 2 are denoted by the same reference numerals, and duplicate description will be omitted.

In the second embodiment, an N ⁻ type silicon epitaxial layer 32 is further grown on the P type silicon epitaxial layer 1 to form a semiconductor substrate. The first and second trenches 14a, 14b penetrate the N ⁻ type silicon epitaxial layer 32 and then penetrate the P type silicon epitaxial layer 1, and the trench 14a also causes the N ⁻ type silicon epitaxial layer 32 to have an island-like region 32a, 32
b, 32c. In the MOSFET, an N ⁺ type source 11 serving as a source contact portion is formed in an island-like region 32c of the N ⁻ type silicon epitaxial layer 32,
The island region 32 c of the N ⁻ type silicon epitaxial layer becomes the N ⁻ type source that contacts the channel region 20.

Then, the PNP bipolar transistor 3
6, the region 32 of the N ^- type silicon epitaxial layer 32
a serves as the base, and the NPN bipolar transistor 37 omits the formation of the N well, and the region 32b of the N ⁻ type silicon epitaxial layer 32 becomes the collector as it is to form the N ⁺ type collector buried layer 34 and the N ⁺ type extraction region 35. I do. With such a structure, a high-performance bipolar transistor can be obtained.

The bipolar transistor has been described as an example of the control element. However, the control element is not limited to the bipolar transistor, and the present invention can be applied to a case where a CMOS or a diode is used as the control element. Is applicable. Further, the present invention is applicable even when the polarity of the semiconductor of the embodiment is reversed, that is, when the N-type is changed to the P-type and the P-type is changed to the N-type.

[0026]

As described above, according to the present invention, a semiconductor substrate is constituted by having an N ^-- type epitaxial layer on an N ⁺ -type substrate and a P-type epitaxial layer thereon. A power MOSFET for flowing a current from the first main surface side of the semiconductor substrate to the second main surface side and the first MOSFET of the semiconductor substrate.
A trench isolation method can be used in an element isolation region for isolating a control element formed on the main surface side of the element. Also, MO
Since the channel region of the SFET is formed on the sidewall of the trench in a direction perpendicular to the first and second main surfaces of the semiconductor substrate in the P-type epitaxial layer, the buried layer can be eliminated and the structure can be simplified. .

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a method of manufacturing the first embodiment of the present invention in the order of steps.

FIG. 3 is a sectional view showing a second embodiment of the present invention.

FIG. 4 is a cross-sectional view showing an example of the related art.

FIG. 5 is a sectional view showing another example of the prior art.

[Explanation of symbols]

Reference Signs List 1 P-type silicon epitaxial layer 1 a, 1 b, 1 c Island-shaped region of P-type epitaxial layer 1 2 N ⁻ -type silicon epitaxial layer 3 N ⁺ -type silicon substrate 4 P ⁺ type collector of PNP bipolar transistor 5 P ^{+ of} PNP bipolar transistor -type emitter 6 PNP bipolar transistor of the N ⁺ -type base contact portion 7 PNP bipolar transistor N-type base 8 P ⁺ -type base contact portion of the N ⁺ type emitter 10 NPN bipolar transistor of the N ⁺ -type collector 9 NPN bipolar transistor of the NPN bipolar transistor 11 second trench for gate structure of a MOSFET of the N ⁺ -type first trench 14b MOSFET for insulating film 14a isolation of the source 12 within the first trench for gate electrode 13 isolation of MOSFET Reference Signs List 5 MOSFET drain electrode 16 MOSFET source electrode 17 Bipolar transistor electrode 18 P-type base of NPN bipolar transistor 19 N-type well for forming NPN bipolar transistor 20 MOSFET channel region 21 MOSFET gate insulating film 22 P-type region 24 MOSFET Channel region 25 P ⁻ type epitaxial layer 26 N ⁺ type buried layer 27 N ⁻ type silicon epitaxial layer 27 a, 27 b, 27 c N ⁻ type epitaxial layer 2
7 island-shaped region 28 P ⁺ type diffusion layer 29 P well 30 trench 32 N ⁻ type silicon epitaxial layer 32 a, 32 b, 32 c island type region of N ⁻ type silicon epitaxial layer 32 33 insulating film on semiconductor substrate 34 N ⁺ -Type collector buried layer 35 N ⁺ -type lead-out region 36 PNP bipolar transistor 37 NPN bipolar transistor 38 MOSFET of the present invention 39 Conventional MOSFET 41 Gate insulating film 42 Gate electrode 43 Insulating film 50 Semiconductor substrate 51 First semiconductor substrate Main surface 52 Second main surface of semiconductor substrate

Claims (2)

(57) [Claims] 1. An insulated gate field-effect transistor for power, which allows a current to flow from a first main surface side of a semiconductor substrate to a second main surface side, and formed on the first main surface side of the semiconductor substrate.
In a semiconductor integrated circuit device having a control element for controlling the insulated gate field effect transistor and an element isolation region for separating the insulated gate field effect transistor and the control element, the semiconductor substrate is a semiconductor of a first conductivity type. A base; a first conductive type first semiconductor layer formed on the semiconductor base with a lower impurity concentration than the semiconductor base;
And a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, and first and second trenches each having the same depth penetrate the second semiconductor layer. And the element isolation region is configured to include the first trench and an insulator layer formed on an inner surface of the first trench. A channel region is formed on a sidewall of the second trench in the second semiconductor layer, and a surface of the second conductivity type second semiconductor layer is formed on the semiconductor substrate.
A first main surface of a plate, the second half of a second conductivity type surrounded by the element isolation region;
A first conductivity type well is formed at the location of the conductor layer, and the first conductivity type well is formed.
The semiconductor integrated circuit device , wherein the control element is formed in the electric well . 2. An insulated gate field-effect transistor for power, which allows a current to flow from the first main surface side of the semiconductor substrate to the second main surface side, and formed on the first main surface side of the semiconductor substrate.
In a semiconductor integrated circuit device having a control element for controlling the insulated gate field effect transistor and an element isolation region for separating the insulated gate field effect transistor and the control element, the semiconductor substrate is a semiconductor of a first conductivity type. A base; a first conductive type first semiconductor layer formed on the semiconductor base with a lower impurity concentration than the semiconductor base;
A second conductive type second semiconductor layer formed on the first semiconductor layer, and a first conductive type epitaxial layer formed on the second conductive type second semiconductor layer. The element isolation region includes a first trench that penetrates the second semiconductor layer and reaches the first semiconductor layer, and an insulator layer formed on an inner surface of the first trench. A channel region of the effect transistor is formed on a side wall of the second trench in the second semiconductor layer, and the epitaxial layer of the first conductivity type is used as a source of the insulated gate field effect transistor. First and second bipolar transistors, wherein the first conductivity type epitaxial layer is used as a base of the first bipolar transistor;
A semiconductor integrated circuit device, wherein a conductive type epitaxial layer is used as a collector of the second bipolar transistor.