JP2001127287A - Insulating gate-type semiconductor device - Google Patents
Insulating gate-type semiconductor deviceInfo
- Publication number
- JP2001127287A JP2001127287A JP30605399A JP30605399A JP2001127287A JP 2001127287 A JP2001127287 A JP 2001127287A JP 30605399 A JP30605399 A JP 30605399A JP 30605399 A JP30605399 A JP 30605399A JP 2001127287 A JP2001127287 A JP 2001127287A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- base layer
- drain
- source
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 230000002093 peripheral effect Effects 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims description 32
- 238000009792 diffusion process Methods 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 11
- 239000010703 silicon Substances 0.000 abstract description 11
- 238000000926 separation method Methods 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 description 9
- 238000000034 method Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、アナログＩＣの
出力回路等に用いて好適な絶縁ゲート型半導体装置に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device suitable for use in an output circuit of an analog IC.
【０００２】[0002]
【従来の技術】アナログＩＣの出力回路として、図６に
示すように、ｎチャネルＭＯＳトランジスタＱ１，Ｑ２
を用いて構成したものがよく用いられる。ｎチャネルＭ
ＯＳトランジスタを用いるのは、ｐチャネルに比べて電
流駆動能力が高く、またサージ耐性も高いからである。
これらの出力回路トランジスタＱ１，Ｑ２に好適な構造
として、ＳＯＩ（Silicon-On-Insulator)基板に形成さ
れるＤＭＯＳ（Double-Diffused MOS）トランジスタが
知られている。2. Description of the Related Art As an output circuit of an analog IC, as shown in FIG. 6, n-channel MOS transistors Q1, Q2
What is constituted using is often used. n channel M
The OS transistor is used because it has higher current driving capability and higher surge resistance than the p-channel.
A DMOS (Double-Diffused MOS) transistor formed on an SOI (Silicon-On-Insulator) substrate is known as a structure suitable for these output circuit transistors Q1 and Q2.
【０００３】図７は、ＳＯＩ基板１を用いたＤＭＯＳト
ランジスタ構造を示している。ＳＯＩ基板のｎ-型シリ
コン層１ｃの一部が素子分離領域２により囲まれて高抵
抗ドレイン層３となる。素子分離領域２は、シリコン層
１ｃの底部絶縁膜１ｂに達する深さに溝２ａを形成し、
その側壁に絶縁膜２ｂを形成して多結晶シリコン２ｃを
埋め込んで形成される。これにより高抵抗ドレイン層３
は、他の素子領域から完全に誘電体分離される。FIG. 7 shows a DMOS transistor structure using the SOI substrate 1. A part of the n − -type silicon layer 1 c of the SOI substrate is surrounded by the element isolation region 2 to form the high-resistance drain layer 3. The element isolation region 2 forms a groove 2a at a depth reaching the bottom insulating film 1b of the silicon layer 1c,
An insulating film 2b is formed on the side wall and polycrystalline silicon 2c is buried. Thereby, the high-resistance drain layer 3 is formed.
Is completely dielectrically isolated from other element regions.
【０００４】高抵抗ドレイン層３の表面にｐ型のベース
層４が形成され、このベース層４の表面にｎ+型のソー
ス層５が形成される。高抵抗ドレイン層３には、ベース
層４から所定距離離れてｎ+型のドレイン・コンタクト
層６が形成される。ベース層４のソース層５と高抵抗ド
レイン層３により挟まれた領域をチャネル領域７とし
て、この上にゲート絶縁膜８を介してゲート電極９が形
成される。ソース電極１１はソース層５とｐ型ベース層
４に同時にコンタクトするように形成される。ドレイン
・コンタクト層６にはドレイン電極１２が接続される。A p-type base layer 4 is formed on the surface of the high-resistance drain layer 3, and an n + -type source layer 5 is formed on the surface of the base layer 4. An n + -type drain contact layer 6 is formed on the high-resistance drain layer 3 at a predetermined distance from the base layer 4. A region between the source layer 5 and the high-resistance drain layer 3 of the base layer 4 is defined as a channel region 7, on which a gate electrode 9 is formed via a gate insulating film 8. The source electrode 11 is formed so as to contact the source layer 5 and the p-type base layer 4 at the same time. The drain electrode 12 is connected to the drain contact layer 6.
【０００５】ＤＭＯＳトランジスタの実際の製造工程で
は、ベース層４とソース層５とは、ゲート電極９を拡散
マスクの一部とする不純物の二重拡散により形成され、
これらのベース層４とソース層５の拡散深さの差により
チャネル領域７がゲート電極９に対して自己整合的に形
成される。In an actual manufacturing process of a DMOS transistor, the base layer 4 and the source layer 5 are formed by double diffusion of impurities using the gate electrode 9 as a part of a diffusion mask.
The channel region 7 is formed in a self-aligned manner with respect to the gate electrode 9 due to the difference in the diffusion depth between the base layer 4 and the source layer 5.
【０００６】アナログＩＣの出力回路では特に、ＥＳＤ
（Electrostatic-Discharge）耐量（サージ耐量）に対
する要求が厳しい。上述したＤＭＯＳトランジスタを用
いた場合のサージ耐量を改善する方法として従来は、ソ
ース・ドレイン間隔を大きくして、トランジスタ耐圧そ
のものを高くする方法、トランジスタ面積を大きくして
その寄生容量によりサージパルスを吸収する方法、等が
考えられている。In the output circuit of an analog IC, in particular, ESD
(Electrostatic-Discharge) The demand for withstand voltage (surge withstand voltage) is severe. Conventionally, as a method of improving the surge withstand capability when the above-mentioned DMOS transistor is used, a method of increasing the transistor withstand voltage itself by increasing a source-drain interval, and a method of increasing a transistor area and absorbing a surge pulse by its parasitic capacitance are used. There is a method to do this.
【０００７】[0007]
【発明が解決しようとする課題】しかし、従来のサージ
耐量の改善の方法は、素子面積を大きくする割には、サ
ージ耐量の改善効果が小さいという問題があった。特
に、図７に示すように、ＳＯＩ基板を用いたＤＭＯＳト
ランジスタでは、素子領域が完全に絶縁分離されてい
て、寄生トランジスタ等により基板にサージ電流を流す
経路は形成されない。従って、サージ電流が全て素子内
部を流れ、これがサージ耐量の改善を難しくしている。However, the conventional method for improving the surge withstand capability has a problem that the effect of improving the surge withstand capability is small in spite of increasing the element area. In particular, as shown in FIG. 7, in a DMOS transistor using an SOI substrate, the element region is completely insulated and separated, and a path for flowing a surge current through the substrate by a parasitic transistor or the like is not formed. Therefore, all surge currents flow inside the element, which makes it difficult to improve surge withstand capability.
【０００８】特に問題になるのは、図８に示すように、
サージによる降伏電流の一部が、破線で示すように、ゲ
ート絶縁膜８を通りゲート電極９に抜けることである。
即ち、通常のＤＭＯＳトランジスタ構造では、ソース電
極１１とドレイン電極１２の間にゲート電極９が配置さ
れる。このため、ドレインからソースに抜ける降伏電流
はｐ型ベース層４のゲート電極９の直下を通り、ベース
層４での電圧降下によりチャネル領域７が電位上昇す
る。この結果、降伏電流の一部がゲート電極９に抜ける
ために、ゲート絶縁膜８が破壊される。A particular problem is that, as shown in FIG.
A part of the breakdown current due to the surge passes through the gate insulating film 8 to the gate electrode 9 as shown by a broken line.
That is, in a normal DMOS transistor structure, the gate electrode 9 is arranged between the source electrode 11 and the drain electrode 12. Therefore, the breakdown current flowing from the drain to the source passes immediately below the gate electrode 9 of the p-type base layer 4, and the potential of the channel region 7 increases due to the voltage drop in the base layer 4. As a result, the gate insulating film 8 is broken because a part of the breakdown current passes through the gate electrode 9.
【０００９】この発明は、上記事情を考慮してなされた
もので、サージによる降伏電流がゲート電極直下を流れ
ないようにしてサージ耐量を改善した絶縁ゲート型半導
体装置を提供することを目的としている。SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and has as its object to provide an insulated gate semiconductor device in which a breakdown current due to a surge is prevented from flowing immediately below a gate electrode to improve a surge withstand capability. .
【００１０】[0010]
【課題を解決するための手段】この発明に係る絶縁ゲー
ト型半導体装置は、半導体基板と、この半導体基板に素
子分離領域により区画された第１導電型のドレイン層
と、このドレイン層の表面に形成された第２導電型のベ
ース層と、前記ドレイン層の表面に前記ベース層から離
れて形成された第１導電型のドレイン・コンタクト層
と、前記ベース層の表面に選択的に形成された第１導電
型のソース層と、前記ベース層の前記素子分離領域に近
い側の周縁表面をチャネル領域として、このチャネル領
域上にゲート絶縁膜を介して形成されたゲート電極と、
このゲート電極とドレイン層との間に配置されて前記ソ
ース層とベース層にコンタクトするソース電極と、を有
することを特徴とする。According to the present invention, there is provided an insulated gate semiconductor device comprising: a semiconductor substrate; a first conductivity type drain layer divided by an element isolation region in the semiconductor substrate; A second conductive type base layer formed; a first conductive type drain contact layer formed on the surface of the drain layer away from the base layer; and selectively formed on the surface of the base layer. A first conductivity type source layer, a gate electrode formed on the channel region with a peripheral surface on a side closer to the element isolation region as a channel region, with a gate insulating film interposed therebetween;
A source electrode disposed between the gate electrode and the drain layer and in contact with the source layer and the base layer.
【００１１】この発明においては、ベース層のドレイン
・コンタクト層に近い側の周縁ではなく、素子分離領域
に近い側の周縁表面をチャネル領域として用いることに
より、ドレイン・コンタクト層との関係でゲートとソー
スの配置が従来のＭＯＳトランジスタとは逆になる。従
ってこの発明によるＭＯＳトランジスタでは、サージに
よるドレイン・ソース間の降伏電流は、ゲート電極直下
を通ることなくソース電極に抜ける。このため、従来の
ようなゲート電極直下の電位上昇、その結果としてのゲ
ート絶縁膜を通るゲート電極への電流突き抜けが生じる
ことはなく、サージによるゲート絶縁膜破壊という事故
が抑制される。In the present invention, by using the peripheral surface of the base layer, which is closer to the element isolation region, instead of the peripheral edge of the base layer closer to the drain contact layer, as the channel region, the gate and the drain can be connected in relation to the drain / contact layer. The arrangement of the sources is reversed from that of the conventional MOS transistor. Therefore, in the MOS transistor according to the present invention, the breakdown current between the drain and the source due to the surge flows to the source electrode without passing right below the gate electrode. For this reason, the potential rise immediately below the gate electrode and the resulting current penetration to the gate electrode passing through the gate insulating film do not occur as in the related art, and the accident of the gate insulating film destruction due to the surge is suppressed.
【００１２】この発明において好ましくは、半導体基板
は、支持基板と、この支持基板上に第１の絶縁膜により
支持基板と分離された状態で形成された第１導電型の半
導体層とを有するＳＯＩ基板とする。この場合ドレイン
層は、半導体層の一部が素子分離領域により囲まれたも
のである。またこの発明において好ましくは、素子分離
領域は、ドレイン層を囲んで第１の絶縁膜に達する深さ
に形成された素子分離溝と、この素子分離溝の少なくと
も側壁に形成された第２の絶縁膜とを有するものとす
る。In the present invention, preferably, the semiconductor substrate includes an SOI having a support substrate and a first conductivity type semiconductor layer formed on the support substrate and separated from the support substrate by a first insulating film. Substrate. In this case, the drain layer has a part of the semiconductor layer surrounded by the element isolation region. Preferably, in the present invention, the element isolation region includes an element isolation groove formed to a depth reaching the first insulating film surrounding the drain layer, and a second insulating layer formed at least on a side wall of the element isolation groove. And a membrane.
【００１３】またこの発明において、ベース層とソース
層は例えば、ゲート電極を拡散マスクの一部として用い
た不純物の二重拡散により形成され、これによりＤＭＯ
Ｓトランジスタが得られる。ベース層及びソース層は、
ドレイン・コンタクト層を挟んで二箇所に配置されても
よいし、或いはベース層、ソース層及びゲート電極が、
ドレイン・コンタクト層を取り囲んでリング状に形成さ
れてもよい。In the present invention, the base layer and the source layer are formed by, for example, double diffusion of impurities using a gate electrode as a part of a diffusion mask.
An S transistor is obtained. The base layer and the source layer are
It may be arranged at two places with the drain / contact layer interposed, or the base layer, the source layer and the gate electrode may be
It may be formed in a ring shape surrounding the drain / contact layer.
【００１４】この発明に係る絶縁ゲート型半導体装置は
また、半導体基板と、この半導体基板に素子分離領域に
より区画された第１導電型の第１ベース層と、この第１
ベース層の表面に形成された第２導電型の第２ベース層
と、前記第１ベース層の表面に前記第２ベース層から離
れて形成された第２導電型のドレイン層と、前記第２ベ
ース層の表面に選択的に形成された第１導電型のソース
層と、前記第２ベース層の前記素子分離領域に近い側の
周縁表面をチャネル領域として、このチャネル領域上に
ゲート絶縁膜を介して形成されたゲート電極と、前記ソ
ース層と第２ベース層にコンタクトするように形成され
たソース電極とを備えて、ＩＧＢＴ（Insulated Gate B
ipolar Transistor）として構成することもできる。The insulated gate semiconductor device according to the present invention also includes a semiconductor substrate, a first base layer of a first conductivity type defined by an element isolation region in the semiconductor substrate,
A second conductive type second base layer formed on the surface of the base layer, a second conductive type drain layer formed on the surface of the first base layer away from the second base layer; A first conductive type source layer selectively formed on the surface of the base layer and a peripheral surface of the second base layer closer to the element isolation region as a channel region, and a gate insulating film is formed on the channel region. An IGBT (Insulated Gate B) including a gate electrode formed through the gate electrode and a source electrode formed to contact the source layer and the second base layer.
ipolar Transistor).
【００１５】[0015]
【発明の実施の形態】以下、図面を参照して、この発明
の実施の形態を説明する。以下の実施の形態では、第１
導電型としてｎ型、第２導電型としてｐ型を用いるが、
各部の導電型を逆にしてもよい。 ［実施の形態１］図１Ａはこの発明の実施の形態による
ＤＭＯＳトランジスタの平面図であり、図１Ｂは図１Ａ
のＡ−Ａ’断面図である。半導体基板１はこの実施の形
態の場合、支持基板としてのｐ-型シリコン基板１ａ
と、この上にシリコン酸化膜等の絶縁膜１ｂを介して形
成されたｎ-型シリコン層１ｃとからなるＳＯＩ基板で
ある。このＳＯＩ基板１は具体的には、シリコン基板の
直接接着技術により作られる。Embodiments of the present invention will be described below with reference to the drawings. In the following embodiment, the first
Although n-type is used as the conductivity type and p-type is used as the second conductivity type,
The conductivity type of each part may be reversed. [Embodiment 1] FIG. 1A is a plan view of a DMOS transistor according to an embodiment of the present invention, and FIG.
3 is a sectional view taken along line AA ′ of FIG. In this embodiment, the semiconductor substrate 1 is a p - type silicon substrate 1a as a supporting substrate.
When, n formed via an insulating film 1b of the silicon oxide film or the like on this - a SOI substrate comprising a -type silicon layer 1c. The SOI substrate 1 is specifically made by a direct bonding technique of a silicon substrate.
【００１６】このＳＯＩ基板１のシリコン層１ｃの中
に、素子分離領域２により囲まれた高抵抗のドレイン層
３が区画される。素子分離領域２はこの実施の形態の場
合、底部絶縁膜１ｂに達する深さに素子分離溝２ａを形
成し、この溝２ａの側壁にシリコン酸化膜等の絶縁膜２
ｂを形成して、多結晶シリコン２ｃを埋め込んで構成さ
れている。これによりドレイン層３は他の領域から完全
に誘電体分離される。In the silicon layer 1c of the SOI substrate 1, a high-resistance drain layer 3 surrounded by an element isolation region 2 is defined. In the case of this embodiment, an element isolation groove 2a is formed in the element isolation region 2 at a depth reaching the bottom insulating film 1b, and an insulating film 2 such as a silicon oxide film is formed on a side wall of the groove 2a.
b and polycrystalline silicon 2c is buried. As a result, the drain layer 3 is completely separated from other regions by a dielectric.
【００１７】高抵抗ドレイン層３は細長い矩形パターン
に区画されており、その表面の長手方向の一端寄りに矩
形のｐ型ベース層４が形成され、このベース層４から離
れてドレイン層３の長手方向の他端寄りに矩形のｎ+型
ドレイン・コンタクト層６が形成されている。ｐ型ベー
ス層４のドレイン・コンタクト層６側とは反対の周縁寄
りには矩形のｎ+型ソース層５が形成されている。図１
Ｂに示すように、ソース層５とドレイン・コンタクト層
６を横切るＡ−Ａ’断面では、ベース層４の周縁は、ド
レイン・コンタクト層６に近い方と素子分離領域２に近
い方の２箇所あるが、そのうち素子分離領域２に近い方
の周縁表面をチャネル領域７として、この上にゲート絶
縁膜８を介してゲート電極９が形成されている。The high-resistance drain layer 3 is partitioned into an elongated rectangular pattern, and a rectangular p-type base layer 4 is formed near one end of the surface in the longitudinal direction. A rectangular n + -type drain contact layer 6 is formed near the other end in the direction. A rectangular n + -type source layer 5 is formed near the periphery of the p-type base layer 4 opposite to the drain / contact layer 6 side. FIG.
As shown in B, in the AA ′ cross section that crosses the source layer 5 and the drain / contact layer 6, the periphery of the base layer 4 has two positions, one near the drain / contact layer 6 and one near the element isolation region 2. However, a gate electrode 9 is formed on the peripheral surface closer to the element isolation region 2 as a channel region 7 with a gate insulating film 8 interposed therebetween.
【００１８】なお実際の製造工程では、ベース層４及び
ソース層５より先にゲート電極９が作られる。そしてゲ
ート電極９を不純物拡散マスクの一部として用いて（即
ち図１Ｂにおいて、ゲート電極９の右側エッジをマスク
開口のエッジとして）、ｐ型不純物とｎ型不純物の二重
拡散を行うことにより、ベース層４とソース層５を形成
する。これにより、ゲート電極９に自己整合された形で
チャネル領域７が形成される。In the actual manufacturing process, the gate electrode 9 is formed before the base layer 4 and the source layer 5. By using the gate electrode 9 as a part of the impurity diffusion mask (that is, in FIG. 1B, the right edge of the gate electrode 9 is set as the edge of the mask opening), double diffusion of the p-type impurity and the n-type impurity is performed. The base layer 4 and the source layer 5 are formed. As a result, the channel region 7 is formed so as to be self-aligned with the gate electrode 9.
【００１９】拡散層とゲート電極が形成された基板上は
絶縁膜１０で覆われ、これにコンタクト孔が開けられ
て、ソース層５及びドレイン・コンタクト層６にそれぞ
れコンタクトするソース電極１１及びドレイン電極１２
が形成される。ソース電極１１はソース層５と同時に、
ベース層４にもコンタクトさせる。これにより、ＤＭＯ
Ｓトランジスタのバルク領域であるベース層４は、ソー
スと同電位に固定されることになる。The substrate on which the diffusion layer and the gate electrode are formed is covered with an insulating film 10, and a contact hole is formed in the insulating film 10 so that the source electrode 11 and the drain electrode contact the source layer 5 and the drain / contact layer 6, respectively. 12
Is formed. The source electrode 11 and the source layer 5
The base layer 4 is also contacted. With this, DMO
The base layer 4 which is the bulk region of the S transistor is fixed at the same potential as the source.
【００２０】以上のようにこの実施の形態では、ｐ型ベ
ース層４のドレイン・コンタクト層６から遠い方の周縁
（言い換えれば、素子分離領域２に近い側の周縁）の表
面をチャネル領域７としている。即ち、ソース電極１１
とドレイン電極１２の間にゲート電極９が配置される通
常の電極配置と異なり、この実施の形態ではゲート電極
９、ソース電極１１、ドレイン電極１２の順に配置され
る。従ってゲート電極９に正のバイアスを与えてＤＭＯ
Ｓトランジスタをオンさせたとき、ソースからドレイン
に流れる電子電流は、図１Ｂに破線で示したように流れ
る。即ち、ソース層５から流れ出る電子電流は、ドレイ
ン・コンタクト層６から離れる方向にチャネル領域７を
通ってドレイン層３に入り、ベース層４の側面を迂回し
ながらその底面下を流れて、ドレイン・コンタクト層６
まで流れる。As described above, in this embodiment, the surface of the periphery of the p-type base layer 4 far from the drain / contact layer 6 (in other words, the periphery near the element isolation region 2) is defined as the channel region 7. I have. That is, the source electrode 11
Unlike the normal electrode arrangement in which the gate electrode 9 is arranged between the gate electrode 9 and the drain electrode 12, in this embodiment, the gate electrode 9, the source electrode 11, and the drain electrode 12 are arranged in this order. Therefore, a positive bias is applied to the gate
When the S transistor is turned on, the electron current flowing from the source to the drain flows as shown by a broken line in FIG. 1B. That is, the electron current flowing out of the source layer 5 enters the drain layer 3 through the channel region 7 in a direction away from the drain contact layer 6, flows under the bottom surface while bypassing the side surface of the base layer 4, Contact layer 6
Flows up to
【００２１】この実施の形態のＤＭＯＳトランジスタに
おいて、サージによりドレイン・ソース間に降伏電流が
流れる様子を、従来の図８（ａ）と対応させて図８
（ｂ）に示した。この実施の形態の場合、ゲート電極９
がソース電極１１の外側にあるから、破線で示すように
降伏電流はゲート電極９の直下を流れることがなく、ソ
ース電極１１に抜ける。これにより、サージによるゲー
ト絶縁膜の破壊が防止され、高いＥＳＤ耐性が得られ
る。In the DMOS transistor of this embodiment, a state in which a breakdown current flows between a drain and a source due to a surge is shown in FIG.
(B). In the case of this embodiment, the gate electrode 9
Is outside the source electrode 11, so that the breakdown current does not flow directly below the gate electrode 9 but flows to the source electrode 11 as shown by the broken line. As a result, the gate insulating film is prevented from being damaged by the surge, and high ESD resistance is obtained.
【００２２】［実施の形態２］図２Ａはこの発明の別の
実施の形態によるＤＭＯＳトランジスタの平面図であ
り、図２Ｂは図２ＡのＡ−Ａ’断面図である。先の実施
の形態と対応する部分には先の実施の形態と同じ符号を
付して詳細な説明は省く。この実施の形態では、素子分
離された高抵抗ドレイン層３の表面の長手方向両端部に
ｐ型ベース層４ａ，４ｂが形成され、これらのベース層
４ａ，４ｂのそれぞれにｎ+型ソース層５ａ，５ｂが形
成されている。ｎ+型ドレイン・コンタクト層６は、二
つのベース層４ａ，４ｂの中間位置に一つ形成されてい
る。ベース層４ａ，４ｂのドレイン・コンタクト層６か
ら遠い方の周縁表面がそれぞれチャネル領域７ａ，７ｂ
とされ、ここにゲート絶縁膜８を介してゲート電極９
ａ，９ｂが形成されている。[Embodiment 2] FIG. 2A is a plan view of a DMOS transistor according to another embodiment of the present invention, and FIG. 2B is a sectional view taken along the line AA 'of FIG. 2A. Portions corresponding to those in the previous embodiment are denoted by the same reference numerals as in the previous embodiment, and detailed description is omitted. In this embodiment, p-type base layers 4a and 4b are formed at both ends in the longitudinal direction of the surface of the high-resistance drain layer 3 from which the element is separated, and an n + -type source layer 5a is formed on each of these base layers 4a and 4b. , 5b are formed. One n + -type drain contact layer 6 is formed at an intermediate position between the two base layers 4a and 4b. The peripheral surfaces of the base layers 4a and 4b remote from the drain contact layer 6 are channel regions 7a and 7b, respectively.
Here, the gate electrode 9 is interposed via the gate insulating film 8.
a, 9b are formed.
【００２３】この実施の形態のＤＭＯＳトランジスタ構
造は、先の実施の形態のゲート及びソース部分をドレイ
ンを挟んで対称的に二つ配置したものということができ
る。但しゲート電極９ａ，９ｂは、図２Ａに示すように
同じ多結晶シリコン膜等により連続的にパターン形成さ
れる。ソース層５ａ，５ｂとベース層４ａ，４ｂにコン
タクトするソース電極１１ａ，１１ｂも同様に、図２Ａ
に示したように連続的にメタル膜によりパターン形成さ
れる。In the DMOS transistor structure of this embodiment, it can be said that the gate and source portions of the above embodiment are symmetrically arranged with the drain interposed therebetween. However, the gate electrodes 9a and 9b are continuously patterned by the same polycrystalline silicon film or the like as shown in FIG. 2A. Similarly, the source electrodes 11a and 11b contacting the source layers 5a and 5b and the base layers 4a and 4b are shown in FIG.
As shown in (1), a pattern is continuously formed by a metal film.
【００２４】この実施の形態のＤＭＯＳトランジスタ構
造は、先の実施の形態に比べて電流容量を大きいものと
する場合に有効である。サージ耐量については、先の実
施の形態と同様の理由で改善される。The DMOS transistor structure of this embodiment is effective when the current capacity is increased as compared with the previous embodiment. The surge withstand capability is improved for the same reason as in the previous embodiment.
【００２５】［実施の形態３］図３は、更に別の実施の
形態によるＤＭＯＳトランジスタの平面図である。断面
図は先の実施の形態の図２Ｂと同じになるので省略し
た。この実施の形態では、ｐ型ベース層４、更にその中
のｎ+型ソース層５が、ドレイン・コンタクト層６を取
り囲むようにリング状に拡散形成されている。そして、
ベース層４の外周部表面を全てチャネル領域７として、
ゲート電極９もリング状にパターン形成されている。そ
の他、先の実施の形態１，２と同様である。この実施の
形態によっても、先の実施の形態と同様の効果が得られ
る。[Embodiment 3] FIG. 3 is a plan view of a DMOS transistor according to still another embodiment. The sectional view is omitted because it is the same as FIG. 2B of the previous embodiment. In this embodiment, the p-type base layer 4 and the n + -type source layer 5 therein are formed in a ring shape so as to surround the drain / contact layer 6. And
The entire outer peripheral surface of the base layer 4 is defined as a channel region 7.
The gate electrode 9 is also patterned in a ring shape. In other respects, the configuration is the same as in the first and second embodiments. According to this embodiment, the same effect as that of the previous embodiment can be obtained.
【００２６】［実施の形態４］ここまでの実施の形態
は、多数キャリアの伝導を利用する通常のＭＯＳトラン
ジスタであるが、この発明は導電変調型のＭＯＳトラン
ジスタ、即ちバイポーラ動作をするＩＧＢＴにも同様に
適用可能である。図４はその様な実施の形態のＩＢＧＴ
断面構造を、実施の形態１の図１Ｂに対応させて示して
いる。実施の形態１と異なる点は、実施の形態１のｎ+
型ドレイン・コンタクト層６の部分が、ｐ+型ドレイン
層４２となることである。また実施の形態１の高抵抗ド
レイン層３は、この実施の形態では機能的には第１ベー
ス層４１となり、実施の形態１と同様のｐ型ベース層４
が第２ベース層となる。平面図は図１Ａと同様であるの
で省略する。[Embodiment 4] Although the embodiments described so far are ordinary MOS transistors utilizing majority carrier conduction, the present invention is also applied to a conduction modulation type MOS transistor, that is, an IGBT which performs bipolar operation. It is equally applicable. FIG. 4 shows an IBGT of such an embodiment.
The cross-sectional structure is shown corresponding to FIG. 1B of the first embodiment. The difference from the first embodiment is that n +
That is, the portion of the type drain / contact layer 6 becomes the p + type drain layer 42. Further, the high-resistance drain layer 3 of the first embodiment is functionally a first base layer 41 in this embodiment, and is the same as the p-type base layer 4 of the first embodiment.
Becomes the second base layer. The plan view is the same as FIG.
【００２７】ＩＧＢＴにおいては、動作上、ゲート駆動
によりソース層５からの電子注入と、電子がドレイン層
４２に到達することによるドレイン層４２からのホール
注入とによる導電変調が起こる点が通常のＭＯＳトラン
ジスタと異なる。そして導電変調の効果により、低いオ
ン電圧が得られる。そしてこのＩＧＢＴの場合も、先の
各実施の形態と同様の理由でサージ耐量が大きいものと
なる。ＩＧＢＴについて、実施の形態２或いは実施の形
態３と同様のレイアウトを採用することももちろん有効
である。The operation of the IGBT in a normal MOS transistor is characterized in that the operation of the IGBT causes conduction modulation due to injection of electrons from the source layer 5 by driving the gate and injection of holes from the drain layer 42 when the electrons reach the drain layer 42. Different from transistors. Then, a low on-voltage can be obtained by the effect of the conductivity modulation. The IGBT also has a large surge withstand capability for the same reason as in the previous embodiments. Of course, it is also effective to adopt a layout similar to that of the second or third embodiment for the IGBT.
【００２８】［実施の形態５］図５は、実施の形態１を
変形した実施の形態のＤＭＯＳトランジスタの断面を図
１Ｂに対応させて示している。この実施の形態の半導体
基板１はＳＯＩ基板ではなく、支持基板としてのｐ-型
シリコン基板５１ａにｎ-型シリコン層５１ｂを例えば
エピタキシャル成長させたエピタキシャル基板を用いて
いる。また素子分離領域２も誘電体分離でなく、シリコ
ン基板１に達するｐ+型拡散層５２を形成したｐｎ接合
分離を利用している。その他は、実施の形態１と同様で
ある。この実施の形態によっても、ゲート、ソース、ド
レインの配置関係により、先の実施の形態と同様にサー
ジ耐量が高いものとなる。このｐｎ接合分離の構造で実
施の形態２，３と同様のレイアウトを採用した場合も同
様である。[Fifth Embodiment] FIG. 5 shows a cross section of a DMOS transistor according to a modification of the first embodiment, corresponding to FIG. 1B. The semiconductor substrate 1 of this embodiment is not an SOI substrate but an epitaxial substrate obtained by epitaxially growing an n − -type silicon layer 51b on a p − -type silicon substrate 51a as a support substrate. Also, the element isolation region 2 uses not a dielectric isolation but a pn junction isolation in which ap + type diffusion layer 52 reaching the silicon substrate 1 is formed. Others are the same as the first embodiment. Also in this embodiment, the surge withstand capability is high as in the previous embodiment, due to the positional relationship between the gate, source, and drain. The same applies to the case where the same layout as in the second and third embodiments is adopted in this pn junction isolation structure.
【００２９】[0029]
【発明の効果】以上述べたようにこの発明によれば、サ
ージによる降伏電流がゲート電極直下を流れないように
拡散層及び電極のレイアウトを考慮することにより、サ
ージ耐量を改善した絶縁ゲート型半導体装置を得ること
ができる。As described above, according to the present invention, by considering the layout of the diffusion layers and the electrodes so that the breakdown current due to the surge does not flow directly under the gate electrode, the insulated gate semiconductor with improved surge withstand capability is provided. A device can be obtained.
【図１Ａ】実施の形態１によるＤＭＯＳトランジスタの
平面図である。FIG. 1A is a plan view of a DMOS transistor according to a first embodiment.
【図１Ｂ】図１ＡのＡ−Ａ’断面図である。FIG. 1B is a sectional view taken along the line A-A ′ of FIG. 1A.
【図２Ａ】実施の形態２によるＤＭＯＳトランジスタの
平面図である。FIG. 2A is a plan view of a DMOS transistor according to a second embodiment.
【図２Ｂ】図２ＡのＡ−Ａ’断面図である。FIG. 2B is a sectional view taken along line A-A ′ of FIG. 2A.
【図３】実施の形態３によるＤＭＯＳトランジスタの平
面図である。FIG. 3 is a plan view of a DMOS transistor according to a third embodiment.
【図４】実施の形態４によるＩＧＢＴの断面図である。FIG. 4 is a sectional view of an IGBT according to a fourth embodiment.
【図５】実施の形態５によるＤＭＯＳトランジスタの断
面図である。FIG. 5 is a sectional view of a DMOS transistor according to a fifth embodiment.
【図６】出力回路の構成例である。FIG. 6 is a configuration example of an output circuit.
【図７】同出力回路に用いられるＤＭＯＳトランジスタ
の断面図である。FIG. 7 is a sectional view of a DMOS transistor used in the output circuit.
【図８】従来のＤＭＯＳトランジスタと実施の形態のＤ
ＭＯＳトランジスタのサージによる降伏電流の流れる様
子を示す図である。FIG. 8 shows a conventional DMOS transistor and D of the embodiment.
FIG. 6 is a diagram showing a state in which a breakdown current flows due to a surge of a MOS transistor.
１…半導体基板、１ａ…支持基板、１ｂ…絶縁膜、１ｃ
…シリコン層、２…素子分離領域、２ａ…素子分離溝、
２ｂ…絶縁膜、２ｃ…多結晶シリコン、３…高抵抗ドレ
イン層、４…ｐ型ベース層、５…ｎ+型ソース層、６…
ｎ+型ドレイン・コンタクト層、７…チャネル領域、８
…ゲート絶縁膜、９…ゲート電極、１０…絶縁膜、１１
…ソース電極、１２…ドレイン電極。DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 1a ... Support substrate, 1b ... Insulating film, 1c
... Silicon layer, 2 ... Element isolation region, 2a ... Element isolation groove,
2b ... insulating film, 2c ... polycrystalline silicon, 3 ... high-resistance drain layer, 4 ... p-type base layer, 5 ... n + type source layer, 6 ...
n + -type drain contact layer, 7 channel region, 8
... gate insulating film, 9 ... gate electrode, 10 ... insulating film, 11
... source electrode, 12 ... drain electrode.
Claims (7)
電型のドレイン層と、 このドレイン層の表面に形成された第２導電型のベース
層と、 前記ドレイン層の表面に前記ベース層から離れて形成さ
れた第１導電型のドレイン・コンタクト層と、 前記ベース層の表面に選択的に形成された第１導電型の
ソース層と、 前記ベース層の前記素子分離領域に近い側の周縁表面を
チャネル領域として、このチャネル領域上にゲート絶縁
膜を介して形成されたゲート電極と、 前記ソース層とベース層にコンタクトするソース電極
と、を有することを特徴とする絶縁ゲート型半導体装
置。1. A semiconductor substrate, a first conductivity type drain layer defined by an element isolation region in the semiconductor substrate, a second conductivity type base layer formed on a surface of the drain layer, and the drain layer A first conductivity type drain / contact layer formed on the surface of the base layer away from the base layer; a first conductivity type source layer selectively formed on the surface of the base layer; Having a peripheral surface on the side closer to the isolation region as a channel region, a gate electrode formed on the channel region via a gate insulating film, and a source electrode in contact with the source layer and the base layer. Gate type semiconductor device.
持基板上に第１の絶縁膜により支持基板と分離された状
態で形成された第１導電型の半導体層とを有し、 前記ドレイン層は、前記半導体層の一部が前記素子分離
領域により囲まれたものであることを特徴とする請求項
１記載の絶縁ゲート型半導体装置。2. The semiconductor substrate, comprising: a support substrate; and a first conductivity type semiconductor layer formed on the support substrate and separated from the support substrate by a first insulating film. 2. The insulated gate semiconductor device according to claim 1, wherein the layer has a part of the semiconductor layer surrounded by the element isolation region.
囲んで前記第１の絶縁膜に達する深さに形成された素子
分離溝と、この素子分離溝の少なくとも側壁に形成され
た第２の絶縁膜とを有することを特徴とする請求項２記
載の絶縁ゲート型半導体装置。3. The device isolation region includes a device isolation groove formed at a depth surrounding the drain layer and reaching the first insulating film, and a second isolation trench formed on at least a side wall of the device isolation groove. 3. The insulated gate semiconductor device according to claim 2, comprising an insulating film.
電極を拡散マスクの一部として用いた不純物の二重拡散
により形成されていることを特徴とする請求項１記載の
絶縁ゲート型半導体装置。4. The insulated gate semiconductor device according to claim 1, wherein said base layer and said source layer are formed by double diffusion of impurities using said gate electrode as a part of a diffusion mask. .
イン・コンタクト層を挟んで二箇所に配置されているこ
とを特徴とする請求項１記載の絶縁ゲート型半導体装
置。5. The insulated gate semiconductor device according to claim 1, wherein said base layer and said source layer are arranged at two places with said drain / contact layer interposed therebetween.
は、前記ドレイン・コンタクト層を取り囲んでリング状
に形成されていることを特徴とする請求項１記載の絶縁
ゲート型半導体装置。6. The insulated gate semiconductor device according to claim 1, wherein the base layer, the source layer, and the gate electrode are formed in a ring shape surrounding the drain / contact layer.
電型の第１ベース層と、 この第１ベース層の表面に形成された第２導電型の第２
ベース層と、 前記第１ベース層の表面に前記第２ベース層から離れて
形成された第２導電型のドレイン層と、 前記第２ベース層の表面に選択的に形成された第１導電
型のソース層と、 前記第２ベース層の前記素子分離領域に近い側の周縁表
面をチャネル領域として、このチャネル領域上にゲート
絶縁膜を介して形成されたゲート電極と、 前記ソース層と第２ベース層にコンタクトするように形
成されたソース電極と、を有することを特徴とする絶縁
ゲート型半導体装置。7. A semiconductor substrate, a first conductive type first base layer partitioned by an element isolation region in the semiconductor substrate, and a second conductive type second base layer formed on a surface of the first base layer.
A base layer; a second conductivity type drain layer formed on the surface of the first base layer away from the second base layer; and a first conductivity type selectively formed on the surface of the second base layer. A gate electrode formed on the channel region with a peripheral surface of the second base layer closer to the element isolation region as a channel region, with a gate insulating film interposed therebetween; A source electrode formed so as to be in contact with the base layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30605399A JP4175750B2 (en) | 1999-10-27 | 1999-10-27 | Insulated gate semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30605399A JP4175750B2 (en) | 1999-10-27 | 1999-10-27 | Insulated gate semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001127287A true JP2001127287A (en) | 2001-05-11 |
| JP4175750B2 JP4175750B2 (en) | 2008-11-05 |
Family
ID=17952493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30605399A Expired - Fee Related JP4175750B2 (en) | 1999-10-27 | 1999-10-27 | Insulated gate semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4175750B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005101581A (en) * | 2003-08-29 | 2005-04-14 | Fuji Electric Holdings Co Ltd | Semiconductor device |
| US6972458B2 (en) | 2002-12-18 | 2005-12-06 | Denso Corporation | Horizontal MOS transistor |
| CN101814526A (en) * | 2009-02-20 | 2010-08-25 | 株式会社半导体能源研究所 | Semiconductor device with and manufacture method |
| US7799667B2 (en) | 2003-06-13 | 2010-09-21 | Denso Corporation | Method for manufacturing semiconductor device with planer gate electrode and trench gate electrode |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104282740B (en) * | 2009-11-09 | 2017-03-01 | 苏州博创集成电路设计有限公司 | The transverse P-type igbt of silicon-on-insulator |
-
1999
- 1999-10-27 JP JP30605399A patent/JP4175750B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6972458B2 (en) | 2002-12-18 | 2005-12-06 | Denso Corporation | Horizontal MOS transistor |
| US7799667B2 (en) | 2003-06-13 | 2010-09-21 | Denso Corporation | Method for manufacturing semiconductor device with planer gate electrode and trench gate electrode |
| JP2005101581A (en) * | 2003-08-29 | 2005-04-14 | Fuji Electric Holdings Co Ltd | Semiconductor device |
| CN101814526A (en) * | 2009-02-20 | 2010-08-25 | 株式会社半导体能源研究所 | Semiconductor device with and manufacture method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4175750B2 (en) | 2008-11-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3262579B2 (en) | Metal oxide semiconductor field effect transistor circuit | |
| US5801420A (en) | Lateral semiconductor arrangement for power ICS | |
| US6894348B2 (en) | Semiconductor device | |
| JP3346825B2 (en) | Power semiconductor device and method of manufacturing the same | |
| JP2002532905A (en) | Lateral thin film silicon-on-insulator (SOI) JFET device | |
| JPH0883897A (en) | Mos control type thyristor | |
| JPH01112764A (en) | Semiconductor device | |
| US5889310A (en) | Semiconductor device with high breakdown voltage island region | |
| US5608238A (en) | Semiconductor device having two insulated gates and capable of thyristor function and method for operating the same | |
| US6563193B1 (en) | Semiconductor device | |
| US5874767A (en) | Semiconductor device including a lateral power device | |
| JP3489404B2 (en) | Insulated gate semiconductor device | |
| JPH0851197A (en) | Mos control thyristor having electric current saturation property | |
| JP4175750B2 (en) | Insulated gate semiconductor device | |
| JPH1065018A (en) | Semiconductor device | |
| US8698194B2 (en) | Semiconductor integrated circuit with high withstand voltage element forming trench isolation on substrate | |
| JP3161091B2 (en) | Semiconductor integrated circuit device | |
| JP2004006555A (en) | Semiconductor device | |
| JPH06151863A (en) | Semiconductor device | |
| JP2825038B2 (en) | Semiconductor device | |
| JPH11195784A (en) | Insulated-gate semiconductor element | |
| JPH05190561A (en) | Semiconductor device | |
| JPH1174517A (en) | Semiconductor device | |
| JPH08130312A (en) | Lateral semiconductor device and its use | |
| JPH055373B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20040607 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060410 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20071127 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080128 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080226 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080428 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080527 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080714 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20080812 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20080819 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110829 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110829 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120829 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120829 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130829 Year of fee payment: 5 |
|
| LAPS | Cancellation because of no payment of annual fees |