JP2007258501A - Dielectric separated the semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To minimize the area of an insulated separation region of a dielectric separated type semiconductor device, and to avoid the increase of ON-resistance. <P>SOLUTION: In the dielectric separated type semiconductor device, the impurity concentration of the inside of a well region, in which the inversion layer of an MOS (metal oxide semiconductor) transistor or a channel is formed, is higher than that in the surface thereof, and the well region is contacted with a drain region of low impurity concentration. A depletion layer, formed on impressing the drain voltage, is suppressed so as to be narrow and short-channel effect will not be caused; and even when the source region is made to further approach the drain region, the MOS transistor, having a short gate length, is available whereby the transfer conductance gm can be increased, and the gate width can be contracted. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device that uses a dielectric isolation method for element isolation, and more particularly to a semiconductor device that optimally controls a power device that drives a high-power motor.

  In a semiconductor device that optimally controls a power device, each element is surrounded by a dielectric material such as a silicon oxide film, and the elements and between the element and the substrate are insulated and separated at a high voltage, a high voltage element, a large current output circuit, In addition, a dielectric isolation type semiconductor device in which a low-breakdown-voltage logic circuit is integrated has been proposed. Patent Document 1 discloses an example of such a semiconductor device.

  FIG. 14 shows an example of a motor drive system using a dielectric separation type semiconductor device. From an IGBT module that drives a motor of a load, a drive circuit that basically includes two upper and lower MOS transistors that control the switching operation of the IGBT module, and a dielectric isolation type semiconductor device that optimally controls the drive circuit Become. Here, the dielectric isolation type semiconductor device includes a control logic circuit that interfaces with a high voltage side gate drive circuit and a high voltage MOS transistor that supplies a control signal to the drive circuit, and a digital control IC that controls the entire system, Although not shown in the figure, it includes various protection circuits.

In FIG. 14, the elements constituting the high-voltage side gate drive circuit and the low-voltage side gate drive circuit have a MOS transistor structure, and a cross-sectional view of a typical element structure is shown in FIG. In FIG. 12, reference numeral 1 denotes an n ⁺ type high impurity concentration source region, 2 denotes a gate electrode, 3 denotes an n ⁺ type high impurity concentration drain region, and 30 denotes an n ⁻ type low impurity concentration. This is the drain region. Numeral 140 in FIG. 12, a low impurity concentration n ^- p-type well region formed on the first surface of the silicon substrate 11, 61, a low impurity concentration in which the MOS transistors are formed n ^- silicon A dielectric separation layer 150 for insulating and separating the substrate 11 is an n ⁺ type high impurity concentration layer provided adjacent to the dielectric separation layer 61. Figure 13, for each region n in the drain region ^- is a diagram showing the respective regions, the impurity concentration in the depth direction from the silicon surface of the silicon substrate 11. The p-type well region 140 has a distribution in which the impurity concentration does not change from the surface.

  Since the drain region 3 having a high impurity concentration is surrounded by the drain region 30 having a low impurity concentration, the avalanche voltage at the drain junction is increased, and a higher voltage than a normal logic MOS transistor, for example, a medium voltage of 15 to 30 V can be controlled. It is a MOS transistor. Thereby, the gate drive circuit composed of the MOS transistor can generate an output voltage of 15V to 20V necessary for a control signal of the MOS transistor for driving the IGBT module at the next stage.

  Furthermore, since the gate drive circuit must charge and discharge the gate voltage of the MOS transistor at the next stage at a sufficient speed, a predetermined output current is required. For this reason, the MOS transistor constituting the drive circuit is designed to have a large gate width to obtain a necessary drain current. The output current of a normal gate drive circuit is 0.5A to 1A. Since the gate width for obtaining such a large current is usually on the order of several millimeters, the planar layout area becomes large and occupies most of the element area of the dielectric isolation type semiconductor device in FIG. For this reason, it is indispensable to increase the current of the MOS transistor of the gate drive circuit in order to reduce the size of the dielectric isolation type semiconductor device and reduce the cost.

  However, in the case of the MOS transistor having the structure shown in FIGS. 12 and 13, in order to increase the current, the distance between the source and the drain, that is, the gate length is shortened to increase the transfer conductance gm of the transistor. There is a need.

Japanese Unexamined Patent Publication No. 2001-251886 (description of FIGS. 1 and 9)

  However, since the conventional MOS transistors shown in FIGS. 12 and 13 have the drain region 30 having a low impurity concentration deeper than that of the source region 1 in order to obtain a drain junction breakdown voltage of a medium voltage, if the gate length is shortened, this deep An element structure in which the gate length cannot be shortened because the electric field from the drain region has a significant effect on the distribution of charges, and thus the transistor characteristics deteriorate, such as a decrease in threshold voltage, a decrease in breakdown voltage, and an increase in transistor leakage current. There are the above restrictions.

  An object of the present invention is a novel element structure that does not cause deterioration of element characteristics due to a short channel effect even if the gate length of a MOS transistor constituting a drive circuit of a dielectric isolation type semiconductor device is shortened to improve gm. Another object is to provide a semiconductor device capable of reducing the area of a gate driving circuit.

  The semiconductor device of the present invention has a dielectric isolation structure with a substantially vertical deep trench, and the well region of a medium breakdown voltage MOS transistor having an element breakdown voltage about the gate voltage of a high breakdown voltage element has a low impurity concentration deeper than that of the source region. The impurity concentration is higher than that near the surface deeper than the drain region.

  According to the semiconductor device of the present invention, the insulation isolation region can be minimized, and an increase in on-resistance can be prevented.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following drawings, the same portions are denoted by the same reference numerals, and description of each drawing is omitted.

  The dielectric isolation type semiconductor device of the present embodiment selects a semiconductor, particularly silicon, as a semiconductor material, uses an SOI (Silicon on Insulator) substrate advantageous for dielectric isolation, and reaches an intermediate silicon oxide film from the main surface. After forming a deep trench (groove) and filling the trench with a dielectric such as a silicon oxide film and polycrystalline silicon, dielectric isolation is performed, and then a predetermined LOCOS (local oxidation of silicon) method is used to define a region for forming a MOS transistor. After forming the well region of the present invention by appropriately setting an accelerating voltage for implanting impurities in the ion implantation technique, a thick oxide film is formed in this region. Forming and processing crystalline silicon, and adding the normal ion implantation technique and heat treatment process to form the source region, drain region, and other active regions Realize by doing.

FIG. 1 is a cross-sectional view of a dielectric isolation type semiconductor device according to this embodiment, which is applied to an nMOS transistor 100 for forming an n-type channel. In FIG. 1, only an nMOS transistor is shown, and other elements are omitted. An n ⁺ -type silicon layer 9 having a low resistance, that is, a high impurity concentration, and an n ⁻ -type silicon layer 10 having a high resistance, that is, a low impurity concentration, are disposed on a semiconductor substrate, particularly the silicon substrate 5, via a silicon oxide film 6. A so-called SOI substrate is formed in which are stacked. A substantially vertical groove reaching the silicon oxide film 6 from the main surface of the n ⁻ -type silicon layer 10 is formed, and a dielectric member is embedded in the groove to form a dielectric isolation groove 7. The planar shape of the groove is a closed loop and has a function of insulating and separating the inside and the outside. N ⁺ -type silicon layers 8 are formed on both sides of the dielectric isolation trench 7. A p-type well region 90 having a high impurity concentration from the main surface to the inside of the n ⁻ -type silicon layer 10 is adjacent to the p-type well region 90 and has a lower impurity concentration than the p-type well region 90 to the main surface. Well regions 91 are respectively formed. A thin silicon oxide film (not shown in FIG. 1) is formed on the main surfaces of the p-type well regions 90 and 91, and the gate electrode 2 made of polycrystalline silicon is disposed thereon. On one side of the gate electrode, an n ⁺ type silicon source region 1 is formed in a p type well region 91. On the other side opposite to the source region 1, an n ⁻ -type silicon drain region 30 having a lower impurity concentration and deeper than the source region 1 is formed, and an n ⁺ -type silicon drain region 3 is disposed in the drain region 30. ing.

1 from the surface to the inside of the drain region, that is, the drain region 3, the low impurity concentration drain region 30, the low impurity concentration p-type well region 91, the high impurity concentration p-type well region 90, and The impurity concentration distribution of the n ⁻ -type silicon layer 10 is shown in FIG. In FIG. 2, the concentration of the high impurity concentration p-type well region 90 formed therein is preferably set to about 5 to 10 times slightly higher than that of the low impurity concentration drain region 30. In addition, since the p-type well region 90 having a high impurity concentration exists in the MOS transistor according to the present embodiment, the parasitic region constituted by the drain regions 3 and 30, the p-type well regions 90 and 91, and the n ⁻ -type silicon layer 10. The operation of the npn bipolar transistor can be greatly improved.

  According to this embodiment, in the well region where the channel which is the inversion layer of the MOS transistor is formed, the impurity concentration inside is higher than the surface, and is in contact with the drain region having a low impurity concentration. Therefore, a depletion layer formed when a drain voltage is applied is suppressed to be narrow, and a short channel effect does not occur even when the source region and the drain region are brought closer to each other. Therefore, the MOS transistor having a short gate length can be used, so that the transfer conductance gm can be increased and the gate width can be reduced.

FIG. 3 is a sectional view of the dielectric isolation type semiconductor device according to this embodiment. The dielectric isolation type semiconductor device of this embodiment includes a high breakdown voltage pMOS transistor 300, a medium breakdown voltage nMOS transistor 100, and a medium breakdown voltage pMOS transistor 200. In the medium breakdown voltage pMOS transistor 200, a p ⁻ type low impurity concentration drain region 40, an n type well region 80 having a slightly high impurity concentration deeper than the low impurity concentration drain region 40, and an n type Low impurity concentration n-type well regions 81 formed adjacent to the well region 80 are formed. Similarly to the nMOS transistor 100, the medium breakdown voltage pMOS transistor 200 can shorten the channel, so that the transfer conductance gm can be increased and the gate length can be shortened.

  According to the present embodiment, when the gate drive circuit is constituted by the CMOS circuit of the nMOS transistor 100 and the pMOS transistor 200, the chip area can be reduced and the power consumption of the CMOS circuit can be simultaneously achieved. At this time, since the nMOS transistor 100 and the pMOS transistor 200 are individually separated by the dielectric isolation groove 7, the pnpn parasitic thyristor structure is not formed. Therefore, it is possible to eliminate the defect of element destruction due to the latch-up phenomenon of the CMOS circuit. Further, in this embodiment, the p-type well regions 90 and 91 of the nMOS transistor are shared as the drain layer of the high breakdown voltage pMOS transistor 300. Therefore, the impurity concentration is higher than that of the drain of the prior art, and it is less affected by the impurity charge that is induced by the high applied voltage of the high breakdown voltage pMOS and accumulated on the thin oxide film 50, thereby reducing the breakdown voltage of the transistor. A highly reliable pMOS transistor that can be avoided can be realized.

FIG. 4 is a cross-sectional view of the dielectric isolation type semiconductor device of this example. The dielectric isolation type semiconductor device of this embodiment includes a high breakdown voltage nMOS transistor 400, a medium breakdown voltage nMOS transistor 100, and a medium breakdown voltage pMOS transistor 200. In FIG. 4, reference numeral 41 denotes an n ⁺ type silicon source region, the source of the nMOS transistor 400, and 40 a drain region, which is generally called a p body and is an area where an n type channel is formed by the gate electrode 2. The source region 41 and the channel of the drain region 40 have a DMOS structure in which the channel is formed in a self-aligned manner with respect to the gate electrode 2. In the collector, an n ⁺ -type silicon layer 43 with a high impurity concentration and n-type well regions 80 and 81 arranged with a medium breakdown voltage nMOS surrounding this region are arranged to reduce the electric field.

FIG. 5 is a cross-sectional view of the dielectric isolation type semiconductor device according to this embodiment. The dielectric isolation type semiconductor device of this embodiment includes a high breakdown voltage IGBT transistor 500, a medium breakdown voltage nMOS transistor 100, and a medium breakdown voltage pMOS transistor 200. Reference numeral 51 in FIG. 5 is an n ⁺ type silicon emitter region, 40 is an IGBT p body called a drain region in which an n type channel is formed by the bias of the gate electrode 2, and 53 is a p ⁺ type silicon collector region. An n-type silicon region 531 surrounding the collector region 53 is arranged as shown in FIG. 5 and controls the injection of holes from the collector region 53. In some cases, the n-type well regions 80 and 81 may be disposed so as to further surround the n-type silicon region 531 similarly to the drain of the high voltage nMOS transistor shown in FIG.

  FIG. 6A shows a planar pattern arranged for each functional block of the dielectric isolation type semiconductor device of Examples 1 to 4 shown in FIGS. 1, 3, 4, and 5. FIG. The planar pattern in FIG. 6A shows the case of a three-phase driver IC. In the upper arms of the U-phase, V-phase, and W-phase, level shift circuits composed of high voltage nMOS transistors and pMOS transistors are arranged in the vicinity. Protecting the U phase, V phase, and W phase to protect the device from destruction due to overcurrent of the power semiconductor device and the like in the inverter system using the dielectric isolation type semiconductor device of the first to fourth embodiments, and heating A circuit is provided and arranged. Further, bonding pads are arranged around a control circuit for interfacing with the microcomputer and a power supply circuit for generating various power supplies. FIG. 6B shows a planar pattern of a medium voltage MOS transistor used in each drive circuit in the planar pattern shown in FIG. However, not all of the drive circuit is shown, but a part of it is shown. The planar pattern is the same for both nMOS and pMOS. In this planar pattern, the gate electrode 2 is constituted by connecting a plurality of these in parallel with a predetermined gate length Lg and a predetermined gate width Wg as a basic unit.

  FIG. 7 is a cross-sectional view of the dielectric isolation type semiconductor device according to this example. The dielectric isolation type semiconductor device of the present embodiment includes a medium breakdown voltage nMOS transistor 100 and a medium breakdown voltage pMOS transistor 200. In the case of a semiconductor device in which many semiconductor elements are integrated on the same silicon substrate, a source region 1, a channel region, a gate region, a drain region 3 and the like of each transistor are formed on the main surface of silicon. In order to separate them from each other, a region where an oxide film is formed is disposed.

  In the dielectric isolation type semiconductor device of the present embodiment, the oxide film has at least two types of regions of a thin oxide film 50 portion and a thick oxide film 60 portion. This is because the thick oxide film 60 is electrically insulated from the underlying silicon substrate even if the wiring laid out thereon has a high potential. Specifically, when a voltage of 600 V is applied, the thickness of the oxide film needs to be at least 4 μm.

  In the case of the present embodiment, the n-type well regions 80 and 81 and the p-type well regions 90 and 91 of the nMOS transistor 100 and the pMOS transistor 200 correspond to the region where the thick oxide film 60 is formed. And self-aligned. By this self-alignment method, the well region is efficiently formed in area, so that the area of the MOS transistor can be reduced.

FIG. 8 is a cross-sectional view of the dielectric isolation type semiconductor device of this example. The dielectric isolation type semiconductor device of this embodiment includes an nMOS transistor 100 having a medium breakdown voltage. Drain region being arranged overlapping with the gate electrode 2 at the upper and lower the n ^- only type silicon drain region 33, the drain region 3 of the n ⁺ -type silicon having a high impurity concentration is located between the gate electrode 2 is offset . Since the offset structure is adopted, the deep low impurity concentration drain region shown in FIGS. 1 to 7 is not necessary in this embodiment. Even in the structure as shown in FIG. 8, since the p-type well region 90 having a high impurity concentration is provided inside, a MOS transistor having a short channel structure can be realized.

  9 and 10 show details of the method for manufacturing the dielectric isolation type semiconductor device of this embodiment. In this example, a manufacturing process of the semiconductor device of Example 2 will be described.

9A, an SOI substrate is prepared in which an n ⁻ -type silicon layer 10 is laminated on one surface of a silicon substrate 5 with a silicon oxide film 6 interposed therebetween. In this case n ^- -type silicon layer 10 is an n ⁺ -type silicon layer 9 provided on the surface in contact with the silicon oxide film 6.

In FIG. 9B, a trench reaching the buried silicon oxide film 6 from the main surface of the n ⁻ -type silicon layer 10 is formed in a vertical shape using a dry etching apparatus. The width of this groove is around 2 μm. After forming the vertical groove, an n ⁺ -type silicon layer 8 is formed by doping an n-type impurity on the side wall of the groove by a vapor phase diffusion method. Thereafter, heat treatment is performed in an oxidizing atmosphere to form a silicon oxide film 71 on the sidewall. Thereafter, polycrystalline silicon is deposited and filled in the gaps of the grooves by the CVD method to form the dielectric separation grooves 7.

  In FIG. 9C, the selective oxidation method using the silicon nitride film is repeated twice to form a thick oxide film 60 region and a thin oxide film 50 region. In some cases, the selective oxidation method is repeated three times to form three types of oxide films having different thicknesses.

In FIG. 10D, the photoresist member 110 is used as a masking member, an opening window is provided in a predetermined region, the acceleration energy of the ion implantation apparatus is set to a high energy of, for example, 1 MeV, and phosphorus is used for n-type impurities, p-type. As impurities, boron is implanted to form high impurity concentration n-type well region 80 and p-type well region 90 inside the silicon. Subsequently, the acceleration voltage is reduced to about 500 keV and the same element is ion-implanted to form a p-type well region 91 and an n-type well region 81 having a low impurity concentration. At this time, since the interface between the oxide film and the silicon substrate is doped at a concentration according to the acceleration voltage in the ion implantation method, the concentration in the interface region due to the segregation phenomenon of boron at the oxide film and the silicon interface does not occur. Absent. In this embodiment, the doping amount of the p-type well regions 90 and 91 is in the range of 2 × 10 ¹² pieces / cm ² to 1 × 10 ¹³ pieces / cm ² . Similarly, the n-type well regions 80 and 81 are formed by ion implantation using phosphorus element in an amount of 2 × 10 ¹² pieces / cm ² to 1 × 10 ¹³ pieces / cm ² .

Thereafter, in FIG. 10E, although not shown, a silicon oxide film is formed on the main surface of the n ⁻ -type silicon layer 10 to a thickness of 50 to 80 nm to form a gate oxide film. A polycrystalline silicon film is formed on the gate oxide film, and the polycrystalline silicon film is patterned with a normal dry etching apparatus to form the gate electrode 2. Next, a drain region 30 which is an n body of a high breakdown voltage pMOS and an n-type drain region 30 of an nMOS transistor are formed simultaneously with the gate electrode 2 in a self-aligned manner. The p ⁻ -type low-concentration drain region 40 of the pMOS transistor is also formed by doping phosphorus element by ion implantation.

  In FIG. 10F, the source regions 1 and 21, the drain regions 3 and 23, and the source region 31 and the drain region 33 of the high breakdown voltage pMOS transistor are masked with the gate electrode 2 and the thin oxide film 50 by ion implantation. Form in a self-aligning manner. After that, a silicon oxide film is formed by a CVD method, for example, in a process necessary for a normal semiconductor manufacturing apparatus, and a dry etching apparatus is used on each element where electrical connection such as a source, collector, and gate is necessary. A step of opening, a step of forming and processing an electrode mainly composed of aluminum by a sputtering method, a final passivation step, and the like are performed, but are omitted in the drawing.

  FIG. 11 shows details of the method of manufacturing the dielectric isolation type semiconductor device of this example. In this example, a manufacturing process of the semiconductor device of Example 5 will be described. In this embodiment, the method of manufacturing a semiconductor device using an SOI substrate is shown, but the SOI substrate itself is not shown in the manufacturing method. Further, only the portion where the well region of the MOS transistor is formed by a self-alignment process is shown, and other steps are omitted.

FIG. 11A shows a process after oxide film regions having different thicknesses, that is, a thick oxide film 60 and a thin oxide film 50 are formed on the main surface of the n ⁻ -type silicon layer 10. A photoresist member 110 is applied to a predetermined thickness, and an opening for ion implantation is formed by a normal photolithography method. In this embodiment, first, since the p-type well region of the nMOS transistor 100 is formed, the photoresist in the nMOS transistor region is opened. Thereafter, a p-type well region having a deep portion and a shallow surface portion is formed by an ion implantation method with a two-level acceleration voltage. At this time, since the acceleration voltage is low in the thick oxide film 60 region, ions do not permeate and remain in the oxide film, and the p-type well region formed in the n ⁻ -type silicon layer 10 has a thick oxide film 60. It is formed in a self-aligned area other than.

  In FIG. 11B, the n-type well region for the pMOS transistor is formed by using the photo process and the ion implantation method in the same manner as the method for forming the p-type well region of the nMOS transistor shown in FIG. It is formed by a self-alignment process using a thick oxide film 60.

  As shown in the embodiment, since each semiconductor element is dielectrically isolated by a substantially vertical deep trench, the insulation isolation region can be minimized. In particular, the drain region of the MOS transistor constituting the gate drive circuit is composed of a low impurity concentration region and a high impurity concentration region, and in the well region where the channel is formed, the internal impurity concentration is higher than that of the surface. Because it is in contact with the low impurity concentration drain region, the depletion layer formed when the drain voltage is applied is kept narrow, and even if the source region and the drain region are brought closer, a short channel effect occurs. There is nothing. Therefore, the MOS transistor having a short gate length can be used, so that the transfer conductance gm can be increased and the gate width can be reduced. As a result, the layout area of the gate driving circuit composed of MOS transistors can be reduced, and the cost reduction can be achieved due to the small size of the dielectric isolation type semiconductor device.

In each of the embodiments described above, the n ⁺ -type silicon layers 8 and 9 with high impurity concentration are formed adjacent to the sidewalls of the dielectric isolation trench and the buried oxide film 6. The present invention can be applied even when the body separation type structure is used as a basis.

1 is a cross-sectional view of a dielectric isolation type semiconductor device of Example 1. FIG. In the dielectric isolation type semiconductor device of Example 1, it is a figure which shows impurity concentration distribution in each area | region along the inside from the silicon surface in the drain region of a MOS transistor. 6 is a cross-sectional view of a dielectric isolation type semiconductor device of Example 2. FIG. 7 is a cross-sectional view of a dielectric isolation type semiconductor device of Example 3. FIG. 7 is a cross-sectional view of a dielectric isolation type semiconductor device of Example 4. FIG. FIG. 10 is a plan view of a dielectric isolation type semiconductor device of Example 5. 6 is a sectional view of a dielectric isolation type semiconductor device according to Example 6. FIG. 7 is a cross-sectional view of a dielectric isolation type semiconductor device of Example 7. FIG. It is explanatory drawing of the manufacturing process of the dielectric material isolation type semiconductor device of Example 8. FIG. It is explanatory drawing of the manufacturing process of the dielectric material isolation type semiconductor device of Example 8. FIG. It is explanatory drawing of the manufacturing process of the dielectric isolation type semiconductor device of Example 9. FIG. It is sectional drawing of the dielectric isolation type semiconductor device of a prior art. It is a figure which shows impurity concentration distribution in each area | region along the inside from the silicon | silicone surface in the drain region of the dielectric material isolation type semiconductor device of a prior art. It is a block diagram which shows the motor drive system to which the dielectric material separation type semiconductor device of a prior art is applied.

Explanation of symbols

1, 21, 31, 41 ... source region, 2 ... gate electrode, 3, 23, 30, 33, 40 ... drain region, 5 ... silicon substrate, 6, 71 ... silicon oxide film, 7 ... dielectric isolation trench, 8 , 9, 43... N ⁺ type silicon layer, 10... N ⁻ type silicon layer, 11... N ⁻ silicon substrate, 50... Thin oxide film, 51... Emitter region, 53. 61 ... Dielectric isolation layer, 80, 81 ... n-type well region, 90, 91 ... p-type well region, 100 ... nMOS transistor, 110 ... photoresist member, 140 ... well region, 150 ... n ⁺ type high impurity concentration layer, 200, 300 ... pMOS transistor, 400 ... nMOS transistor, 500 ... IGBT transistor, 531 ... n-type silicon region.

Claims (10)

A SOI substrate in which a silicon oxide film and a silicon layer are stacked on a silicon substrate has a plurality of high-voltage gate drive circuits and low-voltage gate drive circuits with dielectric isolation grooves extending from the main surface of the silicon layer to the silicon oxide film. In the dielectric isolation type semiconductor device formed in the region,
The MOS transistor of the gate drive circuit includes a drain layer having a low concentration and deeper than the source on the drain side, and a well region in a region deeper than the low concentration drain layer is a well region in an impurity concentration layer region higher than the surface portion. A dielectric isolation type semiconductor device characterized by the above. In claim 1,
2. The dielectric isolation type semiconductor device according to claim 1, wherein the well region is a region formed in a self-aligned manner with respect to a planar shape of a silicon oxide film formed on the element isolation region. In claim 1,
2. The dielectric isolation type semiconductor device according to claim 1, wherein the well region is shared with a drain region or a collector region of a high breakdown voltage element. In claim 1,
2. A dielectric isolation type semiconductor device, wherein a low concentration drain region of a MOS transistor constituting the gate driving circuit is shared with a body region forming a channel of a high breakdown voltage element. A SOI substrate in which a silicon oxide film and a silicon layer are stacked on a silicon substrate has a plurality of high-voltage gate drive circuits and low-voltage gate drive circuits with dielectric isolation grooves extending from the main surface of the silicon layer to the silicon oxide film. In the dielectric isolation type semiconductor device formed in the region,
The MOS transistor of the gate driving circuit has a drain layer having a low concentration and a deeper depth than the source on the drain side, and the well region has a multilayer structure of at least two layers of a low impurity concentration region and a high impurity concentration region. A dielectric-separated semiconductor device. In claim 5,
2. The dielectric isolation type semiconductor device according to claim 1, wherein the well region is a region formed in a self-aligned manner with respect to a planar shape of a silicon oxide film formed on the element isolation region. In claim 5,
2. The dielectric isolation type semiconductor device according to claim 1, wherein the well region is shared with a drain region or a collector region of a high breakdown voltage element. In claim 5,
2. A dielectric isolation type semiconductor device, wherein a low concentration drain region of a MOS transistor constituting the gate driving circuit is shared with a body region forming a channel of a high breakdown voltage element. Preparing an SOI substrate in which a silicon oxide film and a silicon layer are laminated on a silicon support substrate;
Forming a substantially vertical dielectric isolation groove reaching the silicon oxide film from the main surface of the silicon layer;
Filling the isolation trench with a thermal oxide film and polycrystalline silicon;
Forming an oxide film having at least two kinds of film thicknesses for separating the element active layer by selective oxidation;
Forming a well region having a different impurity concentration in the depth direction by using the opening window of the same ion implantation mask by changing the acceleration voltage in the ion implantation apparatus after forming the oxide film. A method of manufacturing a dielectric isolation type semiconductor device. In claim 9,
After forming the oxide film, an impurity is implanted at a first acceleration voltage by the ion implantation apparatus, and an impurity is implanted at a second acceleration voltage lower than the first acceleration voltage. Type semiconductor device manufacturing method.

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