JP2010212588A - Semiconductor element, semiconductor device and method for manufacturing the semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce manufacturing cost of an overall circuit that is integrated an ESD protective element. <P>SOLUTION: The ESD protective element 100 includes an n-channel GGFET structure. In the ESD protective element 100, a first p<SP>+</SP>-low resistive region 41 is provided, at a part of a first p-well region 4, a first p<SP>++</SP>-contact region 5 and a region below the same, an n<SP>++</SP>-source region 8 and a region below it, a first LDD region 6 and a region below the same, a first gate insulating film 12 and a region below the same, a second LDD region 7 and a region below the same, and a part of an n<SP>++</SP>-drain region 9 and a region below the same. A first extension distance(LBP1) between a edge of the n<SP>++</SP>-drain region 9 side of the first p<SP>+</SP>-low resistive region 41 and a edge of the n<SP>++</SP>-drain region 9 side of a first gate electrode 13 is in a range of 0-0.3 μm. The first p<SP>+</SP>-low resistive region 41 of the ESD protection element 100 is formed, at the same time as low-resistive region of a high-breakdown voltage device. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor element, a semiconductor device, and a method for manufacturing a semiconductor element.

  In general, a power IC (Integrated Circuit: integrated circuit) includes, for example, a logic circuit such as a CMOS (Complementary Metal Oxide Semiconductor: Complementary MOS), an IGBT (Insulated Gate Bipolar Transistor), and an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor). High voltage devices such as Metal Oxide Semiconductor Field Effect Transistor (insulated gate field effect transistor) are integrated. In a semiconductor device constituting a high breakdown voltage device or a CMOS, current capability increases as the gate oxide film becomes thinner. That is, by reducing the thickness of the gate oxide film, each semiconductor element can be reduced in size without changing the current capability of each semiconductor element constituting the power IC. Therefore, the device mounting area can be reduced, and the power IC can be miniaturized.

  In response to the reduction in the thickness of the gate oxide film, in the semiconductor element constituting the CMOS, for example, the dimensions of various parameters of the element structure are reduced so as to keep the internal electric field of the semiconductor element constant. However, by miniaturizing the CMOS, the electric field strength near the drain region increases and hot carriers are generated. Some of the hot carriers injected into the gate oxide film are accumulated in the gate oxide film, causing deterioration of characteristics such as the threshold voltage and transfer conductance of the CMOS. Further, by reducing the thickness of the gate oxide film, the leakage current between the source and the drain increases, and the power consumption during standby increases. For this reason, for example, a circuit power supply voltage used as a CMOS power supply voltage needs to be reduced. For example, as a technique for reducing the circuit power supply voltage, a technique for reducing the power supply voltage from 5 V to 3.3 V has been proposed (for example, see Non-Patent Document 1 below).

  In order to improve hot carrier resistance in a semiconductor element constituting a CMOS, for example, the same conductivity type as the source region and the drain region is formed between the source region and the drain region, which is shallower than the source region and the drain region. An LDD (Lightly Doped Drain) structure has been proposed in which an impurity region is provided to reduce an electric field in the vicinity of a drain region of a semiconductor element. As a result, the leakage current in the off state due to the tunnel effect can be suppressed.

  On the other hand, in a high withstand voltage device, since the power supply voltage is determined by the application used, it is difficult to reduce the power supply voltage of the high withstand voltage device. If the gate oxide film of the high breakdown voltage device is thinned without changing the power supply voltage of the high breakdown voltage device, the electric field strength in the gate oxide film is increased. When the gate drive voltage of the high withstand voltage device is, for example, 5 to 7 V used for the circuit power supply voltage, the gate oxide film of the high withstand voltage device can be thinned to a thickness of 15 to 17 nm. In this case, the electric field strength applied to the gate oxide film during the operation of the high breakdown voltage device is 3.3 to 4.6 MV / cm, but various reliability such as the reliability of the gate oxide film of the high breakdown voltage device is available. Secured.

  As described above, in each semiconductor element constituting the power IC, the gate oxide film can be thinned while ensuring reliability. However, the resistance of the semiconductor element to electrostatic discharge (ESD) decreases. Therefore, a power IC is usually provided with a protection element (hereinafter referred to as an ESD protection element) for protecting the internal circuit from electrostatic discharge.

  An example of a conventional ESD protection element is shown below. In this specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached.

  FIG. 29 is a circuit diagram illustrating an example of an ESD protection element. As shown in FIG. 29, the ESD protection element 205 has a MOSFET (GGFET: Gate-Ground Field Effect Transistor) structure in which a source and a gate are short-circuited. An n-channel GGFET 202 and a p-channel GGFET 203 are connected to a signal line that connects a bonding pad (hereinafter referred to as PAD) 201 and the internal circuit 204. The source of the n-channel GGFET 202 is connected to the ground, for example. The drain of the n-channel GGFET 202 is electrically connected to the PAD 201. The source of the p-channel GGFET 203 is connected to the power supply voltage. The drain of the p-channel GGFET 203 is electrically connected to the PAD 201.

  In the ESD protection element 205, when a voltage surge with positive static electricity is generated in the PAD 201, the n-channel GGFET 202 draws the voltage surge and releases the static electricity to the ground. On the other hand, when a voltage surge with negative static electricity occurs in the PAD 201, the p-channel GGFET 203 draws the voltage surge and releases the static electricity to the power supply voltage. Thus, a voltage surge due to ESD or the like is prevented from flowing to the internal circuit 204.

FIG. 30 is a cross-sectional view showing a conventional ESD protection element. 30 shows an n-channel GGFET 202 constituting the ESD protection element shown in FIG. A p-well region 301 is provided on the surface of a support substrate (not shown). An n ⁺⁺ source region 304 and an n ⁺⁺ drain region 305 are provided apart from each other in part of the surface layer of the p well region 301. Between the n ⁺⁺ source region 304 and the n ⁺⁺ drain region 305, so as to be in contact with the n ⁺⁺ source region 304, a source (LDD) region 302 is provided shallower than n ⁺⁺ source region 304. Further, so as to be in contact with the n ⁺⁺ drain region 305, a drain (LDD) region 303 is provided shallower than n ⁺⁺ drain region 305.

a part of the surface of the p-well region 301, over the n ⁺⁺ source region 304 to the n ⁺⁺ drain region 305, a gate insulating film 306 is provided. The gate electrode 307 is provided on the surface of the gate insulating film 306. Source electrode 308 is provided on the surface of n ⁺⁺ source region 304. The drain electrode 309 is provided on the surface of the n ⁺⁺ drain region 305. The drain electrode 309 is electrically connected to a PAD (not shown) (see FIG. 29). The gate electrode 307 is short-circuited with the source electrode 308. The source electrode 308 is connected to the ground.

In such an ESD protection element, when a positive voltage surge due to static electricity or the like occurs in the PAD, reverse breakdown occurs in the pn junction region 401 formed by the shallow drain region 303 and the p well region 301. A large electric field strength generated in the pn junction region 401 generates a large number of electron-hole pairs, and these holes are discharged to the ground through the p-well region 301. When the potential of the p well region 301 rises due to the internal resistance of the p well region 301 and exceeds the potential barrier of the pn junction composed of the p well region 301 and the n ⁺⁺ source region 304, the n ⁺⁺ drain region 305 ( An npn bipolar transistor composed of a collector composed of an LDD region, a base composed of a p-well region 301, and an emitter composed of an n ⁺⁺ source region 304 (including an LDD region) operates. A large current flows between the collector and the emitter of the npn bipolar transistor, and a positive voltage surge generated in the PAD is released from the p-well region 301 to the ground.

  When a negative voltage surge occurs in the PAD, the voltage surge is released from the p-channel GGFET constituting the ESD protection element shown in FIG. 29 to the circuit power supply. The operation of the p-channel GGFET is the same as that of the n-channel GGFET.

  As a configuration example of the ESD protection element, for example, the following GGFET has been proposed. FIG. 31 is a plan view showing a configuration example of the ESD protection element. The ESD protection element shown in FIG. 31 has an n-channel GGFET structure. A plurality of drain electrodes 602, gate electrodes 603, and source electrodes 604 are provided on the surface of the active region 605. The drain electrode 602 and the source electrode 604 are alternately provided apart from each other. A gate electrode 603 is provided between the drain electrode 602 and the source electrode 604 so as to be separated from the drain electrode 602 and the source electrode 604. The drain electrodes 602 are electrically connected. Each gate electrode 603 is electrically connected. Each source electrode 604 is electrically connected. In other words, each electrode has a finger portion formed in a comb-like shape, and the finger portions are provided apart from each other in the active region 605. The drain electrode 602 is electrically connected to the PAD 601. The gate electrode 603 is short-circuited to the source electrode 604 (see, for example, Non-Patent Document 2 below).

  Moreover, when producing an ESD protection element, it is necessary to design so that the following design criteria may be satisfied. FIG. 32 is a characteristic diagram showing a breakdown voltage characteristic of the ESD protection element. As shown in FIG. 32, the withstand voltage of the ESD protection element is larger than the operating voltage (signal range + safety margin) expected for the safe operation of the power IC, and the withstand voltage of the gate oxide film of the semiconductor element constituting the internal circuit of the power IC. It is necessary to design the ESD protection element so as to satisfy a range not exceeding (gate oxide film breakdown voltage or the like) (hereinafter referred to as an ESD design window) (for example, see Non-Patent Document 3 below).

  The ESD protection element has a configuration similar to that of a CMOS such as a logic circuit integrated in an internal circuit, and is manufactured on the same substrate, for example. Therefore, when the gate oxide film of a CMOS or high voltage device is thinned, the gate oxide film of the ESD protection element is similarly thinned. When the gate oxide film of the ESD protection element becomes thinner, the breakdown voltage of the gate oxide film of the ESD protection element is reduced. On the other hand, when the LDD structure or the like is applied (see FIG. 30), the breakdown voltage of the ESD protection element increases, becomes higher than the breakdown voltage of the gate oxide film of the ESD protection element, and falls outside the range of the breakdown voltage that satisfies the ESD design window. May end up.

  For example, when the gate oxide film of the ESD protection element is 15 nm, the breakdown voltage of the gate oxide film of the ESD protection element is about 11V. In addition, when the power IC is used as a scan driver IC of a plasma display panel (PDP), for example, the operating voltage margin (safety margin) allowing for the safe operation of the PDP may be 7V. That is, the withstand voltage of the ESD protection element that satisfies the ESD design window is 7 to 11V. On the other hand, the breakdown voltage of the n-channel MOSFET having the LDD structure is 14V or more. That is, the breakdown voltage of the n-channel GGFET having the LDD structure is 14V or more.

In order to avoid the above-described problem, a technique for reducing the breakdown voltage of a GGFET used as an ESD protection element has been proposed. FIG. 33 is a cross-sectional view showing another example of a conventional ESD protection element. In the ESD protection element shown in FIG. 30, a p ⁺ low resistance region 311 having a resistivity lower than that of the p well region 301 is formed in the entire region under the n ⁺⁺ drain region 305 inside the p well region 301. . Other structures are the same as those of the semiconductor element shown in FIG. In the semiconductor element shown in FIG. 33, when a voltage surge occurs in the PAD (see FIG. 29), the pn junction region 402 formed by the n ⁺⁺ drain region 305 and the p ⁺ low resistance region 311 causes reverse breakdown. It becomes an area. The reverse breakdown voltage of the pn junction region 402 is lower than the reverse breakdown voltage of the pn junction region formed by the n ⁺⁺ drain region 305 and the p well region 301, and the breakdown voltage of the semiconductor element is reduced (for example, the following patent document) 1).

As another semiconductor element, the following technique has been proposed. FIG. 34 is a cross-sectional view showing another example of a conventional ESD protection element. A p ⁻ well region 502 is provided in part of the surface layer of the n-type support substrate 501. The p ⁻ well region 502 is separated from an n drift region (not shown) by a first trench 507 and a second trench 510 embedded with an insulator. A gate electrode 511 is provided on a part of the surface of the p ⁻ well region 502 via a gate insulating film 512. A part of the surface layer of the p ⁻ well region 502 is provided with an n ⁺ drain region 505 and an n ⁺ source region 506 that are formed in a self-aligned manner using the gate electrode 511 as a mask. Further, a first p ⁺ semiconductor region 503 and a second p ⁺ semiconductor are formed on part of the surface layer of the p ⁻ well region 502 on the opposite side of the gate electrode 511 of the n ⁺ drain region 505 and the n ⁺ source region 506. Region 504 is formed. The first p ⁺ semiconductor region 503 is separated from the n ⁺ drain region 505 by a third trench 508 embedded with an insulator. The second p ⁺ semiconductor region 504 is separated from the n ⁺ source region 506 by a fourth trench 509 embedded with an insulator. p ^- Inside the well region 502, n ⁺ so as to occupy a part of the region under the drain region 505, p ^- low p semiconductor region 513 having resistivity than the well region 502 is formed. N ⁺ drain region 505 is electrically connected to PAD 514. The first p ⁺ semiconductor region 503, the second p ⁺ semiconductor region 504, the n ⁺ source region 506, and the gate electrode 511 are electrically short-circuited and connected to the ground. In the semiconductor element shown in FIG. 34, the breakdown voltage of the semiconductor element is reduced by forming a pn junction region formed by the n ⁺ drain region 505 and the p low resistance region 513. (For example, refer to Non-Patent Document 4 below.)

JP 2007-005825 A

Y. Taur, T. H. Ning, Fundamentals of Modern VLSI Devices (UK), 1st edition, Cambridge University Press (UK) (University University Press), 1999, p. 168 ESD in Silicon Integrated Circuits (USA), 1st edition, Wiley-I Triple, by E. Ajith Amerasekera, C. Duvvury.・ E-press (Wiley-IEEE Press), 1995, p. 66-68 Advanced simulation methods for ESD protection by K. Esmark, J. Gosner, and W. Stadler, Advanced simulation methods for ESD ), First edition, Elsevier Ltd., 2003, p. 35 K. Chatty, 5 others, Process and Design Optimization of a Protection Scheme Based on NMOSFETs with ESD Implant in 65nm and 45nm CMOS Technologies 65nm and 45nm CMOS Technologies), (USA), 29th Electrical Overstress / Electrostatic Discharge Symposium Proc. (Proc. EOS / ESD Symposium: 29th) lectrical Overstress / Electrostatic Discharge Symposium Proceedings), 2007 years, p. 7A. 2-1-p. 7A. 2-10

However, in the techniques of Patent Document 1 and Non-Patent Document 4 described above, the p-type low resistance region (for example, the p ⁺ low resistance region in FIG. 33) of the ESD protection element in the manufacturing process of the entire circuit in which the ESD protection element is integrated. Therefore, it is necessary to add an ion implantation process only for forming the. For this reason, the number of manufacturing steps for the entire circuit increases, and the manufacturing cost increases.

  An object of the present invention is to provide a semiconductor element that has a breakdown voltage that satisfies an ESD design window and can be used as an ESD protection element in order to solve the above-described problems caused by the related art. Another object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce the manufacturing cost of the entire circuit in which the ESD protection device is integrated.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to the invention of claim 1 has the following characteristics. A second conductivity type source region provided in a part of the first conductivity type first well region; a second conductivity type drain region provided in a part of the first well region; and the source region; A first gate insulating film provided on a surface of the first well region between the drain regions; a first gate electrode provided on the first gate insulating film; and one of the first well regions A first conductivity type first low resistance region having a resistivity lower than that of the first well region provided in the source region, the region below the source region, and the region below the first gate insulating film; And a source electrode that is in contact with the source region and is short-circuited to the first gate electrode, and a drain electrode that is in contact with the drain region.

  According to a second aspect of the present invention, there is provided a semiconductor device according to the first aspect, further comprising a first conductivity type second semiconductor region provided on the surface of the support substrate via an insulating layer. The first well region is provided in a part of the first semiconductor region. A part of the first well region is provided with a first conductivity type first contact region having a lower resistivity than the first well region and electrically connected to the source region. A portion of the first semiconductor region is provided with a second conductivity type second contact region having a resistivity lower than that of the first semiconductor region, apart from the first well region. The first gate electrode is further short-circuited to a contact electrode in contact with the second contact region.

  According to a third aspect of the present invention, there is provided a semiconductor device according to the first aspect, further comprising a first semiconductor region of a second conductivity type provided on the surface of the support substrate. The first well region is provided in a part of the first semiconductor region. A part of the first well region is provided with a first conductivity type first contact region having a lower resistivity than the first well region and electrically connected to the source region. A portion of the first semiconductor region is provided with a second conductivity type second contact region having a resistivity lower than that of the first semiconductor region, apart from the first well region. The first gate electrode is further short-circuited to a contact electrode in contact with the second contact region.

  According to a fourth aspect of the present invention, there is provided a semiconductor element according to the first aspect of the present invention, further comprising a second semiconductor region of the first conductivity type provided on the surface of the support substrate. The first well region is provided in a part of the second semiconductor region. A part of the first well region is provided with a first conductivity type first contact region having a lower resistivity than the first well region and electrically connected to the source region.

  According to a fifth aspect of the present invention, there is provided a semiconductor device according to the first aspect, further comprising a first conductivity type support substrate. The first well region is provided in a part of the surface layer of the first conductivity type support substrate. A part of the first well region is provided with a first conductivity type first contact region having a lower resistivity than the first well region and electrically connected to the source region.

  A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to any one of the first to fifth aspects, wherein the source region is in contact with a part of the first well region. A second conductivity type third semiconductor region provided shallower than the drain region and a second conductivity type third semiconductor region provided shallower than the drain region so as to be in contact with the drain region at a part of the first well region. 4 semiconductor regions. The first low-resistance region is further provided in the third semiconductor region and a region below it, the fourth semiconductor region and a region below it, and a part of the drain region and a region below it.

  According to a seventh aspect of the present invention, there is provided the semiconductor element according to any one of the first to sixth aspects, wherein the first gate electrode is formed from an end of the first low resistance region on the drain region side. The distance to the end on the drain region side is in the range of 0 μm to 0.3 μm.

  The semiconductor device according to the invention of claim 8 has the following characteristics. 8. A semiconductor device in which the semiconductor element according to claim 1 (hereinafter referred to as a first semiconductor element) and a second semiconductor element are formed on the same wafer. In this semiconductor device, the first semiconductor element and the second semiconductor element are electrically separated by a trench embedded with an insulator formed deeper than the first well region of the first semiconductor element. Yes.

  The semiconductor device according to claim 9 has the following characteristics. 8. A semiconductor device in which the semiconductor element according to claim 1 (hereinafter referred to as a first semiconductor element) and a second semiconductor element are formed on the same wafer. In this semiconductor device, the first semiconductor element and the second semiconductor element are electrically separated by a diffusion region of a first conductivity type formed deeper than the first well region of the first semiconductor element. Yes.

  A method for manufacturing a semiconductor element according to the invention of claim 10 has the following characteristics. A method of manufacturing a semiconductor device, wherein the semiconductor device according to claim 1 (hereinafter referred to as a first semiconductor device) and a second semiconductor device are formed on the same wafer. It includes the process shown. A first conductivity type first low resistance region having a resistivity lower than that of the first well region is formed in the first conductivity type first well region formed on the wafer and formed on the wafer. A low resistance region forming step of forming a first conductivity type second low resistance region having a lower resistivity than the second well region is performed in the first conductivity type second well region. A gate insulating film, a gate electrode, a source region and a drain region of the first semiconductor element are formed in the first well region and the first low resistance region, and in the second well region and the second low resistance region. Then, a first element forming step of forming a gate insulating film, a gate electrode, and a second conductivity type fifth semiconductor region of the second semiconductor element is performed. A second element forming step of forming a first conductive type or a second conductive type sixth semiconductor region in the second conductive type first semiconductor region provided with the second well region apart from the second well region; I do.

  According to the eleventh aspect of the present invention, there is provided a semiconductor device manufacturing method according to the tenth aspect of the present invention, wherein in the low resistance region forming step, boron ions are ion-implanted at an acceleration voltage of 100 keV or more and 250 keV or less. Thus, the first low resistance region and the second low resistance region are formed.

According to a twelfth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the tenth or eleventh aspect, wherein in the low resistance region forming step, boron ions are used in an amount of 1 × 10 ¹³ cm ⁻² or more. The first low resistance region and the second low resistance region are formed by performing ion implantation with a dose of 5 × 10 ¹³ cm ⁻² or less.

  According to a thirteenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to any one of the tenth to twelfth aspects, further comprising the following steps. Before the step of forming the gate insulating film of the first semiconductor element and the gate insulating film of the second semiconductor element in the first element forming step, the temperature is 900 ° C. or higher and 950 ° C. or lower in a nitrogen atmosphere. An annealing process is performed for a minute or less to control the diffusion of the low resistance region and to recover the disorder of the crystal lattice generated in the low resistance region forming step.

  According to the above-described invention, the first low resistance region is formed by simultaneously forming the first low resistance region formed in the ESD protection element and the second low resistance region formed in the high breakdown voltage device. The first low resistance region can be formed in the ESD protection element without adding only the ion implantation step. In addition, by forming the first low resistance region in the ESD protection element, the breakdown voltage of the ESD protection element can be reduced in substantially the same manner as the conventional ESD protection element (see FIG. 33) in which the low resistance region is formed. . As a result, an ESD protection element having a withstand voltage that satisfies the ESD design window can be obtained. Accordingly, the manufacturing cost of the entire circuit in which the ESD protection element is integrated can be reduced. Further, the second well region including the low resistance region is formed so that the impurity concentration at the interface with the gate insulating film is lower than the impurity concentration in the region away from the interface with the gate insulating film in the depth direction. Can do. Further, the second well region including the low resistance region can be formed so as to separate the position where the impurity concentration becomes maximum at the interface with the gate insulating film into two locations. As a result, the low resistance region can be formed in the well region while maintaining the threshold voltage of the element substantially.

  According to the semiconductor element, the semiconductor device, and the semiconductor element manufacturing method of the present invention, there is an effect that the breakdown voltage of the ESD protection element can be reduced. In addition, an ESD protection element having a withstand voltage that satisfies the ESD design window can be produced. In addition, the manufacturing cost of the entire circuit in which the ESD protection element is integrated can be reduced.

It is sectional drawing which shows the ESD protection element concerning embodiment. It is sectional drawing which shows the modification of the ESD protection element concerning embodiment. It is a top view which shows the structural example of the ESD protection element concerning embodiment. It is sectional drawing which shows the high voltage | pressure-resistant device concerning embodiment. It is sectional drawing which shows an example of the semiconductor device concerning embodiment. It is sectional drawing which shows an example of the semiconductor device concerning embodiment. It is sectional drawing which shows an example of the semiconductor device concerning embodiment. It is sectional drawing which shows an example of the semiconductor device concerning embodiment. It is sectional drawing which shows an example of the semiconductor device concerning embodiment. It is sectional drawing which shows an example of the semiconductor device concerning embodiment. It is sectional drawing which shows an example of the semiconductor device concerning embodiment. It is sectional drawing which shows an example of the semiconductor device concerning embodiment. It is sectional drawing which shows an example of the semiconductor device concerning embodiment. It is explanatory drawing which shows the manufacturing method of the semiconductor device concerning embodiment sequentially. It is explanatory drawing which shows the manufacturing method of the semiconductor device concerning embodiment sequentially. It is explanatory drawing which shows the manufacturing method of the semiconductor device concerning embodiment sequentially. It is explanatory drawing which shows the manufacturing method of the semiconductor device concerning embodiment sequentially. It is explanatory drawing which shows the manufacturing method of the semiconductor device concerning embodiment sequentially. It is explanatory drawing which shows the manufacturing method of the semiconductor device concerning embodiment sequentially. It is explanatory drawing which shows the manufacturing method of the semiconductor device concerning embodiment sequentially. It is explanatory drawing which shows the manufacturing method of the semiconductor device concerning embodiment sequentially. It is explanatory drawing which shows the manufacturing method of the semiconductor device concerning embodiment sequentially. It is explanatory drawing which shows the manufacturing method of the semiconductor device concerning embodiment sequentially. It is explanatory drawing which shows the manufacturing method of the semiconductor device concerning embodiment sequentially. FIG. 2 is a diagram showing an impurity concentration of a low resistance region at an interface (arrow I) between the gate insulating film and the well region of FIG. It is a characteristic view which shows the pressure | voltage resistant characteristic of the gate oxide film in the ESD protection element concerning embodiment, and the conventional ESD protection element. It is a characteristic view which shows the breakdown voltage of an element with respect to extension distance LBP1. It is a characteristic view which shows the pressure | voltage resistant characteristic of the ESD protection element concerning embodiment. It is a circuit diagram which shows an example of an ESD protection element. It is sectional drawing which shows the conventional ESD protection element. It is a top view which shows the structural example of an ESD protection element. It is a characteristic view which shows the pressure | voltage resistant characteristic of an ESD protection element. It is sectional drawing which shows another example of the conventional ESD protection element. It is sectional drawing which shows another example of the conventional ESD protection element.

  Exemplary embodiments of a semiconductor element, a semiconductor device, and a method for manufacturing the semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

FIG. 1 is a cross-sectional view illustrating an ESD protection element according to an embodiment. The ESD protection element 100 shown in FIG. 1 is manufactured using an SOI substrate. The SOI substrate has a structure in which an insulating layer 2 made of an oxide film or the like and an n ⁻ semiconductor region 3 are stacked in this order on a p ⁻ support substrate 1. The n ⁻ semiconductor region 3 and the p ⁻ support substrate 1 are insulated by the insulating layer 2. The n ⁻ semiconductor region 3 corresponds to a first semiconductor region.

The first p well region 4 is provided in a part of the surface layer of the n ⁻ semiconductor region 3. The n ⁺⁺ source region 8 is provided in a part of the surface layer of the first p well region 4. The n ⁺⁺ source region 8 has a lower resistivity than the n ⁻ semiconductor region 3. The first p ⁺⁺ contact region 5 is provided in part of the surface layer of the first p well region 4 so as to be in contact with the n ⁺⁺ source region 8. The first p ⁺⁺ contact region 5 has a lower resistivity than the first p well region 4. The first p well region 4 corresponds to the first well region. The first p ⁺⁺ contact region 5 corresponds to the first contact region.

The n ⁺⁺ drain region 9 is provided in a part of the surface layer of the first p well region 4 apart from the n ⁺⁺ source region 8. The n ⁺⁺ drain region 9 has a lower resistivity than the n ⁻ semiconductor region 3. Between the n ⁺⁺ source region 8 and the n ⁺⁺ drain region 9, an n-type first LDD (shallow source) region 6 and an n-type second LDD (shallow) are formed in part of the surface layer of the first p well region 4. Drain) regions 7 are provided apart from each other. The first LDD region 6 is in contact with the n ⁺⁺ source region 8. The first LDD region 6 is formed shallower than the n ⁺⁺ source region 8. Second LDD region 7 is in contact with n ⁺⁺ drain region 9. Second LDD region 7 is formed shallower than n ⁺⁺ drain region 9. The first LDD region 6 corresponds to a third semiconductor region. The second LDD region 7 corresponds to a fourth semiconductor region.

The n ⁺⁺ contact region 10 is provided apart from the first p well region 4 in a part of the surface layer of the n ⁻ semiconductor region 3. The n ⁺⁺ contact region 10 has a lower resistivity than the n ⁻ semiconductor region 3. The n ⁺⁺ contact region 10 corresponds to the second contact region.

A first local oxide film 11 is laminated on a part of the first p ⁺⁺ contact region 5, the surface of the first p well region 4, the surface of the n ⁻ semiconductor region 3, and a part of the n ⁺⁺ contact region 10. The first local oxide film 11 separates the n ⁺⁺ contact region 10 and the first p well region 4. A first gate insulating film 12 is provided on the surfaces of the first LDD region 6, the first p well region 4 and the second LDD region 7. The first gate electrode 13 is provided on the first gate insulating film 12. A first gate sidewall spacer 14 formed of a nitride film or an oxide film is provided on the side surface of the first gate electrode 13. Unless otherwise specified, the end portion of the first gate electrode 13 indicates an interface between the first gate electrode 13 and the first gate sidewall spacer 14.

The source electrode 15, the n ⁺⁺ source region 8 provided in contact with the surface of the first 1p ⁺⁺ contact region 5, and short-circuiting the n ⁺⁺ source region 8 and the 1p ⁺⁺ contact regions 5. The drain electrode 16 is provided in contact with the surface of the n ⁺⁺ drain region 9. For example, the drain electrode 16 is connected to a PAD (see FIG. 29) not shown. Contact electrode 17 is provided in contact with the surface of n ⁺⁺ contact region 10. The first gate electrode 13 is short-circuited to the source electrode 15 and the contact electrode 17.

The first p ⁺ low resistance region 41 includes a first p ⁺⁺ contact region 5 and a region below it, an n ⁺⁺ source region 8 and a region below it, a first LDD region 6 and a part thereof. It is provided in a lower region, a region below the first gate insulating film 12, a second LDD region 7 and a region below the second LDD region 7, and a part of the n ⁺⁺ drain region 9 and a region below it. The end of the n ⁺⁺ drain region 9 of the first p ⁺ low resistance region 41 reaches a part of the interface between the first gate insulating film 12 and the first p well region 4. The first p ⁺ low resistance region 41 has a lower resistivity than the first p well region 4. The first extension distance (hereinafter referred to as LBP1) from the end of the first p ⁺ low resistance region 41 on the n ⁺⁺ drain region 9 side to the end of the first gate electrode 13 on the n ⁺⁺ drain region 9 side is In the range of 0 to 0.3 μm. The reason will be described later. The first p ⁺ low resistance region 41 corresponds to the first low resistance region. Thus, the ESD protection element 100 has an n-channel GGFET structure. The ESD protection element 100 corresponds to a first semiconductor element.

The first LDD region 6 and the second LDD region 7 are low-concentration impurity doped regions provided in the channel region. The first LDD region 6 and the second LDD region 7 are shallowly joined to the n ⁺⁺ source region 8 and the n ⁺⁺ drain region 9, respectively, so that the electric field strength at the gate electrode end of the drain region can be reduced.

Further, by providing the first p ⁺ low resistance region 41, when ESD occurs, the reverse occurs in the pn junction region 51 formed by the first p ⁺ low resistance region 41, the second LDD region 7, and the n ⁺⁺ drain region 9. Yield occurs. Thereby, the breakdown voltage of the ESD protection element 100 can be reduced in substantially the same manner as the conventional ESD protection element (see FIG. 33) provided with the low resistance region. The reason will be described later. Further, by providing the first 1p ⁺ low resistance region 41, a collector made of n ⁺⁺ drain region 9 (including an LDD region), the base consisting of the 1p ⁺ low resistance region 41, n ⁺⁺ source region 8 (LDD region An npn bipolar transistor composed of an emitter made of In the conventional ESD protection element, the base of the npn bipolar transistor is constituted by a p-well region. Therefore, in the ESD protection element 100, the impurity concentration of the base of the npn bipolar transistor can be made higher than that of the conventional ESD protection element. Thereby, the latch-up tolerance of the ESD protection element 100 can be improved.

Further, by providing the n ⁺⁺ contact region 10 in contact with the n ⁻ semiconductor region 3, when ESD occurs and the current flowing in the element increases, the n ⁻ semiconductor region 3 and the first p well region 4 It can be reduced that the pn junction to be formed is partially forward biased.

Note that the ESD protection element 100 described above is formed using an SOI substrate having a p-type support substrate, but is not limited thereto and can be variously changed. FIG. 2 is a cross-sectional view illustrating a modified example of the ESD protection element according to the embodiment. As shown in FIG. 2, the ESD protection element 101 may be manufactured using, for example, a bulk substrate in which an n well region is formed as an n ⁻ semiconductor region 3 on a p ⁻ support substrate 1. Other configurations of the ESD protection element 101 are the same as those of the ESD protection element 100. Alternatively, an epitaxial substrate obtained by epitaxially growing the n ⁻ semiconductor region 3 on the surface of the p ⁻ support substrate 1 may be used. Alternatively, an SOI substrate having an n-type support substrate may be used. Alternatively, the first p well region 4 may be provided on the surface layer of the p ⁻ epitaxial layer by using an epitaxial substrate obtained by p ⁻ epitaxial growth on the surface of the p ⁺ support substrate 1. Further, the first p well region 4 may be provided in the surface layer of the p ⁻ support substrate 1. The first 1p well region 4, for example p ^- in the case of forming the p-type region such as epitaxial layer, since the region formed by the first 1p well region 4 and the p-type region is not a pn junction, n ⁺⁺ contact regions 10 may not be provided.

  Further, the ESD protection element 100 may have a comb-like GGFET structure. FIG. 3 is a plan view illustrating a configuration example of the ESD protection element according to the embodiment. The ESD protection element shown in FIG. 3 has an n-channel GGFET structure. In the surface layer of the active region 86, a plurality of low resistance regions 85 are provided apart from each other. A gate electrode 83 and a source electrode 84 are provided on the surface of each low resistance region 85. A drain electrode 82 is provided on each surface of the active region 86 exposed between adjacent low resistance regions 85. The source electrodes 84 provided in the active region 86 are electrically connected to each other. The gate electrodes 83 provided in the active region 86 are electrically connected. The drain electrodes 82 provided in the low resistance region 85 are electrically connected to each other. That is, each electrode has a finger portion formed in a comb shape, and the finger portion is provided in the active region 86 and the low resistance region 85. The drain electrode 82 is electrically connected to the PAD 81. The gate electrode 83 is short-circuited to the source electrode 84.

FIG. 4 is a cross-sectional view of the high voltage device according to the embodiment. The high voltage device 110 shown in FIG. 4 is manufactured using an SOI substrate. Second p well region 21 is provided in part of the surface layer of n ⁻ semiconductor region 3. The n ⁻ semiconductor region 3 functions as a drift region of the high breakdown voltage device 110. The n ⁺⁺ emitter region 23 is provided in a part of the surface layer of the second p well region 21. The n ⁺⁺ emitter region 23 has a lower resistivity than the n ⁻ semiconductor region 3. A third LDD (shallow emitter) region 22 is provided at the end of the n ⁺⁺ emitter region 23. Third LDD region 22 is formed shallower than n ⁺⁺ emitter region 23. The second p ⁺⁺ contact region 24 is provided in part of the surface layer of the second p well region 21 so as to be in contact with the n ⁺⁺ emitter region 23. The second p ⁺⁺ contact region 24 has a lower resistivity than the second p well region 21. Further, for example, a part of the second p ⁺⁺ contact region 24 may occupy a part of the lower side of the n ⁺⁺ emitter region 23. The n ⁺⁺ emitter region 23 corresponds to the fifth semiconductor region. The second p well region 21 corresponds to a second well region.

The n buffer region 25 is provided in a part of the surface layer of the n ⁻ semiconductor region 3 so as to be separated from the second p well region 21. The n buffer region 25 has a lower resistivity than the n ⁻ semiconductor region 3. The p ⁺⁺ collector region 26 is provided in a part of the surface layer of the n buffer region 25. The p ⁺⁺ collector region 26 has a lower resistivity than the second p well region 21. The p ⁺⁺ collector region 26 corresponds to a sixth semiconductor region.

A second local oxide film 27 is stacked on part of the p ⁺⁺ collector region 26, the n buffer region 25, and the surface of the n ⁻ semiconductor region 3. A second gate insulating film 28 in contact with the second local oxide film 27 is provided on a part of the n ⁺⁺ emitter region 23, the second p well region 21 and the surface of the n ⁻ semiconductor region 3. The second gate electrode 29 is provided so as to straddle part of the second local oxide film 27 and the second gate insulating film 28. A side wall of the second gate electrode 29 is provided with a second gate sidewall spacer 30 formed of a nitride film or an oxide film. Unless otherwise specified, the end portion of the second gate electrode 29 indicates the interface between the second gate electrode 29 and the second gate sidewall spacer 30. The emitter electrode 31 has a n ⁺⁺ emitter region 23 is provided in contact with the surface of the first 2p ⁺⁺ contact regions 24, short-circuited with n ⁺⁺ emitter region 23 and a second 2p ⁺⁺ contact regions 24 Yes. The collector electrode 32 is provided in contact with the surface of the p ⁺⁺ collector region 26.

The second p ⁺ low resistance region 42 is provided in a part of the second p well region 21 and does not reach the interface between the second gate insulating film 28 and the second p well region 21. The second p ⁺ low resistance region 42 has a lower resistivity than the second p well region 21. The width of the second p ⁺ low resistance region 42 provided in the region below the second gate electrode 29 is defined as a second extension distance (hereinafter referred to as LBP2). The second p ⁺ low resistance region 42 corresponds to a second low resistance region. Thus, the high voltage device 110 of the embodiment has a lateral IGBT structure. The high withstand voltage device 110 corresponds to a second semiconductor element.

Instead of the p ⁺⁺ collector region 26, an n-type semiconductor region (drain region) having a lower resistivity than the n buffer region 25 may be provided to form a MOSFET structure. Further, similarly to the ESD protection element, an SOI substrate, an epitaxial substrate, a bulk substrate, or the like having different conductivity types may be used.

The ESD protection element 100 (see FIG. 1) and the high breakdown voltage device 110 (see FIG. 4) described above are manufactured on the same substrate, for example. 5 to 13 are cross-sectional views illustrating an example of the semiconductor device according to the embodiment. The semiconductor device shown in FIG. 5 is manufactured using an SOI substrate in which an insulating layer 2 and an n ⁻ semiconductor region 3 are stacked in this order on a p ⁻ support substrate 1. The n ⁻ semiconductor region 3 is provided with a region for manufacturing an ESD protection element (hereinafter referred to as an ESD protection element region) 120 and a region for manufacturing a high breakdown voltage device (hereinafter referred to as a high breakdown voltage device region) 130. Yes. In the n ⁻ semiconductor region 3, the ESD protection element region 120 and the high breakdown voltage device region 130 are separated by a trench 91 (hereinafter referred to as an isolation trench) that reaches the insulating layer 2 and is filled with an insulator such as an oxide film. ing. The n ⁻ semiconductor region 3 of the high breakdown voltage device region 130 functions as a drift region of the high breakdown voltage device.

In the ESD protection element region 120, the first p well region 4 is provided in the surface layer of the n ⁻ semiconductor region 3, and an ESD protection element (not shown) is manufactured. Further, in the ESD protection element region 120, an n ⁺⁺ contact region 10, a first local oxide film 11, and a contact electrode 17 are further provided. The surface structure of the ESD protection element is the same as that of the ESD protection element shown in FIG. 1 (hereinafter the same in FIGS. 6 to 13). In the high breakdown voltage device region 130, a high breakdown voltage device (not shown) is formed on the surface layer of the n ⁻ semiconductor region 3. The surface structure of the high withstand voltage device is the same as that of the high withstand voltage device shown in FIG. 4 (hereinafter the same in FIGS. 6 to 13). A third local oxide film 92 in contact with isolation trench 91 is provided on n ⁻ semiconductor region 3. The isolation trench 91 and the third local oxide film 92 (hereinafter referred to as an isolation region) prevent the ESD protection element and the high breakdown voltage device from being electrically influenced by each other.

As another example, the ESD protection element and the high breakdown voltage device may be directly formed on the surface layer of the p-type bulk substrate. In the semiconductor device shown in FIG. 6, an ESD protection element region 120 and a high breakdown voltage device region 130 are provided on a p ⁻ support substrate 1 that is a p-type bulk substrate. In the ESD protection element region 120, the first p-well region 4 is provided in the surface layer of the p ⁻ support substrate 1, and an ESD protection element (not shown) is manufactured. The high voltage device region 130, n ^- well region is provided ^- n as the semiconductor region 3. A high breakdown voltage device (not shown) is fabricated in the n ⁻ well region. Isolation trench 91 is formed in p ⁻ support substrate 1 deeper than first p well region 4 and n ⁻ semiconductor region 3. A third local oxide film 92 in contact with the isolation trench 91 is provided on the p ⁻ support substrate 1. In the semiconductor device illustrated in FIG. 6, the n ⁺⁺ contact region 10 and the like are not necessarily provided. Other structures are the same as those of the semiconductor device shown in FIG.

  As another example, a region (hereinafter referred to as a polysilicon region) made of, for example, polysilicon (Poly-Silicon) may be provided inside the isolation trench 91. In the semiconductor device shown in FIG. 7, a polysilicon region 93 is provided inside the isolation trench 91 via an insulator. Other structures are similar to those of the semiconductor device shown in FIG. Providing the polysilicon region 93 leads to improvement of the embedding property of the isolation trench 91 and reduction of substrate warpage.

As another example, a p-type diffusion region may be provided instead of the isolation trench 91. In the semiconductor device shown in FIG. 8, the ESD protection element region 120 and the high breakdown voltage device region 130 are separated by the p ⁺ diffusion region 94. P ⁺ diffusion region 94 is formed deeper than first p well region 4 and n ⁻ semiconductor region 3. In part of the surface layer of the p ⁺ diffusion region 94, a p ⁺⁺ high concentration diffusion region 95 is provided. Third local oxide film 92, the ESD protection element region 120 side of the p ⁺⁺ high concentration diffusion region 95, p ⁺⁺ high concentration diffusion region 95, p ⁺ diffusion region 94, p ^- the support substrate 1 and the second 1p well region 4 is provided across the surface of 4. In the high voltage device region 130 side of the p ⁺⁺ high concentration diffusion region 95, p ⁺⁺ high concentration diffusion region 95, p ⁺ diffusion region 94, p ^- the support substrate 1 and the n ^- across the surface of the semiconductor region 3 Is provided. The p ⁺ diffusion region 94, the p ⁺⁺ high concentration diffusion region 95, and the third local oxide film 92 are isolation regions. Other structures are similar to those of the semiconductor device shown in FIG. The p ⁺⁺ high concentration diffusion region 95 is connected to the ground.

As another example, the ESD protection element and the high breakdown voltage device may be manufactured using an epitaxial substrate obtained by growing an n-type epitaxial layer on the p ⁻ support substrate 1. In the semiconductor device shown in FIG. 9, an n-type epitaxial layer to be the n ⁻ semiconductor region 3 is provided on the p ⁻ support substrate 1. The isolation trench 91 is provided in this n-type epitaxial layer so as to reach the p ⁻ support substrate 1. Other structures are the same as those of the semiconductor device shown in FIG.

  As another example, a polysilicon region may be provided inside the isolation trench 91 of the semiconductor device shown in FIG. In the semiconductor device shown in FIG. 10, the configuration other than the isolation trench is the same as that of the semiconductor device shown in FIG. The effect of providing the polysilicon region 93 is the same as that of the semiconductor device shown in FIG.

As another example, a p-type diffusion region may be provided instead of the isolation trench 91 of the semiconductor device shown in FIG. In the semiconductor device shown in FIG. 11, the ESD protection element region 120 and the high breakdown voltage device region 130 are separated by the p ⁺ diffusion region 94. The p ⁺ diffusion region 94 is provided in the n ⁻ semiconductor region 3 so as to reach the p ⁻ support substrate 1. In part of the surface layer of the p ⁺ diffusion region 94, a p ⁺⁺ high concentration diffusion region 95 is provided. Third local oxide film 92 is provided across the surfaces of n ⁻ semiconductor region 3, p ⁺ diffusion region 94, and p ⁺⁺ high concentration diffusion region 95. Other structures are the same as those of the semiconductor device shown in FIG. The p ⁺ diffusion region 94 and the p ⁺⁺ high concentration diffusion region 95 are the same as those of the semiconductor device shown in FIG.

As another example, the ESD protection element and the high breakdown voltage device may be manufactured using an epitaxial substrate obtained by growing a p-type epitaxial layer on a support substrate. In the semiconductor device shown in FIG. 12, the p ⁻ epitaxial layer 97 is provided on the surface of the p ⁺ support substrate 96. In the p ⁻ epitaxial layer 97, an ESD protection element region 120 and a high breakdown voltage device region 130 are provided. In the ESD protection element region 120, the first p-well region 4 is provided in the p ⁻ epitaxial layer 97, and an ESD protection element not shown is produced. In the high voltage device region 130, p ^- the part of the surface layer of the epitaxial layer 97, n ^- well region is provided ^- n as the semiconductor region 3. A high breakdown voltage device (not shown) is fabricated in the n ⁻ well region. The isolation trench 91 is provided in the p ⁻ epitaxial layer 97 so as to reach the p ⁺ support substrate 96. Other structures are similar to those of the semiconductor device shown in FIG. The p ⁻ epitaxial layer 97 corresponds to the second semiconductor region.

  As another example, a polysilicon region may be provided inside the isolation trench 91 of the semiconductor device shown in FIG. In the semiconductor device shown in FIG. 13, the configuration other than the isolation trench is the same as that of the semiconductor device shown in FIG. The effect of providing the polysilicon region 93 is the same as that of the semiconductor device shown in FIG.

Next, a method for manufacturing the semiconductor device according to the embodiment will be described using the semiconductor device shown in FIG. 5 as an example. FIG. 14 to FIG. 24 are explanatory views sequentially showing the method for manufacturing the semiconductor device according to the embodiment. 14 to 24, the ESD protection element 100 and the high breakdown voltage device 110 are diagrams showing a method for manufacturing a semiconductor device, and do not show the arrangement on the substrate. The arrangement of the ESD protection element 100 and the high breakdown voltage device 110 can be variously changed depending on the semiconductor device to be manufactured. The ESD protection element 100 and the high breakdown voltage device 110 are simultaneously manufactured, for example, on the same substrate. First, as shown in FIG. 14, a first screen oxide film 61 having a thickness of 35 nm, for example, is deposited or grown on the entire surface of the wafer. Then, a first resist pattern 62 is formed by opening the formation region of the first p-well region 4 in a region (ESD protection device region) for manufacturing the ESD protection device 100 by photolithography. Using the first resist pattern 62 as a mask, boron (boron) ions, for example, are implanted at an acceleration voltage of 150 keV, for example, at a dose of 2 × 10 ¹³ cm ⁻² . Next, after removing the first resist pattern 62, the wafer is cleaned. In this manner, for example, boron ions are implanted into the formation region of the first p well region 4 in the ESD protection element region. At this time, the region for manufacturing the high breakdown voltage device 110 (high breakdown voltage device region) is covered with a photoresist. Therefore, for example, boron ions are not implanted into the high breakdown voltage device region.

Next, as shown in FIG. 15, a second resist pattern 63 is formed by opening the formation region of the n buffer region 25 in the high breakdown voltage device region by photolithography. Using the second resist pattern 63 as a mask, for example, phosphorus ions are implanted at a dose of 7.5 × 10 ^{12 to} 1.5 × 10 ¹³ cm ⁻² at an acceleration voltage of, for example, 100 keV to 150 keV. Next, after removing the second resist pattern 63, the wafer is cleaned. In this manner, for example, phosphorus ions are implanted into the formation region of the n buffer region 25 in the high breakdown voltage device region. At this time, the ESD protection element region is covered with a photoresist. Therefore, for example, phosphorus ions are not implanted into the ESD protection element region.

Next, as shown in FIG. 16, a third resist pattern 64 is formed by opening the formation region of the second p-well region 21 in the high breakdown voltage device region by photolithography. Using the third resist pattern 64 as a mask, for example, boron ions are implanted at a dose of 5 × 10 ^{13 to} 7 × 10 ¹³ cm ⁻² at an acceleration voltage of 50 keV, for example. Next, after removing the third resist pattern 64, the wafer is cleaned. In this way, for example, boron ions are implanted into the formation region of the second p well region 21. At this time, the ESD protection element region is covered with a photoresist. Therefore, for example, boron ions are not implanted into the ESD protection element region.

  Next, as shown in FIG. 17, for example, heat treatment is performed in a nitrogen atmosphere, and the implanted impurities are thermally diffused and activated. As a result, the first p well region 4 is formed in the ESD protection element region, and the second p well region 21 and the n buffer region 25 are formed in the high breakdown voltage device region. Then, after removing the first screen oxide film on the wafer surface and forming a buffer oxide film 65 having a thickness of, for example, 35 nm on the entire surface of the wafer, the silicon nitride film 66 having a thickness of, for example, 70 to 200 nm. Is deposited by LPCVD (Low Pressure Chemical Vapor Deposition). Openings are formed in the silicon nitride film 66 and the buffer oxide film 65 by photolithography, and then the wafer is washed after removing the photoresist.

Next, as shown in FIG. 18, thermal oxidation is performed to form a local oxide film (LOCOS oxide film) in the opening of the silicon nitride film. A first local oxide film 11 is formed in the ESD protection element region. A second local oxide film 27 is formed in the high breakdown voltage device region. Then, the buffer oxide film and nitride film on the wafer surface are removed. Thereafter, a second screen oxide film 67 having a thickness of 35 nm, for example, is deposited or grown on the entire surface of the wafer. Then, a third resist pattern 68 having a thickness of 1.0 to 2.0 μm, for example, is formed by photolithography. In the third resist pattern 68, the formation region of the first p ⁺ low resistance region 41 is opened in the ESD protection element region. In the high breakdown voltage device region, the formation region of the second p ⁺ low resistance region 42 is opened. The angle α of the end portion of the third resist pattern 68 is, for example, 80 to 90 °.

Here, in the ESD protection element region, when the first gate electrode is formed later from the end of the third resist pattern 68 on the first local oxide film 11 side, it is provided in a region below the first gate electrode. The width to the end of the first p ⁺ low resistance region is LBP1. The opening of the third resist pattern 68 has an LBP1 of 0.1 μm to 0.4 μm, preferably 0 μm to 0.3 μm. Further, in the high breakdown voltage device region, a second p ⁺ low resistance region provided in a region below the second gate electrode when the second gate electrode is formed later from the end of the third resist pattern 68 on the emitter side. Let LBP2 be the width up to the end of. The opening of the third resist pattern 68 is set so that LBP2 is 0.8 μm or more. Next, for example, boron ions with a accelerating voltage of 100 to 250 keV, for example, a dose amount of 1 × 10 ¹³ cm ⁻² or more and 7.5 × 10 ¹³ cm ⁻² or less, preferably 2.5 × 10 ¹³ or more and 5 × 10 ¹³ or less. Inject with a dose of cm ⁻² or less. Next, after removing the third resist pattern 68, the wafer is cleaned.

Then, the wafer is annealed, for example, at a temperature of 900 to 950 ° C. in a nitrogen atmosphere for 30 minutes to minimize diffusion of boron implanted in FIG. 18 and recover crystal defects caused by ion implantation. Thus, as shown in FIG. 19, with the 1p ⁺ low resistance region 41 is formed in the ESD protection element region, the 2p ⁺ low resistance region 42 is formed in the high voltage device region. Further, ions for adjusting the threshold voltage of the device are implanted into the entire surface of the wafer. Then, the second screen oxide film is removed to form a thermal oxide film or a composite film of an oxide film and a nitride film having a thickness of 14 to 21 nm, for example. The thermal oxide film or the composite film of the oxide film and the nitride film becomes the first gate insulating film 12 in the ESD protection element region, and becomes the second gate insulating film 28 in the high breakdown voltage device region.

  Next, as shown in FIG. 20, polysilicon having a thickness of, for example, 0.2 to 0.4 μm is deposited on the entire surface of the wafer. Then, the first gate electrode 13 is formed in the ESD protection element region by photolithography and anisotropic etching, and the second gate electrode 29 is formed in the high breakdown voltage device region. Further, a fourth resist pattern 69 is formed by photolithography. In the fourth resist pattern 69, the formation region of the first LDD (shallow source) region 6 and the second LDD (shallow drain) region 7 is opened in the ESD protection element region. In the high breakdown voltage device region, the formation region of the third LDD (shallow emitter) region 22 is opened. Using this fourth resist pattern 69 as a mask, for example, phosphorus ions are implanted to form shallowly doped first LDD region 6 and second LDD region 7 in the ESD protection element region, as shown in FIG. In addition, the shallowly doped third LDD region 22 is formed in the high breakdown voltage device region. The first LDD region 6 and the second LDD region 7 are formed in a self-aligned manner using the first gate electrode 13 as a mask. The third LDD region 22 is formed in a self-aligned manner using the second gate electrode 29 as a mask.

Next, after removing the fourth resist pattern, an oxide film or nitride film having a thickness of 130 to 180 nm is deposited on the entire surface of the wafer. Then, the first gate sidewall spacer 14 is formed in the ESD protection element region by anisotropic etching, and the second gate sidewall spacer 30 is formed in the high breakdown voltage device region. Then, as shown in FIG. 22, a fifth resist pattern 70 is formed by photolithography. In the fifth resist pattern 70, the formation region of the first p ⁺⁺ contact region 5 is opened in the ESD protection element region. In the high breakdown voltage device region, the formation region of the second p ⁺⁺ contact region 24 and the p ⁺⁺ collector region 26 is opened. Next, for example, boron ions or BF ₂ ions are implanted using the fifth resist pattern 70 as a mask.

Then, heat treatment is performed, and thermal diffusion is simultaneously performed on the first p ⁺⁺ contact region 5, the second p ⁺⁺ contact region 24, and the p ⁺⁺ collector region 26. As a result, the first p ⁺⁺ contact region 5 is formed in the ESD protection element region. Further, the second p ⁺⁺ contact region 24 and the p ⁺⁺ collector region 26 are formed in the high breakdown voltage device region.

Next, as shown in FIG. 23, a sixth resist pattern 71 is formed by photolithography. In the sixth resist pattern 71, formation regions of the n ⁺⁺ source region 8, the n ⁺⁺ drain region 9 and the n ⁺⁺ contact region 10 are opened in the ESD protection element region. In the high breakdown voltage device region, the formation region of the n ⁺⁺ emitter region 23 is opened. For example, arsenic ions are implanted using the sixth resist pattern 71 as a mask. Then, the sixth resist pattern 71 is removed and the wafer is cleaned. The n ⁺⁺ source region 8 and the n ⁺⁺ drain region 9 are formed in a self-aligned manner using the first gate sidewall spacer 14 as a mask. The n ⁺⁺ emitter region 23 is formed in a self-aligned manner using the second gate sidewall spacer 30 as a mask.

Then, as shown in FIG. 24, heat treatment is performed, and the n ⁺⁺ source region 8, the n ⁺⁺ drain region 9, the first LDD region 6, the second LDD region 7, and the n ⁺⁺ contact region 10 are formed in the ESD protection element region. Form. Further, the n ⁺⁺ emitter region 23 and the third LDD region 22 are formed in the high breakdown voltage device region. Next, a PMD (Pre-metallization Dielectric) film (not shown) is deposited.

  Next, as shown in FIG. 1, the source electrode 15, the drain electrode 16, and the contact electrode 17 are formed in the ESD protection element region. Also, as shown in FIG. 4, the emitter electrode 31 and the collector electrode 32 are formed in the high breakdown voltage device region. Thereafter, an interlayer insulating film, through-holes and wiring layers are formed as many times as necessary to complete a chip.

The step of implanting ions into the formation region of the first p-well region 4 (FIG. 14), the step of implanting ions into the formation region of the n-buffer region 25 (FIG. 15), and the formation of ions in the formation region of the second p-well region 21 The order of the steps of performing the injection (FIG. 16) is not limited to the order described above, and various changes may be made. Further, the ESD protection element 100 and the high breakdown voltage device 110 may be simultaneously manufactured on different chips on the same wafer. Further, when a power MOSFET is manufactured as a high breakdown voltage device, a drain region of the power MOSFET may be formed instead of the p ⁺⁺ collector region 26. The drain region may be a source region of the power MOSFET or an ESD protection element. The drain region and the source region may be formed simultaneously.

In the semiconductor device manufacturing method described above, the isolation region (for example, the isolation trench and the third local oxide film in FIG. 5) that isolates the ESD protection element and the high breakdown voltage device is omitted, but the first local region, for example, is omitted. Before the step of forming the oxide film and the second local oxide film (see FIG. 18), an isolation trench in which an insulator is embedded is formed. Next, the third local oxide film may be formed simultaneously with the formation of the first local oxide film and the second local oxide film. When a p ⁺ diffusion region or a p ⁺⁺ high concentration diffusion region (see, eg, FIG. 8) is formed as the isolation region, for example, the p ⁺ diffusion region is a well region that becomes the n ⁻ semiconductor region 3 and a first p well. The region 4 is formed simultaneously with or before the region 4 is formed. The p ⁺⁺ high concentration diffusion region is formed simultaneously with the step of forming the p ⁺⁺ contact region (see FIG. 22).

In such a manufacturing method, by performing ion implantation for forming the p ⁺ low resistance region 42 in the second p well region 21 before forming the gate electrode, the dose amount of ions at the time of ion implantation is increased. can do. Further, by using a resist mask for forming the p ⁺ low resistance region 42, ions are scattered at the end of the resist mask, and a position where the impurity concentration becomes maximum can be newly formed by the scattered ions. Yes (mask edge effect). In addition, by setting LBP2 to 0.8 μm or more, in the second p well region 21 including the p ⁺ low resistance region 42, the position where the impurity concentration becomes maximum at the interface with the gate insulating film can be separated into two locations. it can.

Further, by forming the first p ⁺ low resistance region 41 and the second p ⁺ low resistance region 42 at the same time, without adding an ion implantation step only for forming the first p ⁺ low resistance region 41, the ESD protection element The first p ⁺ low resistance region 41 can be formed in 100.

Further, when forming the p ⁺ low resistance region in the p well region, by utilizing the mask edge effect, boron ions are converted to 1 × 10 ¹³ cm ⁻² or more and 7.5 × 10 ¹³ cm ⁻ at an acceleration voltage of 100 to 250 keV. By implanting at a dose of ² or less, the impurity concentration in the vicinity of the interface between the p well region and the gate oxide film in the p ⁺ low resistance region is separated from the interface between the p well region and the gate oxide film in the depth direction. The impurity concentration can be lower than the impurity concentration in the region. As a result, the p ⁺ low resistance region can be formed in the p well region while maintaining the threshold voltage of the element substantially.

Next, the impurity concentration of the p ⁺ low resistance region will be described. FIG. 25 is a diagram showing the impurity concentration of the low resistance region at the interface between the gate insulating film and the well region (arrow I in FIG. 1). The arrow I is at a position perpendicular to the gate insulating film, for example, as shown in FIG. In FIG. 25, the horizontal axis represents the depth with reference to the interface between the p-well region and the gate insulating film. Here, the depth of the interface between the p-well region and the gate insulating film is indicated by C point. The vertical axis represents the impurity concentration of the p ⁺ low resistance region. In the ion implantation for forming the p ⁺ low resistance region, boron (B11) ions having a mass number of 11 were set to a dose of 3.5 × 10 ¹³ cm ⁻² at an acceleration voltage of 150 keV. As shown in FIG. 25, the impurity concentration at the interface between the p-well region and the gate insulating film is 2.85 × 10 ¹⁷ cm ⁻³ . In contrast, the impurity concentration in the lower region of the channel region (point D in FIG. 25) is 1.26 × 10 ¹⁸ cm ^−3, which is 4 of the impurity concentration at the interface between the p-well region and the gate insulating film. It turns out that it is 4 times or more. Thus, high impurity concentration of the p ⁺ low resistance region, it can be seen that the resistivity of the p ⁺ low resistance region is lower than the resistivity of the interface between the p-well region and the gate insulating film. Further, the impurity concentration at the interface between the p ⁺ low resistance region and the drain region (including the LDD region) on the silicon surface is higher than the impurity concentration in the lower region of the channel region due to the mask edge effect. Therefore, in the ESD protection element according to the embodiment, the pn junction region (pn junction area 401 in FIG. 30) in which reverse breakdown occurs in the conventional ESD protection element shown in FIG. 30 and the conventional ESD protection element shown in FIG. The reverse breakdown occurs in the pn junction region (pn junction region 51 in FIG. 1) between the pn junction region (pn junction region 402 in FIG. 33) where reverse breakdown occurs.

FIG. 26 is a characteristic diagram showing a breakdown voltage characteristic of the gate oxide film in the ESD protection element according to the embodiment and the conventional ESD protection element. In FIG. 26, the ESD protection element according to the embodiment (hereinafter referred to as Example), the breakdown voltage of the gate oxide film, and the ESD protection element without the low resistance region as shown in FIG. ) And the breakdown voltage of an ESD protection element (hereinafter referred to as a second conventional example) in which a low resistance region is provided over the entire region below the drain region as shown in FIG. In FIG. 26, the drain-source current I _DS and the gate current I _G are standard values. The thickness of the gate oxide film was 15 nm. The ion implantation conditions for forming the low resistance region are the same as those of the ESD protection element shown in FIG. In the results shown in FIG. 26, when the gate voltage V _G applied to the gate oxide film is 10V vicinity, leakage current due to the tunnel effect is beginning to occur. In the first conventional example, almost no leakage current due to the tunnel effect occurred, and the withstand voltage was 14 V or higher. In the second conventional example, when the drain-source voltage V _DS is 5 V, a leak current is generated due to the tunnel effect.

FIG. 27 is a characteristic diagram showing an increase in breakdown voltage of the element with respect to the extension distance LBP1. FIG. 27 is a characteristic diagram showing only the breakdown voltage when the drain-source current I _DS is 1.0 × 10 ⁻⁶ . From the results shown in FIG. 27, when LBP1 is larger than 0.5 μm, the increase in breakdown voltage is almost zero. That is, when LBP1 is larger than 0.5 μm, the breakdown voltage of the ESD protection element is almost the same as the breakdown voltage of the second conventional example shown in FIG. In the second conventional example shown in FIG. 26, since the low resistance region is provided over the entire region below the drain region, LBP1 is regarded as a structure in which the low resistance region is provided in a range larger than 0.5 μm. Can do. Therefore, it can be seen that in the second conventional example, breakdown occurs at a point where the drain-source voltage V _DS is 7V.

  Thus, in the first conventional example, the breakdown voltage of the first conventional example is higher than the voltage at which leakage current starts to occur in the gate oxide film. Therefore, it does not function sufficiently as an ESD protection element, and the gate oxide film or the like of the semiconductor element to be protected cannot be protected. In the second conventional example, since the breakdown voltage is lower than the maximum voltage level of the signal, the circuit does not operate correctly. That is, the breakdown voltage of the ESD protection element is higher than the breakdown voltage of the second conventional example, and a leak current is not generated in the gate oxide film, a range of 7.5 to 9.5 V (hereinafter referred to as a breakdown voltage design range) A It is preferable to be within. The breakdown voltage design range A is a breakdown voltage range that satisfies the ESD design window (see FIG. 26).

FIG. 28 is a characteristic diagram illustrating a breakdown voltage characteristic of the ESD protection element according to the embodiment. For the measurement, an ESD protection element having a comb-like GGFET structure as shown in FIG. 3 was used. ESD protection device having a GGFET structure, the distance between the fingers of the finger portion and the gate electrode of the adjacent drain electrode (hereinafter referred to as a drain-gate distance) and the L _DG and 3.6 [mu] m. The width of the finger part of the gate electrode in the direction parallel to the carrier flow between the source and drain was 1.2 μm, and the width of the finger part of the gate electrode in the vertical direction was 325 μm.

The characteristic diagram shown in FIG. 28 shows the pressure resistance curves of the first sample to the fifth sample in which the LBP 1 and the channel length are changed. The first sample and the second sample had LBP1 of 0 μm and a channel length of 1.2 μm. The third and fourth samples had LBP1 of 0.2 μm and a channel length of 1.2 μm. In the fifth sample, a low resistance region was provided over the entire region under the drain region, and the channel length was set to 1.2 μm. In the first sample and the second sample, the drain-source voltage V _DS was about 8.8 V when the drain-source current I _DS was 1.0 × 10 ⁻⁶ A. In the third sample and the fourth sample, the drain-source voltage V _DS was about 7.6 V when the drain-source current I _DS was 1.0 × 10 ⁻⁶ A. In the fifth sample, the drain-source voltage V _DS was about 7.2 V when the drain-source current I _DS was 1.0 × 10 ⁻⁶ A.

From the results shown in FIG. 28, the first to fourth samples satisfy the withstand voltage design range A. on the other hand. The fifth sample does not satisfy the withstand voltage design range A. This is presumably because in the fifth sample, the area of the pn junction region formed by the drain region and the p ⁺ low resistance region is large, and this pn junction region functions as a Zener diode.

From the above results, the withstand voltage satisfying the withstand voltage design range A can be obtained by adjusting the length of the LBP 1 and reducing the area of the pn junction region formed by the drain region and the p ⁺ low resistance region. all right. In the fifth sample, since the drain-source voltage V _DS is 7.2 V, in order to obtain a breakdown voltage of 7.5 V of the lower limit value of the breakdown voltage design range A, It is desirable to adjust the range. From the results shown in FIG. 27, LBP1 where the increase in breakdown voltage is 0.3 V is 0.3 μm, so LBP1 is 0.3 μm or less, that is, a range B of 0 to 0.3 μm (see FIG. 27). By doing so, the withstand voltage design range A can be satisfied. That is, the breakdown voltage satisfies the ESD design window.

  Further, it was found that even when the ESD protection element according to the present embodiment has a comb-like GGFET structure (see FIG. 3), the ESD protection element having a withstand voltage satisfying the ESD design window can be obtained. The reason is as follows. In the manufacturing method shown in the present embodiment, the low resistance region 85 is not formed in a self-aligned manner using the gate electrode as a mask, but is formed using a photoresist as a mask. Therefore, there is a possibility that a deviation δ due to overlay accuracy occurs in the formation position of the low resistance region 85. Due to this deviation δ, a difference in withstand voltage occurs between the plurality of low resistance regions 85 provided apart from each other. For example, with one finger portion of the drain electrode 82 sandwiched between one finger portion of the adjacent gate electrode 83 (hereinafter referred to as a first gate finger portion), LBP1 is shortened by a deviation δ (LBP1-δ). As a result, the withstand voltage in the vicinity of the low resistance region 85 where the first gate finger portion is provided is increased. On the other hand, in the finger portion of the other gate electrode 83 (hereinafter referred to as the second gate finger portion), LBP1 becomes longer by the displacement δ (LBP1 + δ) in conjunction with the displacement δ in the first gate finger portion. Thereby, the withstand voltage in the vicinity of the low resistance region where the second gate finger portion is provided is reduced. Therefore, the withstand voltage of the entire ESD protection element is determined by the withstand voltage in the low resistance region in which LBP1 becomes longer by the error δ, and is lower than that of the ESD protection element in which no deviation δ occurs.

However, in the ESD protection element having the comb-like GGFET structure shown in FIG. 3, when the LBP1 is 0 μm, the off-breakdown voltage of the ESD protection element is 8.9 to 10.8V. Since the off-breakdown voltage of the ESD protection element is smaller than the breakdown voltage of the gate oxide film (see FIG. 26), a breakdown voltage satisfying the breakdown voltage design range A can be obtained even if a deviation δ due to overlay accuracy occurs. Recognize. Normally, in a semiconductor element manufacturing process that requires high-precision processing in sub-micron units, a shift δ due to overlay accuracy can be suppressed to 0.15 μm or less in photolithography using a photoresist as a mask. For this reason, in the formation of the low resistance region, even if a deviation δ due to overlay accuracy occurs, it is assumed that the same processing as that for adjusting LBP1 in the range of 0 to 0.3 μm is performed. At this time, the voltage at which the leakage current due to the tunnel effect occurs was 7.2 to 9.2V. It was found that the voltage can be lower than the voltage at which leakage current starts to occur in the gate oxide film. As described above, in the ESD protection element having the structure as shown in FIG. 3, even when a shift δ due to overlay accuracy is caused by photolithography using a photoresist as a mask when forming the p ⁺ low resistance region, It has been found that an ESD protection element having a withstand voltage that satisfies the ESD design window can be formed.

  Further, in the ESD protection element having the structure as shown in FIG. 3, the size of the ESD protection element can be easily set by increasing / decreasing the finger portions of each electrode. Therefore, an ESD protection element can be efficiently manufactured according to the ESD charge amount.

As described above, according to the embodiment, by forming the a first 1p ⁺ low resistance region 41 of the ESD protection device 100 and the 2p ⁺ low resistance region 42 of the high voltage devices 110 simultaneously, the 1p ⁺ The first p ⁺ low resistance region 41 can be formed in the ESD protection element 100 without adding an ion implantation process only for forming the low resistance region 41. Further, by forming the first p ⁺ low resistance region 41 in the ESD protection element 100 by the manufacturing method described above, almost the same as the ESD protection element of the second conventional example in which the low resistance region is formed (see FIG. 33), The breakdown voltage of the ESD protection element can be reduced. Thereby, an ESD protection element having a withstand voltage that satisfies the ESD design window can be manufactured, and the manufacturing cost of the entire circuit in which the ESD protection element 100 is integrated can be reduced. Further, the p well region including the low resistance region may be formed so that the impurity concentration at the interface with the gate insulating film is lower than the impurity concentration in the region away from the interface with the gate insulating film in the depth direction. it can. In addition, the second p well region 21 including the low resistance region can be formed so as to separate the position where the impurity concentration is maximized at the interface with the gate insulating film into two locations. As a result, a low resistance region can be formed in the p-well region while substantially maintaining the threshold voltage of the element.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the dimensions, concentrations, dopants, and the like described in the embodiments are examples, and the present invention is not limited to these values. In each embodiment, the first conductivity type is p-type and the second conductivity type is n-type. However, the present invention is the same even if the first conductivity type is n-type and the second conductivity type is p-type. It holds.

  Note that an isolation region that electrically isolates the ESD protection element and the high breakdown voltage device on the same substrate may be provided to isolate the ESD protection element from other devices.

  As described above, according to the semiconductor element, the semiconductor device, and the method for manufacturing the semiconductor element according to the present invention, a semiconductor used for protecting a power IC for driving a plasma display or the like from a voltage surge such as electrostatic discharge (ESD). It is useful as an element.

DESCRIPTION OF SYMBOLS 1 p support substrate 2 Insulating layer 3 n ^- semiconductor region 4 p well region 5 p ⁺⁺ contact region 6 LDD (shallow source) region 7 LDD (shallow drain) region 8 n ⁺⁺ source region 9 n ⁺⁺ drain region 10 n ⁺⁺ contact region 11 local oxide film 12 gate insulating film 13 gate electrode 14 gate side wall spacer 15 source electrode 16 drain electrode 17 contact electrode 41 p ⁺ low resistance region 51 pn junction region 100 ESD protection element

Claims (13)

A second conductivity type source region provided in a part of the first conductivity type first well region;
A drain region of a second conductivity type provided in a part of the first well region;
A first gate insulating film provided on a surface of the first well region between the source region and the drain region;
A first gate electrode provided on the first gate insulating film;
A first conductivity type having a resistivity lower than that of the first well region provided in a part of the first well region in the source region, a region below the source region, and a region below the first gate insulating film. A first low-resistance region of
A source electrode in contact with the source region and short-circuited to the first gate electrode;
A drain electrode in contact with the drain region;
A semiconductor device comprising: A first semiconductor region of a second conductivity type provided on the surface of the support substrate via an insulating layer;
The first well region is provided in a part of the first semiconductor region,
A portion of the first well region is provided with a first contact region of a first conductivity type that is electrically connected to the source region and has a lower resistivity than the first well region,
A portion of the first semiconductor region is provided with a second contact region of a second conductivity type having a resistivity lower than that of the first semiconductor region apart from the first well region.
The semiconductor device according to claim 1, wherein the first gate electrode is further short-circuited to a contact electrode in contact with the second contact region. A first semiconductor region of a second conductivity type provided on the surface of the support substrate;
The first well region is provided in a part of the first semiconductor region,
A portion of the first well region is provided with a first contact region of a first conductivity type that is electrically connected to the source region and has a lower resistivity than the first well region,
A portion of the first semiconductor region is provided with a second contact region of a second conductivity type having a resistivity lower than that of the first semiconductor region apart from the first well region.
The semiconductor device according to claim 1, wherein the first gate electrode is further short-circuited to a contact electrode in contact with the second contact region. A second semiconductor region of the first conductivity type provided on the surface of the support substrate;
The first well region is provided in a part of the second semiconductor region,
A part of the first well region is provided with a first conductivity type first contact region which is electrically connected to the source region and has a lower resistivity than the first well region. The semiconductor device according to claim 1. A first conductivity type support substrate;
The first well region is provided in a part of a surface layer of a first conductivity type support substrate;
A part of the first well region is provided with a first conductivity type first contact region which is electrically connected to the source region and has a lower resistivity than the first well region. The semiconductor device according to claim 1. A third semiconductor region of a second conductivity type provided in a part of the first well region so as to be in contact with the source region and shallower than the source region;
A second conductivity type fourth semiconductor region provided in a part of the first well region so as to be in contact with the drain region and shallower than the drain region;
The first low-resistance region is further provided in the third semiconductor region and a region below it, the fourth semiconductor region and a region below it, and a part of the drain region and a region below it. The semiconductor device according to claim 1, wherein the semiconductor device is characterized in that:   The distance from the end of the first low resistance region on the drain region side to the end of the first gate electrode on the drain region side is in the range of 0 μm to 0.3 μm. The semiconductor element as described in any one of Claims 1-6. A semiconductor device according to claim 1, wherein the semiconductor element (hereinafter referred to as a first semiconductor element) and the second semiconductor element are formed on the same wafer.
The first semiconductor element and the second semiconductor element are electrically separated by a trench formed deeper than a first well region of the first semiconductor element and embedded with an insulator. Semiconductor device. A semiconductor device according to claim 1, wherein the semiconductor element (hereinafter referred to as a first semiconductor element) and the second semiconductor element are formed on the same wafer.
The first semiconductor element and the second semiconductor element are electrically isolated by a diffusion region of a first conductivity type formed deeper than a first well region of the first semiconductor element. Semiconductor device. A method of manufacturing a semiconductor device, wherein the semiconductor device according to any one of claims 1 to 7 (hereinafter referred to as a first semiconductor device) and a second semiconductor device are formed on the same wafer.
A first conductivity type first low resistance region having a resistivity lower than that of the first well region is formed in the first conductivity type first well region formed on the wafer and formed on the wafer. Forming a first resistance type second low resistance region having a lower resistivity than the second well region in the first conductivity type second well region,
A gate insulating film, a gate electrode, a source region and a drain region of the first semiconductor element are formed in the first well region and the first low resistance region, and in the second well region and the second low resistance region. A first element formation step of forming a gate insulating film, a gate electrode, and a second conductivity type fifth semiconductor region of the second semiconductor element;
A second element forming step of forming a first conductive type or a second conductive type sixth semiconductor region in the second conductive type first semiconductor region provided with the second well region apart from the second well region; When,
The manufacturing method of the semiconductor element characterized by the above-mentioned.   In the low resistance region forming step, boron ions are ion-implanted at an acceleration voltage of 100 keV to 250 keV to form the first low resistance region and the second low resistance region. Item 11. A method for manufacturing a semiconductor element according to Item 10. In the low resistance region forming step, boron ions are ion-implanted at a dose of 1 × 10 ¹³ cm ⁻² or more and 7.5 × 10 ¹³ cm ⁻² or less, so that the first low resistance region and the 12. The method of manufacturing a semiconductor element according to claim 10, wherein the second low resistance region is formed. Before the step of forming the gate insulating film of the first semiconductor element and the gate insulating film of the second semiconductor element in the first element forming step,
In a nitrogen atmosphere, annealing is performed for 30 minutes or less at a temperature of 900 ° C. or higher and 950 ° C. or lower to control the diffusion of the low resistance region and recover the disorder of the crystal lattice generated in the low resistance region forming step. The method for manufacturing a semiconductor device according to claim 10, further comprising an annealing step.

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