JPH01235371A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the occupying area of a chip while improving the capacitance of transistors, and to shorten the delay time in an electric circuit manner by forming the gate length of the transistor for a series circuit in size shorter than that of the transistors for other circuit sections. CONSTITUTION:A series circuit composed of two or more transistors such as transistors Q1-Q3 is connected between a power cable 11 or a grounding cable 10 for an FET. The gate length L of the transistors Q1-Q3 is made shorter than that of transistors for other peripheral circuits only by approximately 0.1mum. Consequently, gate length is determined in short size to a possible minimum value from the view point of electrical characteristics and reliability by the characteristics of the transistors decided by a process for a semiconductor integrated circuit device in length where the gate length of the transistors is made shorter than that of transistors for normal circuits Q7, Q8, etc., but it is determined normally from simulation and the transistor characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to the gate length of a transistor constituting a specific circuit.

[Conventional technology]

Conventionally, the gate lengths of transistors used in semiconductor integrated circuit devices have been kept constant except for the first-stage transistor of the input circuit, the transistor of the memory cell, the output transistor, and the like. Furthermore, in complementary integrated circuit devices, P-channel transistors and N-channel transistors may have different gate lengths;
At least transistors of the same conductivity type had the same gate length.

For example, in the case of a three-person circuit using complementary semiconductors as shown in FIG. 2, the mask pattern is as shown in FIG. 4.

That is, the gate lengths of transistors Q1 to Qs were the same as those of transistors in other peripheral circuits. That is, N
Channel transistors Q, ~Q3. The gate length of Q7 and the gate lengths of P channel transistors Q4 to Qa and Qs were configured to be exactly the same.

[Problem to be solved by the invention]

Many LSI circuits have conventional circuits in which transistors are connected in series in multiple stages as shown in Figure 2.
It is particularly used in decoder circuits of memory integrated circuit devices. This decoder circuit has the disadvantage that it is used repeatedly to decode a large number of signal lines, and the chip requires a large area. In addition, the transistor performance decreases in this circuit portion, increasing the delay time of the circuit, and generally when n stages of transistors are connected in series, the transistor performance becomes 1/n.

The purpose of the present invention is to eliminate such drawbacks, shorten the gate length, reduce the chip area, and
An object of the present invention is to provide a semiconductor integrated circuit device with improved transistor performance.

[Means to solve the problem]

The configuration of the present invention provides a semiconductor integrated circuit device including a series circuit in which at least two or more transistors are connected in series between 11 power supply poles or a ground electrode and an output electrode of a field effect transistor, the gates of the transistors of the series circuit. It is characterized in that its length is shorter than the gate length of transistors in other circuit sections.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a mask pattern diagram of an embodiment of the present invention,
A case is shown in which the present invention is applied to a circuit of a complementary semiconductor integrated circuit device as shown in FIG. In this embodiment, transistors Ql, Q2 . The gate length of Q3 is compared to other peripheral circuit transistors! + Shortened by 0.1 μm. This work to shorten the gate length does not require any special man-hours compared to the conventional method.

In this embodiment, the gate length of the transistor is set to the normal circuit Q7. The pQ is 1 μm shorter than transistors such as Q8, but this is due to the characteristics of the transistor determined by the process of semiconductor integrated circuit devices, and it is difficult to shorten the gate length to a value that is possible from the viewpoint of electrical characteristics and reliability. Yes, usually determined from simulation and transistor characteristics. Further, although this embodiment is applied to a complementary semiconductor integrated circuit device, the present invention is not limited to this.

Generally, the gate length of a two-transistor is made short to a length that does not cause problems in terms of electrical circuits and reliability in the manufacturing process of the semiconductor integrated circuit device. Normally, it is not possible to form a transistor with a gate length shorter than this due to the reliability of the electric circuit or the device. However, in a circuit in which transistors are connected in series in multiple stages, the voltage applied to each transistor is low, and there is a margin in terms of electrical circuit reliability. There is no problem even if the length is shortened. However, problems in electric circuits and reliability include transistor breakdown, driver ability, hot carriers, and latch/amplifier breakdown voltage in CMOS devices.

FIG. 3 is a circuit diagram applied to a second embodiment of the present invention. Transistors Qll-Q131Q17 are N-channel transistors, and transistors Q14 to Qss +
Q+s is a P-channel transistor. In this example, three P-channel transistors Q connected directly
14~Q 1s gate length 02 than other transistors
The capacity of the transistor is increased by μrnm<. The dimensions of each transistor in this case are as shown in Table 1.

〔Effect of the invention〕

As explained above, in the case of a circuit in which at least two or more transistors are connected in series between the image line or the ground line and the output end side, the present invention can change the gate length of the transistor without requiring any special man-hours. By making the transistors constituting the circuit shorter, it is possible to increase transistor performance, reduce delay time in terms of electrical circuits, and reduce the circuit area and chip size.

[Brief explanation of the drawing]

FIG. 1 is a mask pattern diagram of an example of a complementary semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of FIG. 1,
FIG. 3 is another circuit diagram equivalent to FIG. 2, and FIG. 4 is a mask pattern diagram when the conventional example is applied to the circuit of FIG. 2. 1.2.3...Input terminal, 5...Output terminal, 10.
...Grounding wire, 11...Power wire, 12...Wiring, 13
...N+ diffusion layer, 14...P+ diffusion layer, 15...
Gate wiring, 16゛°' contact, Ql~Qa +
Q? r Qtt~Qts r Q7°°゛N channel transistor, Q4~Qs + Qs + Q14~Q
Cs r Q+s...P channel transistor. Agent Patent Attorney Uchihara Oto

Claims (1)

[Claims] In a semiconductor integrated circuit device including a series circuit in which at least two or more transistors are connected in series between a power supply electrode or a ground electrode and an output electrode of a field effect transistor, the gate length of the transistor in the series circuit is longer than that of other circuit parts. A semiconductor integrated circuit device characterized by having a structure shorter than the gate length of a transistor.