JPS59231847A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To assure the protection of a gate insulating film by a method wherein an IC with an input protecting circuit between an input terminal and an internal circuit is composed of an electric resistor with a protecting circuit series-inserted thereinto and a clamp element with the protecting circuit parallel-inserted thereinto while the clamp elemnt is composed of a parasitic MOSFET provided underneath the resistor serving both as a gate electrode of this FET. CONSTITUTION:An electric resistor Ri with a protecting circuit series-inserted thereinto and a clamp element Q1 with the protecting circuit parallel-inserted thereinto comprising MOSFET element are provided between an input terminal pad IN and an internal circuit IC. In other words, source and drain regions 12 are diffusion-formed on the surface layer of a semiconductor substrate 10 and the gaps between the regions 12 are covered with a thick insulating film 14 and the overall surface of the film 14 is further covered with another insulating film 16. Next a resistor Ri comprising multicrystal-line Si is provided on the film 16 located between the regions 12 while a parasitic MOSFET element Q1 is composed of the insulating film 14 and the gate insulating film 16. Through these procedures, the drain region D and the resistor Ri to be a gate electrode in the regions 12 are connected to the internal circuit IC while the source region S is grounded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique that is particularly effective when applied to a semiconductor integrated circuit device, for example, a technique that is effective when applied to a human power protection circuit.

[Background technology]

In MOS type semiconductor integrated circuit devices, internal circuits are likely to be destroyed by overvoltage such as static electricity applied to input terminals. Therefore, a human power protection circuit should be interposed between the input terminal and the internal circuit.

FIG. 1 shows a human power protection circuit previously studied by the inventor. The input capture circuit shown in the figure has a resistor Ri inserted in series between the input terminal pad IN and the internal circuit IC, and an MO8 field effect transistor D as a clamp element.
It is formed by inserting I in parallel. Polycrystalline silicon is used as the resistor 11i. Further, the drain D of the MO8 W-effect transistor used as a clamp element is connected to the resistor Ri side, and the gate G and source S are commonly connected to the substrate side. As a result, a clamp diode utilizing the PN junction of the old MO8 field effect transistor is formed between the drain D side and the north S side.

Here, when static electricity of a voltage, for example, is applied to the input terminal pad INK, the applied voltage is applied to the resistor layer and MO8.
It is clamped by field effect transistor D1, thereby protecting the internal circuit IC.

By the way, the above-mentioned input protection circuit is formed between the input end pad IN of the semiconductor substrate and the internal circuit c with the layout shown in FIG. 2. In this case, the following problems arise. The inventor has revealed that there is. That is, a sufficiently large layout area must be allocated to the MO8 field effect transistor as a clamp diode. Otherwise, it will not be possible to provide enough current capacity to absorb destructive energy such as static electricity, and the battery will not be able to function as a color circuit.

However, if a sufficient layout area is allocated to the MO8 field effect transistor DI, a problem arises in that the layout area allocated to the internal circuit IC becomes smaller. It has become clear that in a semiconductor integrated circuit device equipped with a 5Vc input preservation circuit, a troublesome problem arises in that improving the preservation rTIK>4 capability and securing the layout area of the internal circuit conflict with each other. Ta.

Furthermore, in the above example, the MO8 field effect transistor D
Clamp die by IVC, clamp voltage of t-t is PN
This is due to the break-down voltage of the junction diode, but variations tend to occur in the formation of this PN junction.

For this reason, the inventors have found that there is a problem in that the clamp voltage value varies widely and it is difficult to obtain a reliable and effective accent protection function with good reproducibility.

[Purpose of the invention]

One object of the present invention is to provide a protection means that can reliably maintain RΦ of a gate insulating film of a MOS FET.

One object of the present invention is to provide a human power protection element having a current h that can sufficiently absorb destructive energy such as static electricity.

One object of the present invention is that the clamp 'tl'? The object of the present invention is to provide a manpower protection device with low pressure.

One object of the present invention is to provide a semiconductor bond circuit having a protection W7'1 circuit that allows a layout that can effectively utilize the tf+j product on the board.

One object of the present invention is to provide an input storage technique H1 that can provide reliable protection.

One object of the present invention is to provide an input/output circuit technology suitable for a screen-integrated integrated circuit.

One object of the present invention is to provide a semiconductor substrate with a relatively small layout area and a reliable and effective input security function with good reproducibility on a semiconductor substrate with a limited area size. An object of the present invention is to provide an integrated lr1 circuit device.

d) The above and other objects and novel features of the invention will be clearly understood from the description in Part 9 of this specification and the accompanying drawings.

[Summary of the invention]

A brief explanation of typical implantation methods among the inventions disclosed in this application is as follows.

That is, the input holding circuit is formed by a gas resistor inserted directly into the input circuit and a clamp element inserted in parallel with the input circuit.
-T' (Ill
VC is formed by the parasitic current for 40s and the '1'-effect transistor (j・'C is formed, and then the above resistor is
Gate electrode of the second parasitic MO3 field effect transistor,
11■ Suseto,)Yoshishi, Koharr(Yori...j fI'
i-Rise's limited half 2!71 board with 2 relatively few layerers and 1 f.

It achieves the objective of making it possible to reliably and effectively capture inputs.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In one drawing, the same or corresponding parts are indicated by the same reference numerals.

FIG. 3, FIG. 4, and FIG. 5 show an embodiment of a main part of a semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit device shown in the figure is of the MOS type, and its internal circuit IC is constructed using C-MO3 field effect transistors.

First, as shown in FIG. 3, an electric resistor Ri inserted in series between the input terminal pad IN and the internal circuit IC;
A clamp element (Q
l) constitutes an input protection function. The clamping element is formed by an MO8 field effect transistor (Ql).

Furthermore, as shown in FIGS. 4 and 5, the MO8
The field effect transistor (Ql) is constituted by a parasitic MO8 field effect transistor Q1 formed under the resistor Ri. The resistor Ri serves as the gate electrode (G) of the parasitic MO8 field effect transistor Q1.
It also serves as

That is, the resistor Ri also serves as the gate G of the parasitic MO8 field effect transistor Q1.

Here, FIG. 4 shows the layout state of the above-mentioned input protection circuit portion, and FIG.
OS (LOCal Oxidation of 5i
A partially oxidized licon film 14 is formed.

An insulating film 16 is further provided on this LOCO 314, and the resistor 1 (1) is provided on this insulating film 16. The resistor Ri&C is made of polycrystalline silicon (polysilicon).
is used. Further, the parasitic Mos field effect transistor Q1 is formed using the LOCO 814 and the insulating film 16 thereon as a gate insulating film. On the insulating film 16, a resistor Ri which also serves as a gate electrode (G) is provided.

Further, diffusion layers 12.12 are formed in the semiconductor substrate 100 portions on both sides of the LOCO 814, and these are ? ff4
These become the drain D and source S of the EMO8 field effect transistor Q1. Here, L is the gate length (channel length) of the parasitic MO3FET.

As shown in FIG. 3, the parasitic MO3 field effect transistor Q1 has its drain D and upper gate G both connected to the internal circuits T and C of the resistor R1, and its source S connected to the ground iiL ( or power supply potential). These connections are made in this example by aluminum electrodes (arrangements) 20. As a result, the above Z-S raw M
Drain D and source 78 of O8 field effect transistor Q1
When a voltage higher than a certain threshold voltage is applied between them, the applied voltage is bypassed from the drain D to the source S(fil, and as a result, the voltage at the drain D(Ill) is clamped below a certain level.

Here, the above-mentioned clamp voltage is not due to the breakdown voltage of the quartz, but due to the gate threshold voltage of the parasitic MO8 field effect transistor Q1. Therefore, its value can be freely and reproducibly set depending on the gate length, the thickness of the insulating film, etc. Thereby, a reliable and efficient input protection function can be obtained. In addition, the parasitic MO8 field effect transistor Q1
Since is formed overlapping with the resistor Ri, it does not occupy a large layout area alone. As a result, the area of the semiconductor substrate 100 can be used efficiently, and a large layout area can be allocated to the internal circuit IC along with a sufficient input protection function. That is, the first layer of polycrystalline Si was used as a general +7) FETI/)GeHC film, and the second layer of polycrystalline Si formed on a PSG (CVD S+02 film) was used as wiring and a resistor. It is particularly effective when applied to a 10 S FET process on two-layer polycrystalline S+.

In addition, a similar structure can be used in the single-layer polycrystalline Si process, but in this case, the gate of the parasitic MOSFET is directly on the L0CO8 oxide film, so the clamping voltage is considerably lower. It may be lower.

〔effect〕

A) Without using the A1 electrode on a multilayer insulating film.

Parasitic M on the first or second polycrystalline layer existing below
By using it as the gate electrode of O3FET (clamp element), the effective thickness of the gate insulating film becomes thinner.
The crank voltage of the surface preserving element can be lowered.

High resistance polycrystalline Si and parasitic 1'1. (By using the OSFET as a clamp diode, the layout surface fat can be reduced.

When the second layer of polycrystalline Si is used as the electrode of the clamp diode, the clamp voltage can be set to the desired value with relative precision by appropriately controlling the LOCOS oxide layer and the PSG layer . Can be well controlled. Also, under the LOCOS oxide film in the non-active area [4
Impurities to prevent channel inversion (by ion implantation).

) can also control the crank voltage.

By making the resistor that constitutes the input mining circuit also serve as the gate of the parasitic MO8 field effect transistor, it can be used on a semiconductor substrate with a limited area size.

With a relatively small layout area, a reliable and effective input/protection function can be obtained with good reproducibility.

The invention developed by the present inventor has been specifically explained based on Examples.1 However, this invention is not limited to the above-mentioned Examples, and can be carried out without departing from the gist of the invention.
It goes without saying that it can be changed in various ways. For example, the resistor may be made of other than polycrystalline silicon.

In addition, although the above explanation has been made with reference to the LOCOS Brochus, the present invention is not limited thereto, but instead of the 5 planar process +? It can also be applied to processes such as creating and separating i'j"i.

In the above explanation, the contact between the gate of the crank element and the diffusion layer is made by the A2 wiring.

Polycrystalline Si may also be used.

Furthermore, in Fig. 3, the clamp diode is placed after or in the latter half of the protective resistor when viewed from the input terminal, but the present invention is not limited to this circuit diagram; Further, the use in combination with other protection elements does not change the technical idea of the present invention at all.

[Application field]

In the above explanation, the invention made by the present inventor has mainly been explained with respect to a MOS type semiconductor integrated circuit device, which is the field of application which is the background of the invention, but it is not limited thereto, and other input protection devices may also be used. Of course, it can also be applied to any required semiconductor integrated circuit device.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an input protection circuit portion of a semiconductor integrated circuit device that was investigated by the present inventor prior to the present invention. FIG. 2 is a diagram showing an example of the layout state of the portions constituting the circuit diagram of FIG. 1. FIG. 3 is a circuit diagram showing an embodiment of the input extraction circuit portion of the semiconductor integrated circuit device according to the present invention. FIG. 4 is a diagram showing an example of a layout state of a portion forming 4'Mt of the circuit diagram of FIG. 3. FIG. 5 shows a cross-sectional state of the parts constituting the circuit diagram of FIG. 3, and is a diagram corresponding to the cross section of FIG. , Ri - Resistor made of polycrystalline silicon, Dl - MO8tO8 field effect transistor forming a clamp diode - gate. D...drain, S...source, IC...internal circuit, Ql...parasitic MO8 field effect transistor, 10
... Semiconductor substrate, 12... Diffusion layer, 14... LO
CO3 (partial oxide film), 16...insulating film, 20 - aluminum electrode (wiring). Fig. 1 Fig. 3 Fig. U Fig. 4 ``・1 ・ -1suA Fig. 5 Ikro Computer Engineering Co., Ltd. No. 1

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device σ in which a human power protection circuit is interposed between an input terminal and an internal circuit, wherein the human power protection circuit is
The circuit includes a drowsiness resistor inserted in series with the input circuit,
A first component is formed by W and a clamp element inserted in parallel to the input circuit, the clamp element is formed by a parasitic MO8 field effect transistor formed under the resistor, and the resistor is connected to the resistor. 1. A semiconductor integrated circuit device comprising a gate electrode of a parasitic MO8 field effect transistor. 2. A semiconductor integrated circuit device according to claim 1, wherein the resistor is made of polycrystalline silicon. 3. Claims 1 and 2 are attached to device vi', and the above %T raw MO8 field effect transistor is formed with LOCO3 (partial oxide film) interposed below the resistor as a gate insulating film. A semiconductor integrated circuit device characterized by: