JPH0691195B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a technique effectively applied to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device using a polycrystalline silicon film as a resistance element. And effective technology.

BACKGROUND ART A semiconductor integrated circuit device provided with a MISFET has a phenomenon in which a gate insulating film of a MISFET forming an input stage circuit of an internal integrated circuit is destroyed by excessive static electricity induced by its artificial handling (hereinafter, Electrostatic breakdown) is likely to occur.

Therefore, it is necessary to insert an electrostatic breakdown prevention circuit between the external terminal of the semiconductor integrated circuit device and the input stage circuit to prevent electrostatic breakdown.

As described in the specification of Japanese Patent Application No. 57-160999 previously filed by the applicant of the present invention, the electrostatic breakdown prevention circuit includes a resistance element for blunting an excessive voltage and a MISFET for clamping to clamp the excessive voltage. It is advantageous in terms of the structure process to use the one constituted by

The resistance element is usually provided in a p-type well region.
Some are made of n ⁺ type semiconductor regions, and some are made of a polycrystalline silicon film provided on the semiconductor substrate with an insulating film interposed therebetween.

For the resistance element formed of a polycrystalline silicon film, a polycrystalline silicon film is used in which phosphorus is diffused by performing heat treatment in a phosphorus atmosphere in order to obtain an appropriate resistance value (hereinafter referred to as phosphorus treatment). Has been.

This polycrystalline silicon film is usually used to form a gate electrode of a MISFET, and the phosphorus treatment sets the resistance value to about 30 [Ω / □], for example. .

However, as a result of study in such a technique, when the resistance element is formed of a phosphorus-treated polycrystalline silicon film, its resistance value is low, and thus a large area is required to obtain sufficient electrostatic breakdown strength. Then, they found a problem that it hinders the degree of integration of the semiconductor integrated circuit device.

[Object of the Invention] An object of the present invention is to provide a technical means capable of reducing the area required for a resistance element formed of a polycrystalline silicon film and improving the degree of integration of a semiconductor integrated circuit device. .

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Outline of the Invention] The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, in a semiconductor integrated circuit device having an electrostatic breakdown prevention circuit, a polycrystalline silicon film not subjected to phosphorus treatment is provided, and impurities for forming a source region or a drain region of MISFET are introduced into the polycrystalline silicon film. . As a result, a resistance element can be formed of a polycrystalline silicon film having a resistance value of about several hundred [Ω / □], and the area required for the resistance element can be reduced. The degree can be improved.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device (hereinafter referred to as EPROM) having a read-only storage function capable of rewriting information by ultraviolet rays.

[Embodiment I] FIG. 1 is an equivalent circuit diagram showing an input portion of an EPROM for explaining an embodiment I of the present invention, and FIG. 2 is a plan view showing a concrete configuration of FIG. . FIG. 2 does not show insulating films other than the field insulating film provided between the conductive layers for the sake of easy understanding of the structure.

In all the drawings of the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

In FIG. 1, BP is an external terminal for inputting a signal to the internal integrated circuit of the EPROM.

Qp is a p-channel MISFET, Qn is an n-channel MISFET, and is for forming a complementary MISFET (hereinafter referred to as CMIS).

Vcc is a voltage terminal (for example, +5.0 [V]) and is connected to the source region of the p-channel MISFET Qp.

Vss is a voltage terminal (for example, 0 [V]), and is the source region of the n-channel MISFET Qn or the MISF for clamping described later.
The source region of ET and the gate electrode are connected.

P-Out is an output terminal to which the drain regions of MISFETQp and Qn are connected.

Reference numeral I is an inverter circuit, which is composed of MISFETs Qp and Qn, and is for forming an input stage circuit of the EPROM.

R is a resistance element, one end of which is connected to the external terminal BP and the other end of which is connected to the input stage circuit. The resistance element R serves to dull an excessive voltage that causes electrostatic breakdown.

Qc is a clamp MISFET, one end of which is connected to the external terminal BP and the input stage circuit via the resistance element R, and the other end of which is connected to the voltage terminal Vss. This MISFET Qc for clamp is
It is for clamping an excessive voltage that causes electrostatic breakdown.

II is an electrostatic breakdown prevention circuit, for resistance element R and clamp
MISFETQc and is provided between the external terminal BP and the input stage circuit I. This electrostatic breakdown prevention circuit II is for preventing electrostatic breakdown due to an unexpected excessive voltage input from the external terminal BP.

In FIG. 2, reference numeral 1 denotes a p ⁻ type semiconductor substrate made of single crystal silicon, which is used to form an EPROM.

Reference numeral 2 denotes an n ⁻ type well region, which is provided on a predetermined main surface portion of the semiconductor substrate 1. The well region 2 is for forming a CMIS.

A field insulating film 3 is provided on the main surface of the semiconductor substrate 1 or on the main surface of the well region 2. The field insulating film 3 is for electrically separating the semiconductor elements.

Reference numeral 4 denotes a conductive layer, which is provided on the gate insulating film (not shown) to be a semiconductor element forming region between the field insulating films 3. The conductive layer 4 is formed in the first conductive layer forming step in the manufacturing process, and is mainly for forming the gate electrode of the MISFET.

The conductive layer 4 is formed, for example, by chemical vapor deposition (hereinafter, CVD
In order to reduce the resistance, phosphorus as an impurity is introduced by diffusion into the polycrystalline silicon film formed by the above technique, that is, the polycrystalline silicon film is formed by the phosphorus treatment.
This phosphorus treatment sets the resistance value of the polycrystalline silicon film to about 30 [Ω / □], for example, in order to form the gate electrode of the MISFET.

Reference numeral 5 denotes a conductive layer, which is provided on a predetermined upper portion of the field insulating film 3. This conductive layer 5 is the second layer in the manufacturing process.
It is formed in the conductive layer forming step of the second layer, and is mainly for constituting the resistance element R of the electrostatic breakdown prevention circuit.

The conductive layer 5 is formed, for example, by providing a polycrystalline silicon film which is not subjected to phosphorus treatment by a CVD technique, and introducing impurities forming the source region and the drain region of the MISFET into the polycrystalline silicon film. This conductive layer 5 can be set to a resistance value of, for example, about several hundred [Ω / □] because impurities that form the source region or the drain region of the MISFET are introduced.

The resistance element R of the electrostatic breakdown prevention circuit may be formed by the conductive layer 4 in the first conductive layer forming step in the manufacturing process. In this case, the conductive layer 5 formed in the second conductive layer forming step in the manufacturing process is formed of a refractory metal layer (for example, Mo, Ti, Ta, W) or a compound of refractory metal and silicon. A silicide film (for example, MoSi ₂ , TiSi ₂ , TaSi ₂ , WS
i ₂ ), a refractory metal layer may be formed on the polycrystalline silicon film, or a silicide film may be formed on the polycrystalline silicon film.

Reference ^numeral 6 denotes an n ⁺ type semiconductor region, which is provided on the main surface portion of the semiconductor substrate 1 on both sides of the conductive layer 4 which becomes the semiconductor element forming region. The semiconductor region 6 is mainly used as a source region or a drain region, and has an n-channel MI.
This is for configuring the SFET and the clamp MISFET.

Reference ^numeral 7 denotes ap ⁺ type semiconductor region, which is provided on the main surface of the well region 2 on both sides of the conductive layer 4. This semiconductor region 7 is
It is mainly used as a source region or a drain region, and is for forming a p-channel MISFET.

The n-channel MISFETQn or the clamp MISFETQc is mainly composed of a semiconductor substrate 1, a conductive layer 4, a gate insulating film (not shown), and a semiconductor region 6.

The clamp MISFET Qc has a ring shape.

The p-channel MISFETQp is mainly composed of the well region 2, the conductive layer 4, the gate insulating film (not shown), and the semiconductor region 7.

Reference numeral 7A denotes ap ⁺ type semiconductor region, which is provided on the main surface portion of the semiconductor substrate 1 so as to surround the clamp MISFET Qc. The semiconductor region 7A is formed in the same manufacturing process as the semiconductor region 7, and is for stably holding the potential of the semiconductor substrate 1 in the vicinity thereof and for stably operating the clamping MISFET Qc.

8A to 8F are conductive layers, which are provided on the conductive layers 4 and 5 via an insulating film (not shown). The conductive layers 8A to 8F are formed in the third conductive layer forming step in the manufacturing process, and are mainly for electrically connecting the semiconductor elements.

A plurality of conductive layers 8A are provided in the peripheral portion of the semiconductor substrate 1 so as to be arranged, and serve to form the external terminal BP.

The conductive layer 8B has one end connected to the conductive layer 8A and the other end connected to one end of the conductive layer 5 serving as the resistance element R through the connection hole 9A.

The conductive layer 8C has one end connected to the other end of the conductive layer 5 serving as the resistance element R through the connection hole 9A, and the other end serving as the drain region of the clamping MISFET Qc through the connection hole 9B and the connection hole. It is connected to the conductive layer 4 which becomes the gate electrodes of MISFETs Qp and Qn through 9A.

The conductive layer 8D has one end through the connection hole 9B for clamping MISF.
Conductive layer 4 to be the gate electrode of ETQc, semiconductor region 7A and MI
It is connected to the semiconductor region 6 serving as the source region of SFETQn, and the other end is connected to the voltage terminal Vss.

The conductive layer 8E has one end connected to the semiconductor region 7 serving as the source region of the MISFET Qp through the connection hole 9B, and the other end connected to the voltage terminal.
Connected to Vcc.

One end of the conductive layer 8F is connected to the semiconductor region 6 serving as the drain region of the MISFET Qn and the semiconductor region 7 serving as the drain region of the MISFET Qp through the connection hole 9B, and the other end thereof is connected to the input portion (output terminal P-Out of the next stage circuit). )It is connected to the.

Next, a specific manufacturing method of this Example I will be described.

3 to 12 are cross-sectional views of the essential parts of the EPROM in each manufacturing process for explaining the manufacturing method of the embodiment I of the present invention.

In FIGS. 3 to 12, MC is a memory cell (field effect transistor) formation region having a floating gate electrode and a control gate electrode.

NM is n channel MISFETQn (or clamp MISFETQc)
It is a formation area.

PM is a p-channel MISFETQp formation region.

HNM is an n-channel MISFET formation region having a double drain structure provided for the purpose of increasing the breakdown voltage.

CM is a high voltage (for example,
21 [V]) and a low voltage (for example,
The voltage control MISFET formation region controls the voltage control of about 5 [V].

R is a resistance element forming region of the antistatic breakdown circuit.

First, a p ⁻ type semiconductor substrate 1 made of single crystal silicon is prepared.

Then, the p-channel MISFETQp formation region PM, for voltage control
An n ⁻ type well region 2 is formed in the main surface portion of the semiconductor substrate 1 in the MISFET formation region CM and the resistance element formation region R.

After that, a field insulating film 3 is formed on the upper part of the main surface of the semiconductor substrate 1 and the upper part of the main surface of the well region 2 which are between semiconductor elements.

Then, in substantially the same step as the formation of the field insulating film 3, a p-type channel stopper region 10 is formed in the main surface portion of the semiconductor substrate 1 below the field insulating film 3. The channel stopper region 10 is for preventing a parasitic MISFET and further electrically separating adjacent semiconductor elements.

Thereafter, as shown in FIG. 3, on the upper surface of the main surface of the semiconductor substrate 1 and the upper surface of the well region 2 which will be the semiconductor element forming region,
The insulating film 11 is formed. The insulating film 11 is, for example, a silicon oxide film formed by a thermal oxidation technique so as to form a gate insulating film of MISFET.

After the step shown in FIG. 3, the conductive layer 4A for forming the floating gate electrode is formed on the insulating film 11 in the memory cell formation region MC, and the n-channel MISFETQn formation region N is formed.
Insulating film 11 of M, HNM and p channel MISFETQp formation region PM
A conductive layer 4 serving as a gate electrode is formed on the top.

The conductive layers 4 and 4A are formed by the first conductive layer forming step in the manufacturing process, use a polycrystalline silicon film by the CVD technique, and use a polycrystalline silicon film subjected to phosphorus treatment.

This phosphorus processing is performed in order to increase the operating speed of EPROM.
Set to a low resistance value of about 2 [Ω / □].

Then, as shown in FIG. 4, an insulating film 12 is formed to cover the conductive layers 4 and 4A. As the insulating film 12, for example, a silicon oxide film formed by a thermal oxidation technique is used.

After the step shown in FIG. 4, as shown in FIG. 5, a semiconductor is formed in the n-channel MISFET formation region HNM through the insulating film 12 on both sides of the conductive layer 4 to form a double drain structure. An n-type impurity 13A is selectively introduced into the main surface portion of the substrate 1. This impurity 13A is, for example, 1 × 10 ¹³ [atoms / c
It is introduced by the ion implantation technique with an energy of about 50 [KeV] using phosphorus ions of about [m ² ].

After the step shown in FIG. 5, the impurity 13A is stretched and diffused to form an n ⁻ type semiconductor region 13.

Then, in order to form the control gate electrode of the memory cell, the voltage control MISFET, and the resistance element so as to cover the entire surface, the conductive layer 5A whose resistance value can be varied by introducing impurities is formed. The conductive layer 5A is formed by the second conductive layer forming step in the manufacturing process. The conductive layer 5A is, for example, a polycrystalline silicon film (no phosphorus is introduced) formed by the CVD technique, and has a film thickness of 3000 to 4000 [angstrom (hereinafter referred to as A)].
Form with a degree.

After that, an impurity introduction mask 14 is selectively formed on the conductive layer 5A in the voltage control MISFET formation region CM and the resistance element formation region R so that the phosphorus treatment is not performed. The mask 14 is formed of, for example, a silicon oxide film formed by a CVD technique and has a film thickness of about 3000 to 4000 [A].

Then, phosphorus treatment is applied using the mask 14 to form a conductive layer 5B into which phosphorus is introduced, as shown in FIG.
The conductive layer 5B has a thickness of 30 [Ω], similar to the conductive layers 4 and 4A.
/ □] is set to have a low resistance value. Conductive layer
5A is not phosphorus-treated, so 10 ¹¹ to 10 ¹² [Ω
/ □] is set to a high resistance value.

In the present embodiment, the phosphorus treatment employs a method of performing heat treatment in a phosphorus atmosphere to diffuse phosphorus.
A method of introducing phosphorus ions by an ion implantation technique and then performing heat treatment to diffuse phosphorus may be adopted.

After the step shown in FIG. 6, the mask 14 is selectively removed.

Then, in order to form the control gate electrode of the memory cell, the voltage control MISFET and the resistance element, the conductive layers 5A and 5B are subjected to predetermined patterning. That is, as shown in FIG. 7, the conductive layer 5C that has been subjected to the phosphorus treatment is formed in the memory cell formation region MC, and the voltage control MISFET formation region CM is formed.
In the resistance element forming region R, the conductive layer 5D not subjected to the phosphorus treatment is formed.

After the step shown in FIG. 7, the conductive layers 5C and 4A are selectively subjected to a predetermined patterning mainly in the memory cell formation region MC, and as shown in FIG. And a conductive layer 4B which will become the floating gate electrode. Then, in this step, the insulating film 11 other than the gate insulating film and the insulating film 12 covering the conductive layer 4 are removed.

After the step shown in FIG. 8, the insulating film 15 covering the conductive layers 4, 4B, 5E and 5D is formed.

In order to introduce an n-type impurity, a p-channel
An impurity introduction mask 16 is formed on the insulating film 15 in the MISFET Qp formation region PM, the voltage control MISFET formation region CM, and the resistance element formation region R. The mask 16 is, for example, a silicon nitride film formed by a CVD technique and has a film thickness of 1000 to 2000.
It is formed in the order of [A].

After that, using the mask 16, as shown in FIG. 9, the memory cell formation region MC, the n-channel MISFET Qn formation region NM, and the n-channel MISFET formation region HNM, and the conductive layers 4 and 4 are formed.
An n-type impurity 6A is introduced into the main surface portion of the semiconductor substrate 1 that has passed through the insulating films 15 on both sides of B and 5E. The impurities 6A are, for example, phosphorus ions of about 1 × 10 ¹⁴ [atoms / cm ² ] and 1 × 10 4.
50 [KeV] with arsenic ions of about ¹⁶ [atoms / cm ² ]
And ion implantation technology with an energy of about 80 [KeV].

After the step shown in FIG. 9, the impurity 6A is stretched and diffused to form an n ⁺ type semiconductor region 6.

As a result, the memory cell MC, the n-channel MISFETQn, and the n-channel MISFETQh having the double drain structure are
It is almost completed.

The memory cell MC is mainly composed of a semiconductor substrate 1, a conductive layer 4B that serves as a floating gate electrode, a conductive layer 5E that serves as a control gate electrode, insulating films 11 and 12 that serve as gate insulating films, and a pair of semiconductor regions 6. .

The n-channel MISFETQn is mainly composed of the semiconductor substrate 1, the conductive layer 4 serving as a gate electrode, and the insulating film 11 serving as a gate insulating film.
And a pair of semiconductor regions 6.

The n-channel MISFETQh is mainly composed of a semiconductor substrate 1, a conductive layer 4 serving as a gate electrode, an insulating film 1 serving as a gate insulating film.
1. It is composed of a pair of semiconductor regions 13 and a semiconductor region 6.

After that, the mask 16 is selectively removed.

Then, in order to introduce a p-type impurity, the memory cell formation region MC, the n-channel MISFET Qn formation region NM, the upper portion of the insulating film 15 in the n-channel MISFET formation region HNM and the voltage control M.
An impurity introduction mask 17 is formed on a predetermined upper portion of the insulating film 15 in the ISFET formation region CM. The mask 17 is, for example, a silicon oxide film formed by a CVD technique and has a film thickness of 2500 to 3500.
[Å] is formed.

Thereafter, using the mask 17, as shown in FIG. 10, in the p-channel MISFET Qp formation region PM, the well region 2 main surface portion through the insulating film 15 on both sides of the conductive layer 4, the voltage control MISF.
In the ET formation region CM, the conductive layer 5D main surface portion that passes through the insulating film 15 on both sides of the mask 17 and in the resistance element formation region R that passes through the insulating film 15 and in the conductive layer 5D main surface portion, p-type Impurity 7B is introduced. This impurity 7B is, for example, 1 × 10 ¹⁵ [atoms / cm
² ] Boron ions are used, and the ion implantation technique is performed with an energy of about 80 [KeV].

After the step shown in FIG. 10, an insulating film 18 is formed so as to cover the entire surface in order to electrically isolate the semiconductor element and the conductive layer formed on the semiconductor element. This insulating film 18 is, for example,
A phosphosilicate glass film by CVD technology is used.

Then, the impurity 7B is stretched and diffused to form the p ⁺ type semiconductor regions 7 and 7C and the conductive layer 5 to be the resistance element R, as shown in FIG.

As a result, the p-channel MISFET Qp and the resistance element R are almost completed.

The p-channel MISFETQp is mainly composed of the well region 2, the conductive layer 4 serving as a gate electrode, and the insulating film 11 serving as a gate insulating film.
And a pair of semiconductor regions 7.

The resistance element R is formed by introducing an impurity 7B for forming a source region or a drain region of the p-channel MISFET Qp into a conductive layer (polycrystalline silicon film) 5D not subjected to phosphorus treatment. Thereby, the resistance element R can be set to, for example, an intermediate resistance value of about several hundred [Ω / □].

After the step shown in FIG. 11, the insulating film 1 above the conductive layer 5 is predetermined.
5 and 18 are selectively removed to form connection holes 9A, and semiconductor regions 6, 7, 7A (not shown), and 7C insulating film on a predetermined upper portion
The connection holes 9B are formed by selectively removing 15, 18 or the insulating films 15, 18, and the mask 17.

Then, as shown in FIG. 12, the conductive layer 8 is formed on the insulating film 18 so as to be connected to the conductive layer 5 and the semiconductor region 6, 7, 7A or 7C through the connection hole 9A or 9B.

The conductive layer 8 is formed by the third conductive layer forming step in the manufacturing process, and is formed of, for example, an aluminum film by a vapor deposition technique.

As a result, the voltage control MISFET CM is almost completed.

The voltage control MISFET CM is composed of a conductive layer 5D, a conductive layer 8 serving as a gate electrode, insulating films 15, 17, 18 serving as a gate insulating film, and a pair of semiconductor regions 7C.

The EPROM of this embodiment is completed by these series of manufacturing steps. A protective film or the like may be formed after this.

As described above, according to the present Example I, the following effects can be obtained.

(1) By providing a polycrystalline silicon film which is not subjected to phosphorus treatment and introducing an impurity which forms a source region or a drain region of MISFET into the polycrystalline silicon film, it is higher than that which is subjected to phosphorus treatment. It is possible to obtain a medium resistance polycrystalline silicon film having a resistance value.

(2) According to the above (1), since the resistance element can be formed by the polycrystalline silicon film of medium resistance, the area required for the resistance element can be reduced.

(3) Since the area required for the resistance element can be reduced by the above (2), the area required for the electrostatic breakdown prevention circuit can be reduced.

(4) Due to the above (2) and (3), the degree of integration of the semiconductor integrated circuit device can be improved.

(5) A mask for preventing the phosphorus treatment of the high resistance polycrystalline silicon film by forming the medium resistance polycrystalline silicon film in the manufacturing process of the semiconductor integrated circuit device having the high resistance polycrystalline silicon film. Can be used in the same step, so that the number of manufacturing steps can be reduced.

(6) Since the polycrystalline silicon film of medium resistance can be introduced in the same process as the impurity forming the source region or the drain region of the MISFET, the number of manufacturing processes can be reduced.

Example II In Example I, the example in which the polycrystalline silicon film having the medium resistance is formed by the impurities forming the source region or the drain region of the p-channel MISFET has been described.
An example of forming a polycrystalline silicon film of medium resistance with impurities forming the source region or drain region of the n-channel MISFET will be described.

FIG. 13 and FIG. 14 are cross-sectional views of the essential parts of the EPROM in each manufacturing process for explaining the manufacturing method of the embodiment II of the present invention.

First, after the step shown in FIG. 8 of Example I, an insulating film 15 is formed to cover the conductive layer 4 and the conductive layers 4B, 5E and 5D.

In order to introduce an n-type impurity, a p-channel
An impurity introduction mask 16 is formed on the insulating film 15 in the MISFET Qp formation region PM and the voltage control MISFET formation region CM.

After that, using the mask 16, as shown in FIG. 13, the memory cell formation region MC, the n-channel MISFET Qn formation region NM, and the n-channel MISFET formation region HNM, and the conductive layers 4 and 4 are formed.
B, 5E main surface portion of the semiconductor substrate 1 through the insulating film 15 on both sides,
An n-type impurity 6A is introduced into the main surface of the conductive layer 5D through the insulating film 15 in the resistance element forming region R in the same manner as in the step shown in FIG.

After the step shown in FIG. 13, the impurity 6A is stretched and diffused to form an n ⁺ type semiconductor region 6 and a conductive layer 5F to be the resistance element R.

Then, the mask 16 is selectively removed.

After that, in order to introduce the p-type impurity, the insulating film 1 in the memory cell formation region MC, the n-channel MISFETQn formation region NM, the n-channel MISFET formation region HNM, and the resistance element formation region R is formed.
5. An impurity introduction mask 17 is formed on a predetermined upper portion of the insulating film 15 in the upper portion and the voltage control MISFET formation region CM.

Thereafter, using the mask 17, as shown in FIG. 14, in the p-channel MISFET Qp formation region PM, the well region 2 main surface portion through the insulating film 15 on both sides of the conductive layer 4, the voltage control MISF.
In the ET formation region CM, p-type impurities 7B are introduced into the main surface portion of the conductive layer 5D passing through the insulating film 15 on both sides of the mask 17.

After the step shown in FIG. 14 is performed, the steps after the step shown in FIG.
Is completed.

Note that phosphorus ions and arsenic ions may be sequentially introduced into the conductive layer 5D serving as the resistance element R, or either one of the impurities may be introduced.

When the resistance element R is formed in the first conductive layer forming step in the manufacturing process, the resistance element may be formed of the impurity 13A for forming the double drain structure.

Further, as the impurities forming the source region or the drain region of the MISFET, one of the p-type impurities 7B and the n-type impurities 6A, 13A may be combined to form the resistance element.

As described above, according to the present Example II, it is possible to obtain substantially the same effect as that of the Example I.

[Example III] In Examples I and II described above, the resistance element of the electrostatic breakdown prevention circuit was formed, but in this Example III, the resistance element of the circuit other than the electrostatic breakdown prevention circuit was formed. An example will be described.

FIG. 15 is an equivalent circuit diagram showing an EPROM delay circuit for explaining a third embodiment of the present invention, and FIG. 16 is an embodiment of the present invention.
FIG. 4 is an equivalent circuit diagram showing a high voltage determination circuit of an EPROM for explaining III.

In FIG. 15, R ₁ is a resistance element, which is provided between the output section of the preceding inverter circuit and the input section of the latter inverter circuit. The resistance element R ₁ is for delaying the output signal of the preceding inverter circuit.

The resistance element R ₁ is formed by introducing an impurity forming a source region or a drain region of the MISFET into a polycrystalline silicon film which is not subjected to phosphorus treatment, as in the case of the embodiment I or II.

P-In is an input signal terminal and is connected to the input section of the inverter circuit at the preceding stage.

In FIG. 16, BP ₁ is an external terminal, and is a high voltage (for example, Vpp = 12.5) that is a write voltage to the EPROM memory cell.
[V] level) is applied.

R ₂ is the resistance element, Q _R is MISFET used as resistor, Q _D is the MISFET of depletion type.

The high voltage determination circuit is composed of a resistance element R ₂ , MISFETQ _R , Q _D and an inverter circuit. This high voltage determination circuit is for knowing whether the high voltage applied to the external terminal BP ₁ is higher than a predetermined voltage level. The voltage value V _B, which is the resistance division of the resistance element R ₂ and the MISFET Q _R , is lowered, and the magnitude relationship between the voltage V _B and the logic threshold voltage V _T of the inverter circuit is known from the output level of the inverter circuit. Since the relationship between the R ₂ and Q _R is unchanged, it is possible to know the level of high voltage.

The resistance element R ₂ is formed by introducing an impurity for forming a source region or a drain region of a MISFET into a polycrystalline silicon film which has not been subjected to phosphorus treatment, as in the case of the embodiments I and II.

Since this resistance element R ₂ can easily form a resistance value of about several hundred [Ω / □], the resistance value is too high to use the parasitic MISFET and cannot be determined, for example, a high voltage of about 12 [V]. The level of voltage can be determined.

Note that BP ₁ does not have to be an external terminal,
A high voltage Vpp (= 12.5 [V]) obtained by boosting the power supply voltage Vcc (= 5.0 [V]) in the OM chip may be applied.

As described above, according to the present Example III, it is possible to obtain substantially the same effect as that of the above-described example, and also obtain the effects described below.

(1) Since the area required for the resistance element can be reduced, the area required for the delay circuit can be reduced.

(2) Since the area required for the resistance element can be reduced, the area required for the high voltage determination circuit can be reduced.

(3) Due to the above (1) and (2), the degree of integration of the semiconductor integrated circuit device can be further improved.

[Effects] As described above, according to the novel technical means disclosed in the present application, the effects described below can be obtained.

(1) By providing a polycrystalline silicon film which is not subjected to phosphorus treatment and introducing an impurity which forms a source region or a drain region of MISFET into the polycrystalline silicon film, it is higher than that which is subjected to phosphorus treatment. It is possible to obtain a medium resistance polycrystalline silicon film having a resistance value.

(2) According to the above (1), since the resistance element can be formed by the polycrystalline silicon film of medium resistance, the area required for the resistance element can be reduced.

(3) Since the area required for the resistance element can be reduced by the above (2), the area required for the electrostatic breakdown prevention circuit can be reduced.

(4) Since the area required for the resistance element can be reduced by the above (2), the area required for the delay circuit can be reduced.

(5) Since the area required for the resistance element can be reduced by the above (2), the area required for the high voltage determination circuit can be reduced.

(6) Due to the above (3) to (5), the degree of integration of the semiconductor integrated circuit device can be improved.

(7) A mask for preventing the phosphorus treatment of the high-resistance polycrystalline silicon film by forming the medium-resistance polycrystalline silicon film in the manufacturing process of the semiconductor integrated circuit device having the high-resistance polycrystalline silicon film Can be used in the same step, so that the number of manufacturing steps can be reduced.

(8) Since the polycrystalline silicon film of medium resistance can be introduced in the same process as the impurity forming the source region or the drain region of the MISFET, the number of manufacturing processes can be reduced.

Although the invention made by the present inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Of course, you can do that.

For example, although the embodiment has been described with respect to an example in which the present invention is applied to an EPROM, it can be applied to a semiconductor integrated circuit device using a polycrystalline silicon film other than that as a resistance element.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram showing an input portion of an EPROM for explaining an embodiment I of the present invention, FIG. 2 is a plan view showing a specific configuration of FIG. 1, FIG. 3 and FIG. FIG. 13 is a sectional view of an essential part of an EPROM in each manufacturing step for explaining the manufacturing method of Embodiment I of the present invention, and FIGS. 13 and 14 are for explaining the manufacturing method of Embodiment II of the present invention. FIG. 15 is an equivalent circuit diagram showing a delay circuit of the EPROM for explaining the embodiment III of the present invention, and FIG. 16 is a sectional view of the embodiment III of the present invention. FIG. 4 is an equivalent circuit diagram showing a high voltage determination circuit of an EPROM for explaining. In the figure, 1 ... Semiconductor substrate, 2 ... Well region, 3 ... Field insulating film, 4, 4A, 4B, 5, 5A to 5F, 8, 8A to 8F ... Conductive layer, 6, 7, 7A, 7C, 13 ... Semiconductor area,
6A, 7B, 13A …… impurities, 9A, 9B …… connection holes, 10 …… channel stopper region, 11,12,15,18 …… insulating film, 1
4, 16, 17 …… Mask, BP …… External terminal, Q …… MISFE
T, R ... Resistance element, Vcc, Vss ... Voltage terminal, P ... Terminal.

Claims (1)

[Claims] 1. A semiconductor integrated circuit device, comprising a polycrystalline silicon film formed on one semiconductor substrate and a MISFET, wherein a desired circuit is constructed, wherein the polycrystalline silicon film is
A semiconductor integrated circuit device, comprising a resistance element of an electrostatic breakdown prevention circuit having a predetermined resistance value by introducing impurities by ion implantation for forming a source region or a drain region of a MISFET.