JPH0575068A - Semiconductor memory device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce the man-hour and lead time of manufacture of a semiconductor memory device. CONSTITUTION:Impurities such as phosphorus ions are implanted into the channel regions of memory transistors in a region 7 to form impurity diffused layers 9 and, at the same time, impurities such as phosphorus ions are implanted into the drain regions of peripheral transistors in a region 8 to form impurity diffused layers 10. That is, information is written in the memory transistors and, at the same time, the drain breakdown strengths of the peripheral transistors are improved. With this constitution, a process for improving the drain breakdown strengths of the peripheral transistors can be eliminated, so that the manufacturing man-hour can be reduced compared with the man-hour for a conventional constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read-only semiconductor memory device and a method of manufacturing the semiconductor memory device.

[0002]

5 to 10 are sectional views showing a method of manufacturing a conventional read-only semiconductor memory device in the order of steps. The semiconductor memory device is a memory transistor,
The peripheral transistor and the input resistance are formed in the memory transistor formation planned area 7, the peripheral transistor formation planned area 8 and the input resistance formation planned area 11, respectively.

First, as shown in FIG. 5, a device isolation insulating layer 2 is selectively formed on the surface of a semiconductor substrate 1 by a known method to form a memory transistor formation scheduled region 7, a peripheral transistor formation scheduled region 8 and The input resistance formation planned region 11 is separated into elements. Next, the photoresist film 6 having an opening in the molybdenum transistor formation planned region 7 is patterned on the semiconductor substrate 1 based on the information to be written in the channel region of the memory transistor. And
A channel dope impurity having a conductivity type opposite to that of the semiconductor substrate 1 is implanted into the surface of the semiconductor substrate 1. Thus, the impurity diffusion layer 9 to be the channel region is selectively formed on the surface of the semiconductor substrate 1 which is not covered with the photoresist film 6.

Next, as shown in FIG. 6, after the photoresist film 6 is removed, the gate insulating film 3 is formed on the semiconductor substrate 1 in the memory transistor formation planned region 7 and the peripheral transistor formation planned region 8 by a known method. And a gate electrode 4 made of polycrystalline silicon are selectively laminated. Then, using the gate insulating film 3 and the gate electrode 4 as a mask, the impurity diffusion layer 5 to be the source / drain regions of the MOS transistor is selectively formed on the surface of the semiconductor substrate 1.

Recently, in mask ROMs, a redundant circuit is provided to improve the yield, but in order to use this redundant circuit, it is necessary to blow a fuse formed of polycrystalline silicon. This fuse is cut by using a laser or electricity, and in particular, when electrically cutting the fuse, there is one that applies a voltage of about 7 V to the drain of the MOS transistor (IEEE, ISSCC, 1).
Published 989, p. 128). In order to apply such a high voltage to the drain, it is necessary to increase the breakdown voltage of the drain.

Therefore, as shown in FIG. 7, after forming the impurity diffusion layer 5, a photoresist film 6 having an opening in the peripheral transistor formation planned region 8 is formed, and the region except the drain region of the peripheral transistor is photoresist. An impurity such as phosphorus having a conductivity type opposite to that of the semiconductor substrate 1 is implanted by covering with the film 6. As a result, as shown in FIG. 8, the impurity diffusion layer 1 is formed in the drain region of the peripheral transistor formation planned region 8.
Form 0.

Further, in the mask ROM, when the original test mode is set, the input buffer is set to a ternary input, and the third input thereof has a high voltage which is not used by a general user, for example, about 10V. To use. For this reason,
In order to operate the input buffer stably, the breakdown voltage of the pn junction of the impurity diffusion layer 5 used as the input resistance is set to 3
It is necessary to make it higher than the input voltage of the value input buffer or make the drain breakdown voltage of the input protection transistor higher than the input voltage of the ternary input buffer.

Therefore, as shown in FIG. 9, after the impurity diffusion layer 5 is formed, a photoresist film 6 having an opening portion in the input resistance formation planned region 11 is formed, and the region except the input resistance formation planned region 11 is photo-treated. It is covered with a resist film 6, and impurities such as phosphorus having a conductivity type opposite to that of the semiconductor substrate 1 are implanted. As a result, as shown in FIG. 10, the impurity diffusion layer 12 is formed in the input resistance formation planned region 11.

[0009]

However, in the above-described conventional method for manufacturing a semiconductor memory device, the photolithography process and the ion implantation process are performed to write information in the memory transistor, and the breakdown voltage of the drain region of the peripheral transistor is increased. It is necessary to perform a photolithography process and an ion implantation process in order to increase the voltage, and to perform a photolithography process and an ion implantation process in order to increase the breakdown voltage of the pn junction of the input resistance. Therefore, there is a problem that the number of manufacturing steps of the semiconductor memory device increases and the manufacturing period becomes long.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor memory device capable of reducing the number of manufacturing steps and the manufacturing period, and a manufacturing method thereof.

[0011]

A semiconductor memory device according to the present invention has a memory transistor provided on a semiconductor substrate of a first conductivity type and a peripheral element for controlling a memory section provided on the semiconductor substrate. In a semiconductor memory device, first and second impurity diffusions formed in the same process by implanting a second conductivity type coating channel dope impurity into a channel region of the memory transistor and a pn junction of the peripheral element, respectively. It is characterized by having a layer.

Further, the method of manufacturing a semiconductor memory device according to the present invention comprises a step of selectively forming a gate insulating film and a gate electrode on a semiconductor substrate of the first conductivity type, and a source / drain on the surface of the semiconductor substrate. A step of selectively forming a region, and implanting a second conductivity type coating channel dope impurity into a channel region of a predetermined memory transistor through the gate electrode and the gate insulating film, and at the same time, a pn of a peripheral element for controlling a memory unit. And a step of implanting the coating channel dope impurity into the junction.

[0013]

In the semiconductor memory device according to the present invention, the first impurity diffusion layer is formed in the channel region of the memory transistor by implanting a channel doping impurity for coating having a conductivity type opposite to that of the semiconductor substrate. This sets the threshold value of the memory transistor. On the other hand, a second impurity diffusion layer is formed in the pn junction of the peripheral element by implanting the coating channel dope impurity, thereby increasing the breakdown voltage of the peripheral element. In this case, since the first and second impurity diffusion layers are formed in the same step, it is not necessary to add a step for increasing the breakdown voltage of the peripheral element, which is different from the conventional case. Therefore, the number of manufacturing steps of the semiconductor memory device can be reduced, and the manufacturing period can be shortened.

When the fuse made of polycrystalline silicon or the like is electrically cut to use the redundant circuit, a high voltage is applied to the transistor which is a peripheral element. Therefore, the second drain region of this transistor
It is preferable to form the impurity diffusion layer of to increase the breakdown voltage.

Further, in the method of manufacturing a semiconductor memory device according to the present invention, a gate insulating film, a gate electrode, and source / drain regions are provided in advance on a semiconductor substrate, and the gate insulating film and the gate are provided as necessary. A second conductivity type coating channel dope impurity is injected into a channel region of a predetermined memory transistor through an electrode, and at the same time, the coating channel dope impurity is injected into a pn junction of a peripheral element for controlling a memory part. Therefore, the TAT (turn aro
und time) can be shortened.

[0016]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

1 and 2 are cross-sectional views showing a method of manufacturing a semiconductor memory device according to the first embodiment of the present invention in the order of steps. In this semiconductor memory device, a memory transistor and a peripheral transistor are formed in a memory transistor formation planned area 7 and a peripheral transistor formation planned area 8, respectively.

First, as shown in FIG. 1, on the surface of a P-type semiconductor substrate 1 having an impurity concentration of, for example, about 1 × 10 ¹⁶ cm ^-3 , an element isolation insulating layer made of silicon oxide having a thickness of, for example, about 6000 Å. By selectively forming the layer 2, the memory transistor formation-scheduled region 7 and the peripheral transistor formation-scheduled region 8 are isolated. Next, the gate insulating film 3 made of silicon oxide having a thickness of, for example, about 250 Å is formed on the semiconductor substrate 1 in the memory transistor formation planned region 7 and the peripheral transistor formation planned region 8 by a known method.
A gate electrode 4 made of polycrystalline silicon having a thickness of, for example, about 3000 Å and having phosphorus diffused therein is selectively laminated. Next, by using the gate insulating film 3 and the gate electrode 4 as a mask, impurities such as arsenic are implanted into the surface of the semiconductor substrate 1 under the condition that the concentration is 5 × 10 ¹⁵ cm ^−2.
The impurity diffusion layer 5 to be the source / drain region of the S transistor is selectively formed. Next, the photoresist film 6 having an opening in the memory transistor formation-scheduled region 7 is patterned on the semiconductor substrate 1 based on the information to be written in the channel region of the memory transistor. At this time, if it is necessary to increase the breakdown voltage of the drain region of the peripheral transistor, an opening is selectively provided also in the peripheral transistor formation planned region 8 of the photoresist film 6. Then, an impurity such as phosphorus having a conductivity type opposite to that of the semiconductor substrate 1 has an energy of, for example, about 300 keV and a concentration of, for example, about 2 × 1.
It is implanted into the surface of the semiconductor substrate 1 under the condition of 0 ¹³ cm ^-2 .

As a result, as shown in FIG. 2, in the memory transistor formation-scheduled region 7, the impurity diffusion layer 9 serving as a channel region is selectively formed on the surface of the semiconductor substrate 1 in the portion not covered with the photoresist film 6. In the peripheral transistor formation-scheduled region 8, the impurity diffusion layer 10 is selectively formed in the drain region of the transistor.

In this embodiment, at the same time as writing information in the memory transistor, impurities such as phosphorus are implanted also in the drain region of the peripheral transistor. Therefore, in the peripheral transistor, the radius of curvature of the pn junction in the drain region increases and the concentration gradient becomes gentle, so that the depletion layer electric field in the drain region is relaxed and the drain breakdown voltage is improved from, for example, about 12V to 16V. .. Therefore, since it is not necessary to add a step for increasing the drain breakdown voltage of the peripheral transistor, the number of manufacturing steps can be reduced as compared with the conventional case. In particular, the implantation of the channel dope impurity for coating is performed after the gate electrode is formed, so that the TAT (turn around time) of the read-only semiconductor memory device can be shortened.

3 and 4 are sectional views showing a method of manufacturing a semiconductor memory device according to the second embodiment of the present invention in the order of steps. In this semiconductor memory device, a memory transistor and an input resistance are formed in the memory transistor formation planned area 7 and the input resistance formation planned area 11, respectively.

First, as shown in FIG. 3, element isolation insulation made of silicon oxide having a thickness of, for example, about 8000 Å is formed on the surface of a P-type semiconductor substrate 1 having an impurity concentration of, for example, about 1 × 10 ¹⁶ cm ^-3. By selectively forming the layer 2, the memory transistor formation-scheduled region 7 and the input resistance formation-scheduled region 11 are isolated. Next, by a known method, the gate insulating film 3 made of silicon oxide having a thickness of, for example, about 280 Å and the impurity such as phosphorus having a thickness of, for example, about 1500 Å are formed on the semiconductor substrate 1 in the memory transistor formation planned region 7. Implanted polycrystalline silicon and has a thickness of, for example, about 1
A gate electrode 4 made of tungsten silicide of 500 Å is selectively laminated. Next, by using the gate insulating film 3 and the gate electrode 4 as a mask, impurities such as arsenic are implanted into the surface of the semiconductor substrate 1 under the condition that the concentration is 8 × 10 ¹⁵ cm ⁻² , and thus the source / drain of the MOS transistor is formed. The impurity diffusion layer 5 to be the region is selectively formed. Next, the photoresist film 6 having an opening in the memory transistor formation-scheduled region 7 is patterned on the semiconductor substrate 1 based on the information written in the channel region of the memory transistor. At this time, if it is necessary to increase the breakdown voltage of the pn junction of the input resistance, an opening is selectively provided also in the input resistance formation planned region 11 of the photoresist film 6.
Then, an impurity such as phosphorus having a conductivity type opposite to that of the semiconductor substrate 1 has an energy of, for example, about 500 keV and a concentration of, for example, about 3 keV.
It is implanted into the surface of the semiconductor substrate 1 under the condition of × 10 ¹³ cm ^-2 .

As a result, as shown in FIG. 2, in the memory transistor formation-scheduled region 7, the impurity diffusion layer 9 serving as a channel region is selectively formed on the surface of the semiconductor substrate 1 which is not covered with the photoresist film 6. And the impurity diffusion layer 12 is formed deeper than the impurity diffusion layer 5 in the input resistance formation planned region 11.

In this embodiment, at the same time as writing information in the memory transistor, impurities such as phosphorus are injected into the input resistance. Therefore, in the input resistance, the depletion layer electric field at the pn junction is relaxed, and the junction breakdown voltage is, for example, about 7V to 12V.
Improve to V. Therefore, it is not necessary to add a step for increasing the breakdown voltage of the pn junction of the input resistance, so that the number of manufacturing steps can be reduced and the manufacturing period of the semiconductor memory device can be shortened as compared with the conventional case.

[0025]

As described above, according to the present invention, the channel region of the memory transistor and the pn junction of the peripheral element are each doped with the channel doping impurity for coating of the conductivity type opposite to that of the semiconductor substrate in the same step. As a result, the first and second impurity diffusion layers are formed, so there is no need to add a step for increasing the breakdown voltage of the pn junction of the peripheral element. Therefore, the number of manufacturing steps of the semiconductor memory device can be reduced, and the manufacturing period can be shortened.

In the method of manufacturing a semiconductor memory device according to the present invention, after the gate insulating film, the gate electrode and the source / drain regions are formed, the channel region of a predetermined memory transistor is passed through the gate insulating film and the gate electrode. To the pn junction of the peripheral element for controlling the memory section at the same time that the second conductivity type coating channel dope impurity is implanted into the T channel of the semiconductor element of the read-only semiconductor memory device.
AT can be shortened.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a mask state during impurity implantation in a method for manufacturing a semiconductor memory device according to a first example of the present invention.

FIG. 2 is a cross-sectional view showing a state after impurity implantation in the method for manufacturing the semiconductor memory device according to the first example of the present invention.

FIG. 3 is a cross-sectional view showing a mask state at the time of impurity implantation in the method of manufacturing a semiconductor memory device according to the second embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a state after impurity implantation in the method for manufacturing a semiconductor memory device according to the second embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a step of forming a channel region in a manufacturing method of a conventional semiconductor memory device.

FIG. 6 is a cross-sectional view showing a step of forming source / drain regions in a manufacturing method of a conventional semiconductor memory device.

FIG. 7 is a cross-sectional view showing a mask state at the time of implanting impurities in a manufacturing method of a conventional semiconductor memory device.

FIG. 8 is a cross-sectional view showing a state after impurity implantation in a conventional semiconductor memory device in a manufacturing method.

FIG. 9 is a cross-sectional view showing a mask state at the time of implanting impurities in a manufacturing method of a conventional semiconductor memory device.

FIG. 10 is a cross-sectional view showing a state after implanting impurities in a manufacturing method of a conventional semiconductor memory device.

[Explanation of symbols]

 1; semiconductor substrate 2; element isolation insulating layer 3; gate insulating film 4; gate electrodes 5, 9, 10, 12; impurity diffusion layer 6; photoresist film 7; memory transistor formation scheduled region 8; peripheral transistor formation scheduled region 11 ; Input resistance formation area

Claims (3)

[Claims] 1. A semiconductor memory device having a memory transistor provided on a semiconductor substrate of a first conductivity type and a peripheral element for controlling a memory section provided on the semiconductor substrate, wherein a channel region of the memory transistor and the A semiconductor memory device having first and second impurity diffusion layers formed in the same step by respectively implanting a second conductivity type coating channel dope impurity into a pn junction of a peripheral element. 2. The semiconductor memory device according to claim 1, wherein the peripheral element is a transistor. 3. A step of selectively forming a gate insulating film and a gate electrode on a first conductivity type semiconductor substrate, a step of selectively forming source / drain regions on the surface of the semiconductor substrate, and the gate. A second conductivity type coating channel doping impurity is implanted into a channel region of a predetermined memory transistor through the electrode and the gate insulating film, and at the same time, the coating channel doping impurity is implanted into a pn junction of a peripheral element for controlling a memory portion. A method of manufacturing a semiconductor memory device, comprising: