JPS6015973A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6015973A JPS6015973A JP58123267A JP12326783A JPS6015973A JP S6015973 A JPS6015973 A JP S6015973A JP 58123267 A JP58123267 A JP 58123267A JP 12326783 A JP12326783 A JP 12326783A JP S6015973 A JPS6015973 A JP S6015973A
- Authority
- JP
- Japan
- Prior art keywords
- input
- resistor
- output side
- input side
- protective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000009792 diffusion process Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000001681 protective effect Effects 0.000 abstract 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- 238000003860 storage Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明はゲート保菌回路を有する半導体装置に関し、特
に回路内に設けた入力保護抵抗の破壊耐圧の白土を図っ
た半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device having a gate holding circuit, and more particularly to a semiconductor device in which the breakdown voltage of an input protection resistor provided in the circuit is improved.
一般ＫＭＯ８）ランジスタを用いた半導体装置では、外
部の過大信号から内部回路を保護するために所謂ゲート
保護回路を設けている。例えば第１図はその一例であり
、半導体基板１上に設けた外部電極（電極バット）２と
内部回路３との間にポリシリコンにて形成した入力保護
抵抗４を接続し、更にこの抵抗４の一端にゲート６とド
レイン７を直結したＭＯＳ）ランジスタ５のソース８を
接続し保護ダイオードとしたものである。この抵抗４と
保護ダイオード５０作用によって入力信号に電圧降下を
生じさせ、内部回路への過大信号の入力防止を図って還
・る（特願昭５６−９５３５７号公報など）。General KMO8) Semiconductor devices using transistors are provided with a so-called gate protection circuit to protect internal circuits from excessive external signals. For example, FIG. 1 shows an example of this, in which an input protection resistor 4 made of polysilicon is connected between an external electrode (electrode bat) 2 provided on a semiconductor substrate 1 and an internal circuit 3. The source 8 of a MOS transistor 5, in which the gate 6 and drain 7 are directly connected, is connected to one end of the MOS transistor 5 to serve as a protection diode. A voltage drop is caused in the input signal by the action of the resistor 4 and the protection diode 50, and the input signal is prevented from being input to the internal circuit (Japanese Patent Application No. 56-95357, etc.).
ところで、これまでのこの種のゲート保菌回路に用いら
れている入力保護抵抗４は、ポリシリコン膜の厚さや不
純物のドープ貴等に基づいて単位面積当りの抵抗値をめ
、これから幅寸法（すなわち断面積）や長さを算出して
所定の抵抗値に設定されている。そして、計算上やパタ
ーニングの容易性等から、入力保護抵抗４は均一幅寸法
、換言すれば均一断面積のものとし又形成されて（・る
。By the way, for the input protection resistor 4 that has been used in this type of gate storage circuit so far, the resistance value per unit area is determined based on the thickness of the polysilicon film, the doping level of impurities, etc., and the width dimension (i.e. The cross-sectional area) and length are calculated and set to a predetermined resistance value. For reasons of calculation and ease of patterning, the input protection resistor 4 is formed to have a uniform width dimension, in other words, a uniform cross-sectional area.
どころか、本発明者の種々の検討によれば、このような
均−断面積の入力保護抵抗４を用いると、例えば静電ｑ
による過大信号が入力されたときには入力側、つまり電
極バッド２に近い側の部分で抵抗４に静電破壊が生じる
ことが多く、その信頼性が低くなるという問題が生じる
ことがあきらかになった。また、同様にｃＭｏｓ以外の
半導体装置にお℃・て入力保護抵抗に拡散抵抗を使用す
る保護回路にあっても、拡散断面績が均一であると入力
側において静電破壊が生じゃすいことがゎがっプこ。On the contrary, according to various studies conducted by the present inventor, if the input protection resistor 4 having such a uniform cross-sectional area is used, for example, the electrostatic charge q
It has become clear that when an excessive signal is input, electrostatic damage often occurs in the resistor 4 on the input side, that is, on the side close to the electrode pad 2, resulting in a problem of lower reliability. Similarly, even in a protection circuit that uses a diffused resistor as an input protection resistor in semiconductor devices other than cMOS, if the diffusion cross section is uniform, electrostatic damage may occur on the input side. Wappuko.
本発明の目的は入力保護抵抗の破壊耐圧を増大して破壊
を防止し、これによりゲルト保護回路ないし半導体装僅
全体の信頼性な向上することができる半導体装置を提供
することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which the breakdown voltage of an input protection resistor is increased to prevent breakdown, thereby improving the reliability of the gel protection circuit or the semiconductor device as a whole.
本発明の前記ならび忙そのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかＫなるであ
ろう。The foregoing and other objects and novel features of the present invention include:
It will be clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、入力保護抵抗の単位長さあたりの抵抗値を出
力側に較べて入力側で大きくするためその断面積を出力
側に較べて入力側で大きくすることにより、入力側の破
壊耐圧を大きくし、これにより入力側な℃・し抵抗全体
での破壊を防止して信頼性の向上を達成するものである
。In other words, by making the resistance value per unit length of the input protection resistor larger on the input side than on the output side, and by making the cross-sectional area larger on the input side than on the output side, the breakdown voltage on the input side can be increased. This prevents damage to the entire input-side temperature resistor and improves reliability.
〔実施例１〕
第２図は本発明をＣＭＯＳ構成の半導体装置に適用した
実施例で、第３図はその等価回路図である。図示のよう
ＫＰチャネルＭＯ８）ランジヌタ、ＮチャネルＭＯ８Ｉ
−ランジスタからなるＣＭＯＳ構成の内部回路１２を形
成した半導体基板工ｌの一部にはＡ１ 材料等からなる
方形の外部電極端子（電極バンド）１３を形成し、この
電極バッド１３と前記内部回路１２との間にゲート保＝
ｉ回路１４を設けている。ゲート保贋回路１４はポリシ
リコン膜にて形成した入力保護抵抗１５と、ＭＯＳ）ラ
ンジスタを利用した保簡ダイオードＩ６とで構成してい
る。[Embodiment 1] FIG. 2 shows an embodiment in which the present invention is applied to a semiconductor device having a CMOS configuration, and FIG. 3 is an equivalent circuit diagram thereof. KP channel MO8) lunge nut, N channel MO8I as shown
- A rectangular external electrode terminal (electrode band) 13 made of A1 material or the like is formed on a part of the semiconductor substrate processing l on which the internal circuit 12 of the CMOS configuration consisting of a transistor is formed, and this electrode pad 13 and the internal circuit 12 are formed. Gate guard between =
An i-circuit 14 is provided. The gate protection circuit 14 includes an input protection resistor 15 made of a polysilicon film and a protection diode I6 using a MOS transistor.
前記入力保ｎＨＱ抵抗１５ばつづら折り状にパターニン
グしたポリシリコン膜からなり、その入力側ｌｒａ １
５ ａはコンタクトホール１７を介して前記電極バッド
１３に接続される。また、出力側端１５ｂはＡｌ 配置
２３を通して前記内部回路の例えばゲートに接続され、
他方Ａ） 配線２２を通して保護ダイオード１６に接続
される。保護ダイオード１６は、ソー７１８、ポリシリ
コン膜からなるゲート１９、ドレ・ｆン２０を方形枠状
に形成したＭＯＳトランジスタからｔ、Ｃす、ゲート１
９とドレイン２０をＡｌ 配線２１によって一体的に４
通接続した上で、ソース１９をＡ１ 配置９：ｊｉ！
２２を介して前記抵抗１５の出力（ｉｌｌ団１．１他方
１５ｂに接続している。The input holding nHQ resistor 15 is made of a polysilicon film patterned in a zigzag shape, and the input side lra 1
5 a is connected to the electrode pad 13 through a contact hole 17 . Further, the output side end 15b is connected to, for example, the gate of the internal circuit through the Al arrangement 23,
The other side A) is connected to the protection diode 16 through the wiring 22. The protection diode 16 is connected to a MOS transistor in which a saw 718, a gate 19 made of a polysilicon film, and a drain 20 are formed in a rectangular frame shape.
9 and drain 20 are integrally connected to 4 by Al wiring 21.
After connecting the source 19 to A1 Arrangement 9: ji!
22 is connected to the output of the resistor 15 (1.1 to the other 15b).
そして、前記入力保に’ＴＩ抵抗１５はポリシリコン膜
内へ不純物をドープする等によって適宜の比抵抗ρに調
整される。そして、ポリシリコン膜の幅寸法Ｗｔ ９ｗ
ｔ 、Ｗ３を入力’ｆＪＩ！１４’：Ｍ １５ ａがら
出力側端１５ｂ□□□向かって折曲する毎に低減させて
いる。換言すれば、ポリシリコン膜の厚さが均一である
ことから、その断面積が出力側よりも入力（１４１＋で
大きくなるように形成しても・るのである。この結果、
抵抗１５の単位長さあたりの抵抗値Ｒは入力側で小さく
出力（ｔｉｌｌで大きくなっている。すなわち、分布抵
抗の値が出力側で大きくなっている。Then, to maintain the input voltage, the TI resistor 15 is adjusted to have an appropriate resistivity ρ by doping impurities into the polysilicon film. And the width dimension Wt of the polysilicon film is 9w
t, input W3'fJI! 14': M 15a is reduced each time it is bent toward the output side end 15b□□□. In other words, since the thickness of the polysilicon film is uniform, it can be formed so that its cross-sectional area is larger on the input side (141+) than on the output side.As a result,
The resistance value R per unit length of the resistor 15 is small on the input side and large on the output side (till). That is, the value of the distributed resistance is large on the output side.
この構成によれば、電極バッド１３に過大信号が入力さ
れてこれがゲート保護回路１４、即ち入力保護抵抗１５
に印加されても、入力保護抵抗１５は入力側端１５ａに
おける断面積が大きく形成され℃いるのでその破壊耐圧
が向上されており、し。According to this configuration, an excessive signal is input to the electrode pad 13, and this is transmitted to the gate protection circuit 14, that is, the input protection resistor 15.
Since the input protection resistor 15 has a large cross-sectional area at the input side end 15a, even when the voltage is applied to the input resistor 15, its breakdown voltage is improved.
たがって入力側端における破壊は確実に防止される。ま
た、過大信号は入力保護抵抗１５内で順次電圧降下され
るので出力１１１］端１５ｂ、１５ｃの断面積が小さく
ても破壊されることは７１℃・。結局、入力保護抵抗１
５の破壊を防止し、これによりケ−ト保菌回路ないし半
導体装置全体の信頼性を向上できる。Therefore, breakage at the input side end is reliably prevented. Furthermore, since the excessive signal is sequentially voltage-dropped within the input protection resistor 15, the output 111 will not be destroyed even if the cross-sectional area of the terminals 15b and 15c is small. In the end, input protection resistor 1
5 is prevented from being destroyed, thereby improving the reliability of the gate storage circuit or the semiconductor device as a whole.
なお、入力保護抵抗１５は、ポリシリコン膜の幅寸法を
入力側から出力側に向かって連続的あるいは非連続的（
段階的）に低減させてもよく、またポリシリコン膜の厚
さを変化させることにより断面積を変化させるようにし
てもよい。Note that the input protection resistor 15 has a width dimension of the polysilicon film that is continuous or discontinuous (from the input side to the output side).
The cross-sectional area may be changed by changing the thickness of the polysilicon film.
〔実施例２〕
第４図は本発明をＣＭＯ８以外の例えばＮＭＯＳトラン
ジスタ措成の半導体装置に適用した例である。即ち、内
部回路ＫＣＭＯ３を使用しない装置ではラッチアップ等
の寄生素子現象の心配がなし・ことから入力保護抵抗に
所謂拡散抵抗を使用できる。したがって、図示のよ５＋
Ｃ半心体基板３１の主面に不純物のイオン打込みや拡散
によって入力保護抵抗３２を形成し、これに保護ダイオ
ード３３を接続してゲート保護回路３４を４１り成した
上で電極パッド３５と内部回路３６の間に接続している
。[Embodiment 2] FIG. 4 is an example in which the present invention is applied to a semiconductor device other than CMO8, such as an NMOS transistor structure. That is, in a device that does not use the internal circuit KCMO3, a so-called diffused resistor can be used as the input protection resistor since there is no concern about parasitic element phenomena such as latch-up. Therefore, as shown in the figure, 5+
An input protection resistor 32 is formed on the main surface of the C half-core substrate 31 by ion implantation or diffusion of impurities, and a protection diode 33 is connected to this to form a gate protection circuit 34. It is connected between the circuits 36 and 36.
前記入力保Ｒ′〉抵抗１５は保設ダイオード３３を構成
スるＭＯＳ）ランジスタのソース３７、ト°レイン３８
の各領域と同時に形成し、特にソース３７とは直接接続
された状態にある。またこのソース３７にはＡｌ配線３
９を接続して内部回路３６に接続して℃・る。ポリシリ
コン等にて形成したゲート４０はドレイン３８と共に所
定レベル例えば接地電位に接続される。そして、このよ
うに形成した入力保護抵抗３２は入力側端３２ａから出
力側端３２ｂに向かって幅寸法を徐々に低減させ、断面
積が出力側よりも入力側で増大するように構成している
のである。The input protection resistor 15 is connected to the source 37 and train 38 of a MOS transistor that constitutes the storage diode 33.
It is formed at the same time as each region, and in particular, it is directly connected to the source 37. Also, this source 37 has an Al wiring 3
9 and connect it to the internal circuit 36. A gate 40 formed of polysilicon or the like is connected together with a drain 38 to a predetermined level, for example, ground potential. The input protection resistor 32 formed in this manner is configured such that the width dimension gradually decreases from the input side end 32a toward the output side end 32b, and the cross-sectional area increases on the input side than on the output side. It is.
したがって、本実施例の入力保護抵抗３２にあっても入
力側端３２ａの破壊耐圧を太きくシ、入力側ないし出力
側にわたっての破壊を防止して信頼性の向上を達成する
ことができる。本例に牙ｄ℃・ても、抵抗３２０幅やそ
の拡散深さを連続的あるいは段階的に変化させて断面積
を変化させるようにしてもよ〜・。Therefore, even in the input protection resistor 32 of this embodiment, it is possible to increase the breakdown voltage of the input side end 32a, prevent breakdown across the input side or the output side, and improve reliability. In this example, the width of the resistor 320 and its diffusion depth may be changed continuously or stepwise to change the cross-sectional area.
（１）入力保護抵抗の断面積を入力側で大きく、出力側
で小さくしているので、特に入力側でその破壊耐圧を高
めることができ、入力側ないし出力側での破壊を防止し
てゲート保設回路および半導体装置全体の信頼性を向上
できる。(1) Since the cross-sectional area of the input protection resistor is large on the input side and small on the output side, the breakdown voltage can be particularly increased on the input side, preventing breakdown on the input or output side and The reliability of the storage circuit and the entire semiconductor device can be improved.
（２） ポリシリコン膜の幅寸法を入力側で大きく、出
力（ＩＩＩで小さくして（・るので、パターニングの際
のパターンを若干変更するだけで抵抗を半成でき、製造
工程を従来と相異させる必要は全くない。(2) The width of the polysilicon film is made larger on the input side and smaller on the output side (III), so half the resistor can be formed by slightly changing the pattern during patterning, making it possible to integrate the manufacturing process with the conventional one. There is no need to make any difference.
（３）拡散抵抗にお（・てもイオン打込みや拡散のパタ
ーンを変えるだけでよ（、製造工程を増やす必要もな見
・。(3) Diffusion resistor can be changed by simply changing the ion implantation and diffusion patterns (there is no need to increase the manufacturing process).
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しな〜・範囲で種々変更
可能であることは（・うまでもない。たとえば、保菌抵
抗の入力側と出力側の単位長さあたりの抵抗値を変える
手段として他の手段例えば比抵抗を変える方法を用−・
でも良い。また入力側と出力側の断面積の変化割合は、
必要とされる抵抗値に応じて適宜変化できる。Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above examples, and can be modified in various ways without departing from the gist thereof. For example, as a means to change the resistance value per unit length on the input side and output side of the storage resistor, other means such as a method of changing specific resistance can be used.
But it's okay. Also, the rate of change in the cross-sectional area on the input side and output side is
It can be changed as appropriate depending on the required resistance value.
以上の説明では主として本発明者によってなされた発明
をその背景とかった利用分野であるＭＯ８型半導体装置
に適用した場合につ（・てＭＱ明しブこが、それに限定
されるものではなく、ＭＩＳ型ある〜・はバイポーラ型
等の半導体装置にも適用することができる。The above explanation will mainly be based on the case where the invention made by the present inventor is applied to the MO8 type semiconductor device, which is the application field based on the background of the invention. The MIS type can also be applied to bipolar type semiconductor devices.
第１図は従来装置の一部の平面図、 第２図は本発明装置の要部の平面図、 第３図は等価回路図。 第４図は他の実施例の要部平面図である。 Figure 1 is a plan view of a part of the conventional device. FIG. 2 is a plan view of the main parts of the device of the present invention; Figure 3 is an equivalent circuit diagram. FIG. 4 is a plan view of main parts of another embodiment.
Claims (1)
を宿成し、過大入力に対して内部回路の保菌を図ってな
る半導体装置にお（・て、前記入力保護抵抗の単位長さ
あたりの抵抗値を内部回路に接続される出力側よりも過
大入力が入力され得る入力側で太き（形成したことを特
徴とする半導体装置。 ２、入力保に５抵抗をポリシリコン膜で形成し、その幅
寸法を出力側よりも入力側で大きくしてなる特許請求の
範囲第１項記載の半導体装置。 ３、入力保護抵抗を不純物の拡散層で形成し、その幅寸
法や拡散深さを出力側よりも入力側で太き（してなる特
許請求の範囲第１項記載の半導体装置。[Scope of Claims] 1. In a semiconductor device in which a gate protection circuit is formed by an input protection resistor and a protection diode, and the internal circuit is maintained against excessive input. A semiconductor device characterized in that the resistance value per unit length is thicker on the input side to which an excessive input can be inputted than on the output side connected to the internal circuit. 2. The semiconductor device according to claim 1, which is formed of a silicon film and whose width is larger on the input side than on the output side. 3. The input protection resistor is formed with an impurity diffusion layer, and its width is larger on the input side than on the output side. The semiconductor device according to claim 1, wherein the diffusion depth is thicker on the input side than on the output side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58123267A JPS6015973A (en) | 1983-07-08 | 1983-07-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58123267A JPS6015973A (en) | 1983-07-08 | 1983-07-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6015973A true JPS6015973A (en) | 1985-01-26 |
Family
ID=14856329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58123267A Pending JPS6015973A (en) | 1983-07-08 | 1983-07-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6015973A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6242454A (en) * | 1985-08-19 | 1987-02-24 | Sanyo Electric Co Ltd | Input protecting circuit |
| JPS6254458A (en) * | 1985-09-03 | 1987-03-10 | Toshiba Corp | Input protecting circuit |
| JPH09293836A (en) * | 1996-04-25 | 1997-11-11 | Rohm Co Ltd | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5877252A (en) * | 1981-11-02 | 1983-05-10 | Hitachi Ltd | Input protective circuit device |
-
1983
- 1983-07-08 JP JP58123267A patent/JPS6015973A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5877252A (en) * | 1981-11-02 | 1983-05-10 | Hitachi Ltd | Input protective circuit device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6242454A (en) * | 1985-08-19 | 1987-02-24 | Sanyo Electric Co Ltd | Input protecting circuit |
| JPS6254458A (en) * | 1985-09-03 | 1987-03-10 | Toshiba Corp | Input protecting circuit |
| JPH09293836A (en) * | 1996-04-25 | 1997-11-11 | Rohm Co Ltd | Semiconductor device |
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